I am have serious issues getting my DDR SDRAM to initialize properly.
Is there any documenation that outlines the basic steps required and what order to do it.
The memory controller I am using is a intel 855gme. I noticed in other intel source files lots of comments curse about the lack of documentation, I have noticed this as well. Does this mean that I probably won't get this to work?
I am really at a loss of what to do next. I am having a hard time debugging this, mostly because I don't exactly know what I need to do in the first place.
Any tips for getting ram to work correctly?
Thanks, Jon
I hate to say it, but you are going to probably have to give up on that chipset absent docs. I have the "DOCS" as intel ships them from developer.intel.com, and, unlike what you could get in 1999, the current set of docs are totally worthless for writing a BIOS. I am told this is intentional. I have had it put to me that this policy simplifies EFI lockin -- no competition.
Sorry
ron
Well that is a bummer, I was having fun (accompanied by frustration) trying to get this to work. Thanks for all the help I received up to this point.
Jon
On 11/29/06, ron minnich rminnich@gmail.com wrote:
I hate to say it, but you are going to probably have to give up on that chipset absent docs. I have the "DOCS" as intel ships them from developer.intel.com, and, unlike what you could get in 1999, the current set of docs are totally worthless for writing a BIOS. I am told this is intentional. I have had it put to me that this policy simplifies EFI lockin -- no competition.
Sorry
ron
I am have serious issues getting my DDR SDRAM to initialize properly.
Is there any documenation that outlines the basic steps required and what order to do it.
Sure there is -- see JESD-79, the DDR SDRAM spec.
Other than that, you'll have to use common sense, Intel's memory controller docs don't go into details (and their data sheets don't say _how_ to use the hardware ever, it seems).
The memory controller I am using is a intel 855gme. I noticed in other intel source files lots of comments curse about the lack of documentation, I have noticed this as well. Does this mean that I probably won't get this to work?
You'll need quite some time, and a good understanding of how DDR SDRAM works. Read the data sheets, and try to put the puzzle together from every little scrap of information you can find. It can be done, DDR-I isn't *that* hard.
I am really at a loss of what to do next. I am having a hard time debugging this, mostly because I don't exactly know what I need to do in the first place.
Any tips for getting ram to work correctly?
Start with a single DIMM, one rank (i.e., a single-sided DIMM). Decode the SPD on it and use the slowest valid setting first. Hardcode all values until you have something working, only then start doing generic memory initialisation. It helps using ECC memory (the ECC checker will tell you when your settings are seriously wrong). Make sure you program the MRS registers properly. Don't despair (although that would be a rational plan sometimes, heh). Use a good oscilloscope if you can.
Segher
Jon Dufresne wrote:
I am really at a loss of what to do next. I am having a hard time debugging this, mostly because I don't exactly know what I need to do in the first place.
Any tips for getting ram to work correctly?
As Ron said, Without docs you have a very hard road ahead.
The following JEDEC document may help you somewhat understand what is going on. It pretty heavy reading though.
Free but you have to register with the jedec site to get to the downloads.
JESD79E DOUBLE DATA RATE (DDR) SDRAM SPECIFICATION:
The mfg datasheets and app notes for the ram chips on your DIMM may also help you understand what you need to do to make the ram talk.
Good luck.
Free but you have to register with the jedec site to get to the downloads.
Actually, direct links to the pdfs work just fine. Just use Google ;-)
The mfg datasheets and app notes for the ram chips on your DIMM may also help you understand what you need to do to make the ram talk.
You can use any other manufacturer's datasheets too, all DDR chips are (supposedly) compatible (within the bounds of the JEDEC spec -- there can be different timings, etc.)
Good luck.
Well at least for DDR-I only luck is needed, no divine intervention required like with DDR-II :-)
Segher