Hi everyone.
I'm a bit stuck on this. As I've said before in other emails here, I'm trying to bring up an AsRock FM2A88X+ with coreboot. I've used as a model the code for the a88xm-e and accomplished my first goal, which was to have a working UART, but I need to boot with the original AMI BIOS first (first boot after mechanical off) for it to work.
The problem seems to be the 48 MHz clock that SB feeds to the SIO. Coreboot's a88xm-e code has the code to configure it early, in sbxxx_enable_48mhzout, and so have I, but I've checked it with an oscilloscope and there's no clock there,
So I turned to the docs. Regarding that clock, we can read,
"The USBCK/14M_25M_48M_OSC pin (G8) as well as the 14M_25M_48M_OSC pin (J26) output a 14.318MHz clock on the first power up if the internal system clock generator mode strap is selected. [1]
14M_25M_48M_OSC is the pin we are interested in. From what I see on the boardfile, the strap is configured as internal system clock.
Later,
"The output will generate 12.5 MHz on power up after the FCH PWR_GOOD is asserted. The output frequency will be 12.5 MHz until the internal PLL is initialized after which time the output will switch to 14.318 MHz clock." [2]
So, it seems that, after the FCH PWR_GOOD and *without any firmware intervention*, we should get 12.5 MHz on that pin. I've checked it with the original AMI BIOS and that's correct, ~150 ms after the assertion of PWR_GOOD we get the 12.5 MHz clock. On the other hand, with my coreboot image, FCH PWR_GOOD is asserted, but there is no clock.
From what I said, I deduce that the AMI BIOS must be doing something that I do not, but, as I understand the databook, the 12.5 MHz should be *automatic* after a PWR_GOOD.
Maybe someone with more experience with AMD chipsets could help me here, especially considering that we have a working image with the same chipset.
I'd appreciate any hints or advice about how to proceed.
[1] Bolton Databook ( https://www.amd.com/system/files/TechDocs/Bolton_D2-D2H-D3-D4_Databook.pdf), Chapter 4, Table 13 [2] Bolton Databook, Chapter 6, Table 52
Hi,
On 07. 10. 22 22:16, Pedro Erencia wrote:
Hi everyone.
I'm a bit stuck on this. As I've said before in other emails here, I'm trying to bring up an AsRock FM2A88X+ with coreboot. I've used as a model the code for the a88xm-e and accomplished my first goal, which was to have a working UART, but I need to boot with the original AMI BIOS first (first boot after mechanical off) for it to work.
What SIO chip you have? Is it different? Do you have SIO datasheet? Maybe it is strapped to something else than 48MHz input. Like you are outputing clocks from chipset and at the same time you are outputting something from SIO. That would explain you don't see it.
I would suggest to have a look to all SIO registers (especially those which are powered on through 5V standby) and including undocumented bits of that SIO registers.
You can also try to have a look to early SEC stage of original BIOS to see what it is doing early.
Thanks, Rudolf
The problem seems to be the 48 MHz clock that SB feeds to the SIO. Coreboot's a88xm-e code has the code to configure it early, in sbxxx_enable_48mhzout, and so have I, but I've checked it with an oscilloscope and there's no clock there,
So I turned to the docs. Regarding that clock, we can read,
"The USBCK/14M_25M_48M_OSC pin (G8) as well as the 14M_25M_48M_OSC pin (J26) output a 14.318MHz clock on the first power up if the internal system clock generator mode strap is selected. [1]
14M_25M_48M_OSC is the pin we are interested in. From what I see on the boardfile, the strap is configured as internal system clock.
Later,
"The output will generate 12.5 MHz on power up after the FCH PWR_GOOD is asserted. The output frequency will be 12.5 MHz until the internal PLL is initialized after which time the output will switch to 14.318 MHz clock." [2]
So, it seems that, after the FCH PWR_GOOD and *without any firmware intervention*, we should get 12.5 MHz on that pin. I've checked it with the original AMI BIOS and that's correct, ~150 ms after the assertion of PWR_GOOD we get the 12.5 MHz clock. On the other hand, with my coreboot image, FCH PWR_GOOD is asserted, but there is no clock.
From what I said, I deduce that the AMI BIOS must be doing something that I do not, but, as I understand the databook, the 12.5 MHz should be *automatic* after a PWR_GOOD.
Maybe someone with more experience with AMD chipsets could help me here, especially considering that we have a working image with the same chipset.
I'd appreciate any hints or advice about how to proceed.
[1] Bolton Databook (https://www.amd.com/system/files/TechDocs/Bolton_D2-D2H-D3-D4_Databook.pdf https://www.amd.com/system/files/TechDocs/Bolton_D2-D2H-D3-D4_Databook.pdf), Chapter 4, Table 13 [2] Bolton Databook, Chapter 6, Table 52
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Pedro Erencia -
Rudolf Marek