Re: [coreboot] Coreboot on X230 and Dualboot / How to make it work

[Peter Stuge]

(Please reply only to the list, rather than Cc:ing me. Your mailer
may have a list-reply plugin to automate that. Thanks a lot!)

One7two99 via coreboot wrote:
> One additional general question regarding the flashing on X230s.

As you document your experience, please investigate what is specific
for the X230, and what is not - and be clear in what you write.
(Most things are in no way X230-specific.)
> Most howtos include that it is sufficient to flash only the upper
> 4MB BIOS Chip and leave the 2nd 8 MB BIOS Chip untouched.

I would consider that bad advice, if coreboot.rom is 12 MB.

There are not "two BIOSes" just because there are two memory chips.

The two memory chips are mapped after each other and function as one
unit. The CPU sees them as one, and so should you.
> After creating my 12 MB Coreboot.rom I split it and use only 4MB
> for flashing.

So you flash only the last third of the CBFS, and ignore the beginning.

I think it is just luck that your system boots at all. If you used a
larger payload such as a kernel then your method will likely cut the
payload in half and end up writing incomplete junk to your flash.

You can compare it to deleting the first two thirds of a .zip file.
> As far as I understand the 2nd Chip include the Intel Mangement
> Engine (ME), shouldn't this chip also touched and (at least party)
> ME'cleaned?

There is no relation between coreboot and the ME. The main CPU and
the ME CPU are not very close to each other, and their respective
firmware have little to do with each other. They interface through
HECI. Neither will care what you do to the other.
> Or is the 2nd BIOS not used at all after flashing Coreboot to the
> top 4MB chip?

Please study the hardware you are working with. What software you put
in either memory is not relevant for how the hardware works, for how
the two memories are mapped to physical CPU addresses.

//Peter

Coreboot on X230 and Dualboot / How to make it work

[One7two99]

Hello Peter,
> -------- Original Message --------
> Subject: Re: [coreboot] Coreboot on X230 and Dualboot / How to make it work
> Local Time: September 25, 2017 1:25 AM
> From: [e-mail]
>
> As you document your experience, please investigate what is specific
> for the X230, and what is not - and be clear in what you write.
> (Most things are in no way X230-specific.)

yes, you are right most stuff is not X230-specific, but while I am currently learning how to flash my X230 I am collecting information from various sites.
From a newbie perspective I'd like to get this information from one or two locations:
1) How to get Coreboot running (general part)
2) How to flash the X230
> > Most howtos include that it is sufficient to flash only the upper
> > 4MB BIOS Chip and leave the 2nd 8 MB BIOS Chip untouched.
>
> I would consider that bad advice, if coreboot.rom is 12 MB.
> There are not "two BIOSes" just because there are two memory chips.
> The two memory chips are mapped after each other and function as one
> unit. The CPU sees them as one, and so should you.

Thanks, I know, what I've meant: there are two physical chips which are seen as one by the mainboard.
> > After creating my 12 MB Coreboot.rom I split it and use only 4MB
> > for flashing.
>
> So you flash only the last third of the CBFS, and ignore the beginning.
> I think it is just luck that your system boots at all. If you used a
> larger payload such as a kernel then your method will likely cut the
> payload in half and end up writing incomplete junk to your flash.

I've followed the howto in the coreboot wiki:
https://www.coreboot.org/Board:lenovo/x230#Hardware_Flashring

"(...)
Write the flash. Since you have to write only top 4M, first split out those 4M:
dd of=top.rom bs=1M if=build/coreboot.rom skip=8
(...)"

This is exactly what I have done, honestly I was also wondering why this is working and even more, why I am skipping the first 8MB of the file.
Can someone provide guidance how to split the generated 12 MB coreboot.rom file into two to flash them to the 1st (4MB) and 2nd (8MB)

to flash the 4MB chip (from the coreboot wiki):
dd of=chip4mb.rom bs=1M if=build/coreboot.rom skip=8

QUESTION:
what do I need to do to flash the 2nd (8MB) chip.
If the 1st chip contains the last 4MB of the file, I assume the correct command could be:
dd of=chip8mb.rom bs=1M if=build/coreboot.rom count=8

Is this correct? If this is right I'll add this to the wiki as soon as I have write permissions.
> > Or is the 2nd BIOS not used at all after flashing Coreboot to the
> > top 4MB chip?
>
> Please study the hardware you are working with. What software you put
> in either memory is not relevant for how the hardware works, for how
> the two memories are mapped to physical CPU addresses.

Honestly I am trying to understand as much as I can, but understanding more about coreboot need some knowledge I am just started to learn, while I knew what AMT is, I have never heard of EHCI.
The good thing is, that a good howto is often written or improved by an interested user, not the tech-power. As such I am happy to contribute to the documentation to make it easier for the next newbie who might not be interested in how his CPU works, but wants to reduce possible entry points which might break his privacy :-)

[799]