Re: [coreboot] How to add a new SuperIO ?

[ron minnich]

I took a look. I don't consider myself qualified to +2 but I added
reviewers who should be able to.

On Thu, Dec 29, 2016 at 4:50 AM Agrain Patrick <
[e-mail]> wrote:
> Hello all,
>
> I’ve pushed the code to support the EXAR SuperIO XR28V382.
>
> It is marked “[WIP]” with “XR28V382” in the title.
>
> Can anybody have a look at it and meaby point me to a bug, missing
> configuration or other… that could explain the messages on the console
> displayed below ?
>
> Thanks.
>
> Patrick Agrain
>
> *De :* coreboot [mailto:[e-mail]] *De la part de*
> Agrain Patrick
> *Envoyé :* jeudi 29 décembre 2016 09:43
> *À :* ron minnich; [e-mail]
>
> *Objet :* Re: [coreboot] How to add a new SuperIO ?
>
> Hi Ron,
>
> Thanks for the advice.
>
> It would be the first time that I will push code into a GIT project with
> Gerrit. Therefore, let me a few moment to gather all required information
> to perform this without disturbance for others.
>
> For the moment, I pulled the Coreboot project and add/modify the required
> files. Platform build is OK.
>
> Now, the push… if you have any checklist to follow, it could be helpful.
>
> Best regards,
>
> Patrick Agrain
>
> *De :* ron minnich [mailto:[e-mail] ]
> *Envoyé :* vendredi 16 décembre 2016 19:18
> *À :* Agrain Patrick; [e-mail]
> *Objet :* Re: [coreboot] How to add a new SuperIO ?
>
> it's way easier if you push your changes to gerrit marked as a WIP. People
> can see the code and will likely spot any problems very quickly.
>
> On Fri, Dec 16, 2016 at 12:40 AM Agrain Patrick <
> [e-mail]> wrote:
>
> Hi all,
>
> I'm trying to add a new superIO chip to the source tree.
> The chip is an EXAR XR28V932.
> I tried to take example of the existing superIO chips, like the i3100 and
> it8716 to compose a correct source tree as following:
> [agrain1@frilldlin059 coreboot]$ ls -als ./src/superio/exar/xr28v382/
> total 10
> 1 drwxr-xr-x 2 agrain1 dhs2  512 Dec 16 09:03 .
> 1 drwxr-xr-x 3 agrain1 dhs2  512 Dec 15 09:41 ..
> 1 -rw-r--r-- 1 agrain1 dhs2  687 Dec 15 09:34 Makefile.inc
> 3 -rw-r--r-- 1 agrain1 dhs2 2614 Dec 16 09:03 superio.c
> 2 -rw-r--r-- 1 agrain1 dhs2 1287 Dec 15 16:28 xr28v382.h
>
> I modified the devicetree.cb of my board (based on an Intel Mohon Peak) as
> following:
>                         device pci 1f.0 on end # LPC bridge
>                                 chip superio/exar/xr28v382 # Super I/O
>                                   device pnp 2e.0 on            # Com1
>                                         io 0x60 = 0x3f8
>                                         irq 0x70 = 4
>                                   end
>                                   device pnp 2e.1 off           # Com2
>                                   end
>                                   device pnp 2e.8 off           # Watchdog
>                                   end
>                                 end
>                         device pci 1f.3 on end # SMBus 0
>
> Now the output of the console log (DEBUG level):
> <...>
> PCI: pci_scan_bus for bus 00
> PCI: 00:00.0 [8086/1f0f] enabled
> PCI: Static device PCI: 00:01.0 not found, disabling it.
> child PNP: 002e.0 not a PCI device
> child PNP: 002e.1 not a PCI device
> child PNP: 002e.8 not a PCI device
> child PNP: 002e.0 not a PCI device
> child PNP: 002e.1 not a PCI device
> child PNP: 002e.8 not a PCI device
> child PNP: 002e.0 not a PCI device
> child PNP: 002e.1 not a PCI device
> child PNP: 002e.8 not a PCI device
> child PNP: 002e.0 not a PCI device
> <...>
> PCI: 00:1f.0 [8086/1f38] enabled
> child PNP: 002e.0 not a PCI device
> child PNP: 002e.1 not a PCI device
> child PNP: 002e.8 not a PCI device
> child PNP: 002e.0 not a PCI device
> child PNP: 002e.1 not a PCI device
> child PNP: 002e.8 not a PCI device
> child PNP: 002e.0 not a PCI device
> child PNP: 002e.1 not a PCI device
> child PNP: 002e.8 not a PCI device
> PCI: 00:1f.3 [8086/1f3c] enabled
> child PNP: 002e.0 not a PCI device
> <...>
> PCI: Left over static devices:
> PNP: 002e.0
> PNP: 002e.1
> PNP: 002e.8
> PCI: Check your devicetree.cb.
> PCI: pci_scan_bus for bus 01
> <...>
> DOMAIN: 0000 (Intel Rangeley Northbridge)
> PCI: 00:00.0 (Intel Rangeley Northbridge)
> PCI: 00:01.0 (Intel Rangeley Northbridge)
> PCI: 00:02.0 (Intel Rangeley Northbridge)
> PCI: 00:03.0 (Intel Rangeley Northbridge)
> PCI: 00:04.0 (Intel Rangeley Northbridge)
> PCI: 00:0b.0 (Intel Rangeley Southbridge)
> PCI: 00:0e.0 (Intel Rangeley Southbridge)
> PCI: 00:13.0 (Intel Rangeley Southbridge)
> PCI: 00:14.0 (Intel Rangeley Southbridge)
> PCI: 00:14.1 (Intel Rangeley Southbridge)
> PCI: 00:14.2 (Intel Rangeley Southbridge)
> PCI: 00:14.3 (Intel Rangeley Southbridge)
> PCI: 00:16.0 (Intel Rangeley Southbridge)
> PCI: 00:17.0 (Intel Rangeley Southbridge)
> PCI: 00:18.0 (Intel Rangeley Southbridge)
> PCI: 00:1f.0 (Intel Rangeley Southbridge)
> PNP: 002e.0 (EXAR XR28V382 Super I/O)
> PNP: 002e.1 (EXAR XR28V382 Super I/O)
> PNP: 002e.8 (EXAR XR28V382 Super I/O)
> PCI: 00:1f.3 (Intel Rangeley Southbridge)
> PCI: 00:0f.0 (unknown)
> PCI: 01:00.0 (unknown)
>
> I guess that the "" are not normal, isn't it ?
> And so the " Check your devicetree.cb." ?
> Moreover, I put a printk() in the init function of the chip and do not see
> it in the log.
> What particular point should I also check to be sure that I do not miss
> anything ?
>
> Thanks for your help.
> Best regards,
> Patrick Agrain