[commit] r6127 - in trunk/src: mainboard/asus/p2b northbridge/intel/i440bx/acpi southbridge/intel/i82371eb southbridge/intel/i82371eb/acpi
Author: ranma Date: Sat Nov 27 10:40:16 2010 New Revision: 6127 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6127
Log: After finding the missing bit poweroff works now. I cleaned up the patch and moved most of the dsdt.dsl and acpi_tables.c into the southbrige/northbridge directory. Updated patch should fix abuild error and incorporates suggestions on irc by uwe (thanks for the comments). Thanks to Idwer Vollering vidwer@gmail.com for the original patch.
Tested: Linux (poweroff, powerbutton event) XP (poweroff, powerbutton event)
Abuild-tested
Signed-off-by: Tobias Diedrich ranma+coreboot@tdiedrich.de Acked-by: Stefan Reinauer stepan@coreboot.org
Added: trunk/src/mainboard/asus/p2b/acpi_tables.c trunk/src/mainboard/asus/p2b/dsdt.asl trunk/src/northbridge/intel/i440bx/acpi/ trunk/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl trunk/src/southbridge/intel/i82371eb/acpi/ trunk/src/southbridge/intel/i82371eb/acpi/isabridge.asl trunk/src/southbridge/intel/i82371eb/acpi/pirq.asl trunk/src/southbridge/intel/i82371eb/acpi_tables.c trunk/src/southbridge/intel/i82371eb/i82371eb_fadt.c Modified: trunk/src/mainboard/asus/p2b/Kconfig trunk/src/mainboard/asus/p2b/devicetree.cb trunk/src/southbridge/intel/i82371eb/Makefile.inc trunk/src/southbridge/intel/i82371eb/chip.h trunk/src/southbridge/intel/i82371eb/i82371eb.h trunk/src/southbridge/intel/i82371eb/i82371eb_early_pm.c trunk/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c trunk/src/southbridge/intel/i82371eb/i82371eb_isa.c trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.c
Modified: trunk/src/mainboard/asus/p2b/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p2b/Kconfig Fri Nov 26 23:42:41 2010 (r6126) +++ trunk/src/mainboard/asus/p2b/Kconfig Sat Nov 27 10:40:16 2010 (r6127) @@ -28,6 +28,7 @@ select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256 + select HAVE_ACPI_TABLES
config MAINBOARD_DIR string
Added: trunk/src/mainboard/asus/p2b/acpi_tables.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asus/p2b/acpi_tables.c Sat Nov 27 10:40:16 2010 (r6127) @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Tobias Diedrich ranma+coreboot@tdiedrich.de + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/acpi.h> + +extern const unsigned char AmlCode[]; + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* mainboard has no ioapic */ + return current; +}
Modified: trunk/src/mainboard/asus/p2b/devicetree.cb ============================================================================== --- trunk/src/mainboard/asus/p2b/devicetree.cb Fri Nov 26 23:42:41 2010 (r6126) +++ trunk/src/mainboard/asus/p2b/devicetree.cb Sat Nov 27 10:40:16 2010 (r6127) @@ -54,6 +54,9 @@ register "ide0_drive1_udma33_enable" = "0" register "ide1_drive0_udma33_enable" = "0" register "ide1_drive1_udma33_enable" = "0" + register "thrm_polarity" = "1" + register "lid_polarity" = "1" + register "gpo" = "0x7fffbbff" end end end
Added: trunk/src/mainboard/asus/p2b/dsdt.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asus/p2b/dsdt.asl Sat Nov 27 10:40:16 2010 (r6127) @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Tobias Diedrich ranma+coreboot@tdiedrich.de + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) +{ + /* Define the main processor.*/ + Scope (_PR) + { + /* Looks like the P_CNT field can't be a method or name + * and has to be hardcoded to 0xe410 or generated in SSDT */ + Processor (CPU0, 0x01, 0xe410, 0x06) {} + } + + /* For now only define 2 power states: + * - S0 which is fully on + * - S5 which is soft off + * Any others would involve declaring the wake up methods. + */ + + /* intel i82371eb (piix4e) datasheet, section 7.2.3, page 142 */ + /* + 000b / 0x0: soft off/suspend to disk (soff/std) s5 + 001b / 0x1: suspend to ram (str) s3 + 010b / 0x2: powered on suspend, context lost (poscl) s1 + 011b / 0x3: powered on suspend, cpu context lost (posccl) s2 + 100b / 0x4: powered on suspend, context maintained (pos) s4 + 101b / 0x5: working (clock control) s0 + 110b / 0x6: reserved + 111b / 0x7: reserved + */ + Name (_S0, Package () { 0x05, 0x05, 0x00, 0x00 }) + Name (_S1, Package () { 0x03, 0x03, 0x00, 0x00 }) + Name (_S5, Package () { 0x00, 0x00, 0x00, 0x00 }) + + /* Root of the bus hierarchy */ + Scope (_SB) + { + /* Top PCI device */ + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x00) + + /* PCI Routing Table */ + Name (_PRT, Package () { + Package (0x04) { 0x0001FFFF, 0, LNKA, 0 }, + Package (0x04) { 0x0001FFFF, 1, LNKB, 0 }, + Package (0x04) { 0x0001FFFF, 2, LNKC, 0 }, + Package (0x04) { 0x0001FFFF, 3, LNKD, 0 }, + + Package (0x04) { 0x0004FFFF, 0, LNKA, 0 }, + Package (0x04) { 0x0004FFFF, 1, LNKB, 0 }, + Package (0x04) { 0x0004FFFF, 2, LNKC, 0 }, + Package (0x04) { 0x0004FFFF, 3, LNKD, 0 }, + + Package (0x04) { 0x0009FFFF, 0, LNKD, 0 }, + Package (0x04) { 0x0009FFFF, 1, LNKA, 0 }, + Package (0x04) { 0x0009FFFF, 2, LNKB, 0 }, + Package (0x04) { 0x0009FFFF, 3, LNKC, 0 }, + + Package (0x04) { 0x000AFFFF, 0, LNKC, 0 }, + Package (0x04) { 0x000AFFFF, 1, LNKD, 0 }, + Package (0x04) { 0x000AFFFF, 2, LNKA, 0 }, + Package (0x04) { 0x000AFFFF, 3, LNKB, 0 }, + + Package (0x04) { 0x000BFFFF, 0, LNKB, 0 }, + Package (0x04) { 0x000BFFFF, 1, LNKC, 0 }, + Package (0x04) { 0x000BFFFF, 2, LNKD, 0 }, + Package (0x04) { 0x000BFFFF, 3, LNKA, 0 }, + + Package (0x04) { 0x000CFFFF, 0, LNKA, 0 }, + Package (0x04) { 0x000CFFFF, 1, LNKB, 0 }, + Package (0x04) { 0x000CFFFF, 2, LNKC, 0 }, + Package (0x04) { 0x000CFFFF, 3, LNKD, 0 }, + + }) + +#include "northbridge/intel/i440bx/acpi/sb_pci0_crs.asl" +#include "southbridge/intel/i82371eb/acpi/isabridge.asl" + } +#include "southbridge/intel/i82371eb/acpi/pirq.asl" + } +}
Added: trunk/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl Sat Nov 27 10:40:16 2010 (r6127) @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Tobias Diedrich ranma+coreboot@tdiedrich.de + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* i440bx Northbridge */ +Device (NB) +{ + Name(_ADR, 0x00000000) + OperationRegion(PCIC, PCI_Config, 0x00, 0x100) +} + +Field (NB.PCIC, AnyAcc, NoLock, Preserve) +{ + Offset (0x67), // DRB7 + DRB7, 8, +} + +Method(TOM1, 0) { + /* Multiply by 8MB to get TOM */ + Return(ShiftLeft(DRB7, 23)) +} + +Method(_CRS, 0) { + Name(TMP, ResourceTemplate() { + WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, + ) + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x0CF7, /* range maximum */ + 0x0000, /* translation */ + 0x0CF8 /* length */ + ) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0D00, /* range minimum */ + 0xFFFF, /* range maximum */ + 0x0000, /* translation */ + 0xF300 /* length */ + ) + + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + }) + CreateDWordField(TMP, MMIO._BAS, MM1B) + CreateDWordField(TMP, MMIO._LEN, MM1L) + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, MM1B) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, MM1L) + + Return(TMP) +}
Modified: trunk/src/southbridge/intel/i82371eb/Makefile.inc ============================================================================== --- trunk/src/southbridge/intel/i82371eb/Makefile.inc Fri Nov 26 23:42:41 2010 (r6126) +++ trunk/src/southbridge/intel/i82371eb/Makefile.inc Sat Nov 27 10:40:16 2010 (r6127) @@ -24,7 +24,8 @@ driver-y += i82371eb_usb.c driver-y += i82371eb_smbus.c driver-y += i82371eb_reset.c +driver-$(CONFIG_HAVE_ACPI_TABLES) += i82371eb_fadt.c +driver-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.c
romstage-y += i82371eb_early_pm.c romstage-y += i82371eb_early_smbus.c -
Added: trunk/src/southbridge/intel/i82371eb/acpi/isabridge.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/intel/i82371eb/acpi/isabridge.asl Sat Nov 27 10:40:16 2010 (r6127) @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Nick Barker Nick.Barker9@btinternet.com + * Copyright (C) 2007 Rudolf Marek r.marek@assembler.cz + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * ISA portions taken from QEMU acpi-dsdt.dsl. + */ + +// Intel LPC Bus Device - 0:4.0 +Device (LPCB) +{ + Name(_ADR, 0x00040000) + + OperationRegion(PCIC, PCI_Config, 0x00, 0x100) + + /* PS/2 keyboard (seems to be important for WinXP install) */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + /* PS/2 floppy controller */ + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { + IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04) + IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + Return (BUF0) + } + } +} + +Device(MBRS) { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + + External(_CRS) /* Resource Template in SSDT */ +}
Added: trunk/src/southbridge/intel/i82371eb/acpi/pirq.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/intel/i82371eb/acpi/pirq.asl Sat Nov 27 10:40:16 2010 (r6127) @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Tobias Diedrich ranma+coreboot@tdiedrich.de + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Field (_SB.PCI0.LPCB.PCIC, AnyAcc, NoLock, Preserve) +{ + Offset (0x60), // Interrupt Routing Registers + PRTA, 8, + PRTB, 8, + PRTC, 8, + PRTD, 8, +} + +Name(IRQB, ResourceTemplate(){ + IRQ(Level,ActiveLow,Shared){15} +}) + +Name(IRQP, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 6, 7, 10, 11, 12} +}) + +/* adapted from ma78gm/dsdt.asl */ +#define PCI_INTX_DEV(intx, pinx, uid) \ +Device(intx) { \ + Name(_HID, EISAID("PNP0C0F")) \ + Name(_UID, uid) \ + \ + Method(_STA, 0) { \ + If (And(pinx, 0x80)) { \ + Return(0x09) \ + } \ + Return(0x0B) \ + } \ + \ + Method(_DIS ,0) { \ + Store(0x80, pinx) \ + } \ + \ + Method(_PRS ,0) { \ + Return(IRQP) \ + } \ + \ + Method(_CRS ,0) { \ + CreateWordField(IRQB, 1, IRQN) \ + ShiftLeft(1, And(pinx, 0x0f), IRQN) \ + Return(IRQB) \ + } \ + \ + Method(_SRS, 1) { \ + CreateWordField(ARG0, 1, IRQM) \ + \ + /* Use lowest available IRQ */ \ + FindSetRightBit(IRQM, Local0) \ + if (Local0) { \ + Decrement(Local0) \ + } \ + Store(Local0, pinx) \ + } \ +} \ + +PCI_INTX_DEV(LNKA, PRTA, 1) +PCI_INTX_DEV(LNKB, PRTB, 2) +PCI_INTX_DEV(LNKC, PRTC, 3) +PCI_INTX_DEV(LNKD, PRTD, 4)
Added: trunk/src/southbridge/intel/i82371eb/acpi_tables.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/intel/i82371eb/acpi_tables.c Sat Nov 27 10:40:16 2010 (r6127) @@ -0,0 +1,137 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Stefan Reinauer stepan@openbios.org + * Copyright (C) 2005 Nick Barker nick.barker9@btinternet.com + * Copyright (C) 2007 Rudolf Marek r.marek@assembler.cz + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci_ids.h> + +extern const unsigned char AmlCode[]; + +unsigned long __attribute__((weak)) acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long __attribute__((weak)) acpi_fill_srat(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long __attribute__((weak)) acpi_fill_madt(unsigned long current) +{ + /* mainboard has no ioapic */ + return current; +} + +unsigned long __attribute__((weak)) acpi_fill_mcfg(unsigned long current) +{ + /* chipset doesn't have mmconfig */ + return current; +} + +unsigned long __attribute__((weak)) acpi_fill_ssdt_generator(unsigned long current, + const char *oem_table_id) +{ + acpigen_write_mainboard_resources("\_SB.PCI0.MBRS", "_CRS"); + return (unsigned long) acpigen_get_current(); +} + +unsigned long __attribute__((weak)) write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_madt_t *madt; + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + /* Align ACPI tables to 16 byte. */ + start = (start + 0x0f) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT table. */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* Clear all table memory. */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* We explicitly add these tables later on: */ + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + + /* we should align FACS to 64B as per ACPI specs */ + current = ALIGN(current, 64); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + dsdt = (acpi_header_t *)current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + /* Don't trust iasl to get checksum right. */ + dsdt->checksum = 0; /* needs to be set to 0 first (part of csum) */ + dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + if (madt->header.length > sizeof(acpi_madt_t)) { + current += madt->header.length; + acpi_add_table(rsdp, madt); + } else { + /* don't add empty madt */ + current = (unsigned long)madt; + } + + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + acpi_create_ssdt_generator(ssdt, "DYNADATA"); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +}
Modified: trunk/src/southbridge/intel/i82371eb/chip.h ============================================================================== --- trunk/src/southbridge/intel/i82371eb/chip.h Fri Nov 26 23:42:41 2010 (r6126) +++ trunk/src/southbridge/intel/i82371eb/chip.h Sat Nov 27 10:40:16 2010 (r6127) @@ -34,6 +34,10 @@ int ide1_drive1_udma33_enable:1; int ide_legacy_enable:1; int usb_enable:1; + /* acpi */ + u32 gpo; /* gpio output default */ + u8 lid_polarity; + u8 thrm_polarity; };
#endif /* SOUTHBRIDGE_INTEL_I82371EB_CHIP_H */
Modified: trunk/src/southbridge/intel/i82371eb/i82371eb.h ============================================================================== --- trunk/src/southbridge/intel/i82371eb/i82371eb.h Fri Nov 26 23:42:41 2010 (r6126) +++ trunk/src/southbridge/intel/i82371eb/i82371eb.h Sat Nov 27 10:40:16 2010 (r6127) @@ -56,14 +56,61 @@
/* SMBus */ #define SMBBA 0x90 /* SMBus base address */ +#define SMBUS_IO_BASE 0x0f00 #define SMBHSTCFG 0xd2 /* SMBus host configuration */
/* Power management (ACPI) */ +#define PMSTS 0x00 /* Power Management Status */ +#define PMEN 0x02 /* Power Management Resume Enable */ +#define PWRBTN_EN (1<<8) +#define GBL_EN (1<<5) +#define PMCNTRL 0x04 /* Power Management Control */ +#define SUS_EN (1<<13) /* S0-S5 trigger */ +#define SUS_TYP_MSK (7<<10) +#define SUS_TYP_S0 (5<<10) +#define SUS_TYP_S1 (4<<10) +#define SUS_TYP_S2 (3<<10) +//#define SUS_TYP_S2>---(2<<10) +#define SUS_TYP_S3 (1<<10) +#define SUS_TYP_S5 (0<<10) +#define SCI_EN (1<<0) +#define PMTMR 0x08 /* Power Management Timer */ +#define GPSTS 0x0c /* General Purpose Status */ +#define GPEN 0x0e /* General Purpose Enable */ +#define THRM_EN (1<<0) +#define PCNTRL 0x10 /* Processor control */ +#define GLBSTS 0x18 /* Global Status */ +#define IRQ_RSM_STS (1<<11) +#define EXTSMI_STS (1<<10) +#define GSTBY_STS (1<<8) +#define GP_STS (1<<7) +#define BM1_STS (1<<6) +#define APM_STS (1<<5) +#define DEV_STS (1<<4) +#define BIOS_EN (1<<1) /* GBL_RLS write triggers SMI */ +#define LEGACY_USB_EN (1<<0) /* Keyboard controller access triggers SMI */ +#define DEVSTS 0x1c /* Device Status */ +#define GLBEN 0x20 /* Global Enable */ +#define EXTSMI_EN (1<<10) /* EXTSMI# signal triggers SMI */ +#define GSTBY_EN (1<<8) +#define BM_TRP_EN (1<<1) +#define BIOS_EN (1<<1) /* GBL_RLS write triggers SMI */ +#define LEGACY_USB_EN (1<<0) /* Keyboard controller access triggers SMI */ +#define GLBCTL 0x28 /* Global Control */ +#define EOS (1<<16) /* End of SMI */ +#define SMI_EN (1<<0) /* SMI enable */ +#define DEVCTL 0x2c /* Device Control */ +#define TRP_EN_DEV12 (1<<24) /* SMI on dev12 trap */ +#define GPO0 0x34 +#define GPO1 0x35 +#define GPO2 0x36 +#define GPO3 0x37 + #define PMBA 0x40 /* Power management base address */ +#define DEFAULT_PMBASE 0xe400 +#define PM_IO_BASE DEFAULT_PMBASE #define PMREGMISC 0x80 /* Miscellaneous power management */
-#define PM_IO_BASE 0xe400 - /* Bit definitions */ #define EXT_BIOS_ENABLE_1MB (1 << 9) /* 1-Meg Extended BIOS Enable */ #define EXT_BIOS_ENABLE (1 << 7) /* Extended BIOS Enable */
Modified: trunk/src/southbridge/intel/i82371eb/i82371eb_early_pm.c ============================================================================== --- trunk/src/southbridge/intel/i82371eb/i82371eb_early_pm.c Fri Nov 26 23:42:41 2010 (r6126) +++ trunk/src/southbridge/intel/i82371eb/i82371eb_early_pm.c Sat Nov 27 10:40:16 2010 (r6127) @@ -39,7 +39,7 @@ PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0);
/* Set the PM I/O base. */ - pci_write_config32(dev, PMBA, PM_IO_BASE | 1); + pci_write_config32(dev, PMBA, DEFAULT_PMBASE | 1);
/* Enable access to the PM I/O space. */ reg16 = pci_read_config16(dev, PCI_COMMAND);
Modified: trunk/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c Fri Nov 26 23:42:41 2010 (r6126) +++ trunk/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c Sat Nov 27 10:40:16 2010 (r6127) @@ -27,8 +27,6 @@ #include "i82371eb.h" #include "i82371eb_smbus.h"
-#define SMBUS_IO_BASE 0x0f00 - int smbus_read_byte(u8 device, u8 address);
void enable_smbus(void)
Added: trunk/src/southbridge/intel/i82371eb/i82371eb_fadt.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/intel/i82371eb/i82371eb_fadt.c Sat Nov 27 10:40:16 2010 (r6127) @@ -0,0 +1,222 @@ +/* + * This file is part of the coreboot project. + * + * Based on src/southbridge/via/vt8237r/vt8237_fadt.c + * + * Copyright (C) 2004 Nick Barker nick.barker9@btinternet.com + * Copyright (C) 2007, 2009 Rudolf Marek r.marek@assembler.cz + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <arch/acpi.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "i82371eb.h" + +/** + * Create the Fixed ACPI Description Tables (FADT) for any board with this SB. + * Reference: ACPIspec40a, 5.2.9, page 118 + */ +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + device_t dev; + + /* Power management controller */ + dev = dev_find_device(PCI_VENDOR_ID_INTEL, + PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI, 0); + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = 244; + header->revision = 1; + memcpy(header->oem_id, "CORE ", 6); + memcpy(header->oem_table_id, "COREBOOT", 8); + memcpy(header->asl_compiler_id, "CORE", 4); + header->asl_compiler_revision = 42; + + fadt->firmware_ctrl = (u32)facs; + fadt->dsdt = (u32)dsdt; + fadt->preferred_pm_profile = 0; /* unspecified */ + fadt->sci_int = 9; + fadt->smi_cmd = 0; /* smi command port */ + fadt->acpi_enable = 0; /* acpi enable smi command */ + fadt->acpi_disable = 0; /* acpi disable smi command */ + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0x0; + + fadt->pm1a_evt_blk = DEFAULT_PMBASE; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = DEFAULT_PMBASE + PMCNTRL; + fadt->pm1b_cnt_blk = 0x0; + + fadt->pm2_cnt_blk = 0; + fadt->pm_tmr_blk = DEFAULT_PMBASE + PMTMR; + fadt->gpe0_blk = DEFAULT_PMBASE + GPSTS; + fadt->gpe1_blk = 0x0; + fadt->gpe1_base = 0; + fadt->gpe1_blk_len = 0; + + /* *_len define register width in bytes */ + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 0; /* not supported */ + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 4; + + fadt->cst_cnt = 0; /* smi command to indicate c state changed notification */ + fadt->p_lvl2_lat = 101; /* >100 means c2 not supported */ + fadt->p_lvl3_lat = 1001; /* >1000 means c3 not supported */ + fadt->flush_size = 0; /* only needed if cpu wbinvd is broken */ + fadt->flush_stride = 0; + fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */ + fadt->duty_width = 3; /* this width is in bits */ + fadt->day_alrm = 0x0d; /* rtc cmos ram offset */ + fadt->mon_alrm = 0x0; /* not supported */ + fadt->century = 0x0; /* not supported */ + /* + * bit meaning + * 0 1: We have user-visible legacy devices + * 1 1: 8042 + * 2 0: VGA is ok to probe + * 3 1: MSI are not supported + */ + fadt->iapc_boot_arch = 0xb; + /* + * bit meaning + * 0 WBINVD + * Processors in new ACPI-compatible systems are required to + * support this function and indicate this to OSPM by setting + * this field. + * 1 WBINVD_FLUSH + * If set, indicates that the hardware flushes all caches on the + * WBINVD instruction and maintains memory coherency, but does + * not guarantee the caches are invalidated. + * 2 PROC_C1 + * C1 power state (x86 hlt instruction) is supported on all cpus + * 3 P_LVL2_UP + * 0: C2 only on uniprocessor, 1: C2 on uni- and multiprocessor + * 4 PWR_BUTTON + * 0: pwr button is fixed feature + * 1: pwr button has control method device if present + * 5 SLP_BUTTON + * 0: sleep button is fixed feature + * 1: sleep button has control method device if present + * 6 FIX_RTC + * 0: RTC wake status supported in fixed register spce + * 7 RTC_S4 + * 1: RTC can wake from S4 + * 8 TMR_VAL_EXT + * 1: pmtimer is 32bit, 0: pmtimer is 24bit + * 9 DCK_CAP + * 1: system supports docking station + * 10 RESET_REG_SUPPORT + * 1: fadt describes reset register for system reset + * 11 SEALED_CASE + * 1: No expansion possible, sealed case + * 12 HEADLESS + * 1: Video output, keyboard and mouse are not connected + * 13 CPU_SW_SLP + * 1: Special processor instruction needs to be executed + * after writing SLP_TYP + * 14 PCI_EXP_WAK + * 1: PM1 regs support PCIEXP_WAKE_(STS|EN), must be set + * on platforms with pci express support + * 15 USE_PLATFORM_CLOCK + * 1: OS should prefer platform clock over processor internal + * clock. + * 16 S4_RTC_STS_VALID + * 17 REMOTE_POWER_ON_CAPABLE + * 1: platform correctly supports OSPM leaving GPE wake events + * armed prior to an S5 transition. + * 18 FORCE_APIC_CLUSTER_MODEL + * 19 FORCE_APIC_PHYSICAL_DESTINATION_MODE + */ + fadt->flags = 0xa5; + + fadt->reset_reg.space_id = 0; + fadt->reset_reg.bit_width = 0; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0x0; + fadt->reset_reg.addrh = 0x0; + fadt->reset_value = 0; + + fadt->x_firmware_ctl_l = (u32)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (u32)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); +}
Modified: trunk/src/southbridge/intel/i82371eb/i82371eb_isa.c ============================================================================== --- trunk/src/southbridge/intel/i82371eb/i82371eb_isa.c Fri Nov 26 23:42:41 2010 (r6126) +++ trunk/src/southbridge/intel/i82371eb/i82371eb_isa.c Sat Nov 27 10:40:16 2010 (r6127) @@ -67,6 +67,13 @@ rtc_init(0);
/* + * Enable special cycles, needed for soft poweroff. + */ + reg32 = pci_read_config16(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_SPECIAL; + pci_write_config16(dev, PCI_COMMAND, reg32); + + /* * The PIIX4 can support the full ISA bus, or the Extended I/O (EIO) * bus, which is a subset of ISA. We select the full ISA bus here. */ @@ -105,12 +112,16 @@ res = new_resource(dev, 2); res->base = 0xff800000UL; res->size = 0x00800000UL; /* 8 MB for flash */ - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | + IORESOURCE_RESERVE;
+#if CONFIG_IOAPIC res = new_resource(dev, 3); /* IOAPIC */ res->base = IO_APIC_ADDR; res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | + IORESOURCE_RESERVE; +#endif }
static const struct device_operations isa_ops = {
Modified: trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.c Fri Nov 26 23:42:41 2010 (r6126) +++ trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.c Sat Nov 27 10:40:16 2010 (r6127) @@ -2,6 +2,9 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Uwe Hermann uwe@hermann-uwe.de + * Copyright (C) 2010 Keith Hui buurin@gmail.com + * Copyright (C) 2010 Idwer Vollering vidwer@gmail.com + * Copyright (C) 2010 Tobias Diedrich ranma+coreboot@gmail.com * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,6 +21,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#include <arch/io.h> +#include <console/console.h> #include <stdint.h> #include <device/device.h> #include <device/pci.h> @@ -26,17 +31,98 @@ #include "i82371eb.h" #include "i82371eb_smbus.h"
-/* TODO: Needed later? */ +static void pwrmgt_enable(struct device *dev) +{ + struct southbridge_intel_i82371eb_config *sb = dev->chip_info; + u32 reg, gpo = sb->gpo; + + /* Sets the base address of power management ports. */ + pci_write_config16(dev, PMBA, DEFAULT_PMBASE | 1); + + /* Set Power Management IO Space Enable bit */ + u8 val = pci_read_config8(dev, PMREGMISC); + pci_write_config8(dev, PMREGMISC, val | 1); + + /* set global control: + * bit25 (lid_pol): 1=invert lid polarity + * bit24 (sm_freeze): 1=freeze idle and standby timers + * bit16 (end of smi): 0=disable smi assertion (cleared by hw) + * bits8-15,26: global standby timer inital count 127 * 4minutes + * bit2 (thrm_pol): 1=active low THRM# + * bit0 (smi_en): 1=disable smi generation upon smi event + */ + reg = (sb->lid_polarity<<25)| + (1<<24)| + (0xff<<8)| + (sb->thrm_polarity<<2); + outl(reg, DEFAULT_PMBASE + GLBCTL); + + /* set processor control: + * bit12 (stpclk_en): 1=enable stopping of host clk on lvl3 + * bit11 (sleep_en): 1=enable slp# assertion on lvl3 + * bit9 (cc_en): 1=enable clk control with lvl2 and lvl3 regs + */ + outl(0, DEFAULT_PMBASE + PCNTRL); + + /* disable smi event enables */ + outw(0, DEFAULT_PMBASE + GLBEN); + outl(0, DEFAULT_PMBASE + DEVCTL); + + /* set default gpo value. + * power-on default is 0x7fffbfffh */ + if (gpo) { + /* only 8bit access allowed */ + outb( gpo & 0xff, DEFAULT_PMBASE + GPO0); + outb((gpo >> 8) & 0xff, DEFAULT_PMBASE + GPO1); + outb((gpo >> 16) & 0xff, DEFAULT_PMBASE + GPO2); + outb((gpo >> 24) & 0xff, DEFAULT_PMBASE + GPO3); + } else { + printk(BIOS_SPEW, + "%s: gpo default missing in devicetree.cb!\n", __func__); + } + + /* Clear status events. */ + outw(0xffff, DEFAULT_PMBASE + PMSTS); + outw(0xffff, DEFAULT_PMBASE + GPSTS); + outw(0xffff, DEFAULT_PMBASE + GLBSTS); + outl(0xffffffff, DEFAULT_PMBASE + DEVSTS); + + /* set pmcntrl default */ + outw(SUS_TYP_S0|SCI_EN, DEFAULT_PMBASE + PMCNTRL); +} + +static void pwrmgt_read_resources(struct device *dev) +{ + struct resource *res; + + pci_dev_read_resources(dev); + + res = new_resource(dev, 1); + res->base = DEFAULT_PMBASE; + res->size = 0x0040; + res->limit = 0xffff; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | + IORESOURCE_RESERVE; + + res = new_resource(dev, 2); + res->base = SMBUS_IO_BASE; + res->size = 0x0010; + res->limit = 0xffff; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | + IORESOURCE_RESERVE; +} + + static const struct smbus_bus_operations lops_smbus_bus = { };
static const struct device_operations smbus_ops = { - .read_resources = pci_dev_read_resources, + .read_resources = pwrmgt_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, .scan_bus = scan_static_bus, - .enable = 0, + .enable = pwrmgt_enable, .ops_pci = 0, /* No subsystem IDs on 82371EB! */ .ops_smbus_bus = &lops_smbus_bus, };
On 11/27/10 1:40 AM, repository service wrote:
+++ trunk/src/mainboard/asus/p2b/dsdt.asl Sat Nov 27 10:40:16 2010 (r6127) @@ -0,0 +1,101 @@
...
+DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) +{
- /* Define the main processor.*/
- Scope (_PR)
- {
/* Looks like the P_CNT field can't be a method or name* and has to be hardcoded to 0xe410 or generated in SSDT */Processor (CPU0, 0x01, 0xe410, 0x06) {}- }
The specified IO port is most likely wrong. As the comment mentions, the SSDT is a good place for that. A preprocessor define used both in the CPU init code and in the asl would solve the problem without an SSDT. For some info on CPU SSDT creation on intel check out src/cpu/intel/speedstep/acpi.c
Stefan
Stefan Reinauer wrote:
On 11/27/10 1:40 AM, repository service wrote:
+++ trunk/src/mainboard/asus/p2b/dsdt.asl Sat Nov 27 10:40:16 2010 (r6127) @@ -0,0 +1,101 @@
...
+DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) +{
- /* Define the main processor.*/
- Scope (_PR)
- {
/* Looks like the P_CNT field can't be a method or name* and has to be hardcoded to 0xe410 or generated in SSDT */Processor (CPU0, 0x01, 0xe410, 0x06) {}- }
The specified IO port is most likely wrong. As the comment mentions, the SSDT is a good place for that. A preprocessor define used both in the CPU init code and in the asl would solve the problem without an SSDT. For some info on CPU SSDT creation on intel check out src/cpu/intel/speedstep/acpi.c
The IO port is ok (and I wrote the comment myself ;)): DEFAULT_PMBASE is 0xe400 PCNTRL reg offset is 0x10
Using the preprocessor will probably work too if iasl can do simple arithmetic (likely yes), I'll look into that.
Tobias Diedrich wrote:
Stefan Reinauer wrote:
The specified IO port is most likely wrong. As the comment mentions, the SSDT is a good place for that. A preprocessor define used both in the CPU init code and in the asl would solve the problem without an SSDT. For some info on CPU SSDT creation on intel check out src/cpu/intel/speedstep/acpi.c
The IO port is ok (and I wrote the comment myself ;)): DEFAULT_PMBASE is 0xe400 PCNTRL reg offset is 0x10
Using the preprocessor will probably work too if iasl can do simple arithmetic (likely yes), I'll look into that.
BTW, my first idea was to use an acpi method that looks up pmbase in the pci cfg space, but when I define a method like this:
Method(TEST, 2) { Return (Add(Arg0, Arg1)) }
I get: |build/mainboard/asus/p2b/dsdt.ramstage.asl 9: Processor (CPU0, |0x01, TEST(0xe400, 0x10), 0x06) {} |Error 4096 - syntax error, unexpected PARSEOP_NAMESEG, |expecting ')' ^
While using the builtin Add() directly works:
Signed-off-by: Tobias Diedrich ranma+coreboot@tdiedrich.de
Index: src/southbridge/intel/i82371eb/i82371eb.h =================================================================== --- src/southbridge/intel/i82371eb/i82371eb.h (revision 6128) +++ src/southbridge/intel/i82371eb/i82371eb.h (working copy) @@ -23,6 +23,7 @@
#if !defined(ASSEMBLY) #if !defined(__PRE_RAM__) +#if !defined(__ACPI__) /* dsdt include */
#include <arch/io.h> #include <device/device.h> @@ -33,6 +34,7 @@
#endif #endif +#endif
/* If 'cond' is true this macro sets the bit(s) specified by 'bits' in the * 'reg' variable, otherwise it clears those bits. Index: src/mainboard/asus/p2b/dsdt.asl =================================================================== --- src/mainboard/asus/p2b/dsdt.asl (revision 6128) +++ src/mainboard/asus/p2b/dsdt.asl (working copy) @@ -17,14 +17,17 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#include "southbridge/intel/i82371eb/i82371eb.h" + DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) { /* Define the main processor.*/ Scope (_PR) { - /* Looks like the P_CNT field can't be a method or name - * and has to be hardcoded to 0xe410 or generated in SSDT */ - Processor (CPU0, 0x01, 0xe410, 0x06) {} + /* Looks like the P_CNT field can't be a name or method (except + * builtins like Add()) and has to be hardcoded or generated + * into SSDT */ + Processor (CPU0, 0x01, Add(DEFAULT_PMBASE, PCNTRL), 0x06) {} }
/* For now only define 2 power states:
On Sun, Nov 28, 2010 at 12:06:56PM +0100, Tobias Diedrich wrote:
BTW, my first idea was to use an acpi method that looks up pmbase in the pci cfg space, but when I define a method like this:
Method(TEST, 2) { Return (Add(Arg0, Arg1)) }I get: |build/mainboard/asus/p2b/dsdt.ramstage.asl 9: Processor (CPU0, |0x01, TEST(0xe400, 0x10), 0x06) {} |Error 4096 - syntax error, unexpected PARSEOP_NAMESEG, |expecting ')' ^
Not sure if or how this can be fixes, but..
While using the builtin Add() directly works:
Signed-off-by: Tobias Diedrich ranma+coreboot@tdiedrich.de
...this solution looks nice and readable too.
Acked-by: Uwe Hermann uwe@hermann-uwe.de
Uwe.
Uwe Hermann wrote:
While using the builtin Add() directly works:
Signed-off-by: Tobias Diedrich ranma+coreboot@tdiedrich.de
...this solution looks nice and readable too.
Acked-by: Uwe Hermann uwe@hermann-uwe.de
Thanks, committed as r6132.
Tobias Diedrich wrote:
Uwe Hermann wrote:
While using the builtin Add() directly works:
Signed-off-by: Tobias Diedrich ranma+coreboot@tdiedrich.de
...this solution looks nice and readable too.
Acked-by: Uwe Hermann uwe@hermann-uwe.de
Thanks, committed as r6132.
Maybe a bit too quick. I didn't test-boot this because iasl did not complain, but now that I did boot for another reason I get: [ 0.111215] ACPI: Core revision 20100428 [ 0.115970] ACPI Error: Found unknown opcode 0xE4 at AML address e07ee578 offset 0x14, ignoring (20100428/psloop-141) [ 0.130114] ACPI Error: Found unknown opcode 0xE4 at AML address e07ee578 offset 0x14, ignoring (20100428/psloop-141) [ 0.140090] ACPI Exception: AE_CTRL_PENDING, While creating Arg 1 (20100428/dsutils-763) [ 0.148689] ACPI Error: Found unknown opcode 0xC3 at AML address 00000008 offset 0x1F811AA4, ignoring (20100428/psloop-141) [ 0.160027] ACPI Error: Found unknown opcode 0xE2 at AML address 00000009 offset 0x1F811AA5, ignoring (20100428/psloop-141) [ 0.172338] ACPI Error: Found unknown opcode 0xF0 at AML address 0000000b offset 0x1F811AA7, ignoring (20100428/psloop-141) [ 0.182325] ACPI Error: Found unknown opcode 0x39 at AML address 00000015 offset 0x1F811AB1, ignoring (20100428/psloop-141) [ 0.192354] ACPI Error: Found unknown opcode 0xC0 at AML address 00000017 offset 0x1F811AB3, ignoring (20100428/psloop-141) [ 0.202386] ACPI Error: Found unknown opcode 0xFE at AML address 00000021 offset 0x1F811ABD, ignoring (20100428/psloop-141) [ 0.219243] ACPI Error: Found unknown opcode 0xF0 at AML address 00000023 offset 0x1F811ABF, ignoring (20100428/psloop-141)
And changing the Add(DEFAULT_PMBASE, PCNTRL) back to 0xe410 fixes it. Either iasl is buggy or the linux kernel... :/
Hi,
Maybe DSDT version is bad?
Thanks, Rudolf
Rudolf Marek wrote:
Maybe DSDT version is bad?
Test dsdt: DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) { Scope (_PR) { Processor (CPU0, 1, Add(2, 3), 4) {} } }
iasl dsdt.asl: |ASL Input: dsdt.asl - 9 lines, 128 bytes, 3 keywords |AML Output: DSDT.aml - 60 bytes, 2 named objects, 1 executable opcodes | |Compilation complete. 0 Errors, 0 Warnings, 0 Remarks, 1 Optimizations
iasl -d DSDT.aml: |Loading Acpi table from file DSDT.aml |Acpi table [DSDT] successfully installed and loaded |Pass 1 parse of [DSDT] |Pass 2 parse of [DSDT] |Parsing Deferred Opcodes (Methods/Buffers/Packages/Regions) | |Parsing completed |Disassembly completed, written to "DSDT.dsl"
So far so good, but the output doesn't match the original input: |ACPI Error: Found unknown opcode 0x2 at AML address 0x1d14af7 offset 0x13, ignoring (20100528/psloop-232) |ACPI Error: Found unknown opcode 0x4 at AML address 0x1d14afb offset 0x17, ignoring (20100528/psloop-232) |ACPI Error: Found unknown opcode 0x2 at AML address 0x1d14af7 offset 0x13, ignoring (20100528/psloop-232) |ACPI Error: Found unknown opcode 0x4 at AML address 0x1d14afb offset 0x17, ignoring (20100528/psloop-232) |/* | * Intel ACPI Component Architecture | * AML Disassembler version 20100528 [...] |DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 0x00000001) |{ | Scope (_PR) | { | Processor (CPU0, 0x01, 0x00000000, 0x0A) | { | 0x03 | Zero | } | } |}
Definitively a iasl problem, it can't even disassemble it's own output back to something equivalent to the input file. It seems to be generating Bytecode for the Add where it shouldn't.
* Tobias Diedrich ranma+coreboot@tdiedrich.de [101128 11:43]:
Stefan Reinauer wrote:
On 11/27/10 1:40 AM, repository service wrote:
+++ trunk/src/mainboard/asus/p2b/dsdt.asl Sat Nov 27 10:40:16 2010 (r6127) @@ -0,0 +1,101 @@
...
+DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) +{
- /* Define the main processor.*/
- Scope (_PR)
- {
/* Looks like the P_CNT field can't be a method or name* and has to be hardcoded to 0xe410 or generated in SSDT */Processor (CPU0, 0x01, 0xe410, 0x06) {}- }
The specified IO port is most likely wrong. As the comment mentions, the SSDT is a good place for that. A preprocessor define used both in the CPU init code and in the asl would solve the problem without an SSDT. For some info on CPU SSDT creation on intel check out src/cpu/intel/speedstep/acpi.c
The IO port is ok (and I wrote the comment myself ;)): DEFAULT_PMBASE is 0xe400 PCNTRL reg offset is 0x10
Oh, I think that's even worse... ;)
1) DEFAULT_PMBASE must be lower than 0x1000 to avoid conflicts with the resource allocator.
2) The IO address in the Processor field should be configured in the MSR PMG_IO_BASE_ADDR (0xe3).
Stefan
Stefan Reinauer wrote:
- Tobias Diedrich ranma+coreboot@tdiedrich.de [101128 11:43]:
The IO port is ok (and I wrote the comment myself ;)): DEFAULT_PMBASE is 0xe400 PCNTRL reg offset is 0x10
Oh, I think that's even worse... ;)
- DEFAULT_PMBASE must be lower than 0x1000 to avoid conflicts with the resource allocator.
It's registered as a fixed resource in i82371eb_smbus.c (added by me in the acpi patch), so it shouldn't be a problem.
- The IO address in the Processor field should be configured in the MSR PMG_IO_BASE_ADDR (0xe3).
This is only for newer processors I think, I didn't see an this msr in the msr list for PIII processors. It's handled by the 440bx chipset acpi registers instead.
Tobias Diedrich wrote:
Definitively a iasl problem, it can't even disassemble it's own output back to something equivalent to the input file. It seems to be generating Bytecode for the Add where it shouldn't.
Here is a solution using the SSDT.
Unfortunately iasl does not resolve simple arithmetic at compile time, so we can not use Add(DEFAULT_PMBASE, PCNTRL) in the Processor statement. This patch instead dynamically generates the processor statement. I can't use the speedstep generate_cpu_entries() directly since the cpu doesn't support speedstep. For now the code is in the southbridge directory, but maybe it should go into cpu/intel/ somewhere. IIRC notebook cpus of the era can already have speedstep, so it would probably be possible to pair the i82371eb with a speedstep-capable cpu... Also, I don't know if multiprocessor boards (abit bp6?) would need to be handled differently.
Abuild-tested.
Signed-off-by: Tobias Diedrich ranma+coreboot@tdiedrich.de
---
Index: src/mainboard/asus/p2b/dsdt.asl =================================================================== --- src/mainboard/asus/p2b/dsdt.asl.orig 2010-12-01 17:50:26.000000000 +0100 +++ src/mainboard/asus/p2b/dsdt.asl 2010-12-01 18:29:22.000000000 +0100 @@ -21,15 +21,6 @@
DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) { - /* Define the main processor.*/ - Scope (_PR) - { - /* Looks like the P_CNT field can't be a name or method (except - * builtins like Add()) and has to be hardcoded or generated - * into SSDT */ - Processor (CPU0, 0x01, Add(DEFAULT_PMBASE, PCNTRL), 0x06) {} - } - /* For now only define 2 power states: * - S0 which is fully on * - S5 which is soft off Index: src/southbridge/intel/i82371eb/acpi_tables.c =================================================================== --- src/southbridge/intel/i82371eb/acpi_tables.c.orig 2010-12-01 17:50:26.000000000 +0100 +++ src/southbridge/intel/i82371eb/acpi_tables.c 2010-12-01 18:30:47.000000000 +0100 @@ -26,9 +26,46 @@ #include <arch/smp/mpspec.h> #include <device/device.h> #include <device/pci_ids.h> +#include "i82371eb.h"
extern const unsigned char AmlCode[];
+static int determine_total_number_of_cores(void) +{ + device_t cpu; + int count = 0; + for(cpu = all_devices; cpu; cpu = cpu->next) { + if ((cpu->path.type != DEVICE_PATH_APIC) || + (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) { + continue; + } + if (!cpu->enabled) { + continue; + } + count++; + } + return count; +} + +void generate_cpu_entries(void) +{ + int len; + int len_pr; + int cpu, pcontrol_blk=DEFAULT_PMBASE+PCNTRL, plen=6; + int numcpus = determine_total_number_of_cores(); + printk(BIOS_DEBUG, "Found %d CPU(s).\n", numcpus); + + /* without the outer scope, furhter ssdt addition will end up + * within the processor statement */ + len = acpigen_write_scope("\_PR"); + for (cpu=0; cpu < numcpus; cpu++) { + len_pr = acpigen_write_processor(cpu, pcontrol_blk, plen); + acpigen_patch_len(len_pr - 1); + len += len_pr; + } + acpigen_patch_len(len - 1); +} + unsigned long __attribute__((weak)) acpi_fill_slit(unsigned long current) { // Not implemented @@ -57,6 +94,10 @@ const char *oem_table_id) { acpigen_write_mainboard_resources("\_SB.PCI0.MBRS", "_CRS"); + /* generate_cpu_entries() generates weird bytecode and has to come + * last or else the following entries will end up inside the + * processor scope */ + generate_cpu_entries(); return (unsigned long) acpigen_get_current(); }
Tobias Diedrich wrote:
Here is a solution using the SSDT.
Unfortunately iasl does not resolve simple arithmetic at compile time, so we can not use Add(DEFAULT_PMBASE, PCNTRL) in the Processor statement. This patch instead dynamically generates the processor statement. I can't use the speedstep generate_cpu_entries() directly since the cpu doesn't support speedstep. For now the code is in the southbridge directory, but maybe it should go into cpu/intel/ somewhere. IIRC notebook cpus of the era can already have speedstep, so it would probably be possible to pair the i82371eb with a speedstep-capable cpu... Also, I don't know if multiprocessor boards (abit bp6?) would need to be handled differently.
Abuild-tested.
Signed-off-by: Tobias Diedrich ranma+coreboot@tdiedrich.de
Not lovely to generate something that is so simple, but sure, if it works.
Acked-by: Peter Stuge peter@stuge.se
Peter Stuge wrote:
Tobias Diedrich wrote:
Here is a solution using the SSDT.
Unfortunately iasl does not resolve simple arithmetic at compile time, so we can not use Add(DEFAULT_PMBASE, PCNTRL) in the Processor statement. This patch instead dynamically generates the processor statement. I can't use the speedstep generate_cpu_entries() directly since the cpu doesn't support speedstep. For now the code is in the southbridge directory, but maybe it should go into cpu/intel/ somewhere. IIRC notebook cpus of the era can already have speedstep, so it would probably be possible to pair the i82371eb with a speedstep-capable cpu... Also, I don't know if multiprocessor boards (abit bp6?) would need to be handled differently.
Abuild-tested.
Signed-off-by: Tobias Diedrich ranma+coreboot@tdiedrich.de
Not lovely to generate something that is so simple, but sure, if it works.
Acked-by: Peter Stuge peter@stuge.se
Thanks, committed as r6153. Damn, three added empty files sneaked in from the other parts of the quilt patch set, removed by r6154.
-
Peter Stuge -
repository service -
Rudolf Marek -
Stefan Reinauer -
Stefan Reinauer -
Tobias Diedrich -
Uwe Hermann