[patch]: it8718f, sometime we use 48Mhz.

[Bao, Zheng]

We should separate the it8718f_24mhz_clkin like the way 8712 does.

Signed-off-by: Zheng Bao

Index: src/superio/ite/it8718f/it8718f_early_serial.c
===================================================================
--- src/superio/ite/it8718f/it8718f_early_serial.c	(revision 449)
+++ src/superio/ite/it8718f/it8718f_early_serial.c	(working copy)
@@ -45,10 +45,9 @@
    outb(value, SIO_DATA);
 }

-/* Enable the peripheral devices on the IT8718F Super I/O chip. */
-static void it8718f_enable_serial(device_t dev, unsigned iobase)
+static void it8718f_enter_conf(void)
 {
-	/* (1) Enter the configuration state (MB PnP mode). */
+	/*  Enter the configuration state (MB PnP mode). */

/* Perform MB PnP setup to put the SIO chip at 0x2e. */
    /* Base address 0x2e: 0x87 0x01 0x55 0x55. */
@@ -57,7 +56,30 @@
    outb(0x01, IT8718F_CONFIGURATION_PORT);
    outb(0x55, IT8718F_CONFIGURATION_PORT);
    outb(0x55, IT8718F_CONFIGURATION_PORT);
+}

+static void it8718f_exit_conf(void)
+{
+	/* Exit the configuration state (MB PnP mode). */
+	it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CC, 0x02);
+}
+
+static void it8718f_24mhz_clkin(void)
+{
+	it8718f_enter_conf();
+
+	/* Select 24MHz CLKIN (48MHZ default)*/
+	it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CLOCKSEL, 0x1);
+
+	it8718f_exit_conf();
+}
+
+/* Enable the peripheral devices on the IT8718F Super I/O chip. */
+static void it8718f_enable_serial(device_t dev, unsigned iobase)
+{
+	/* (1) Enter the configuration state (MB PnP mode). */
+	it8718f_enter_conf();
+
    /* (2) Modify the data of configuration registers. */

/* Select the chip to configure (if there's more than one).
@@ -65,17 +87,14 @@
            If this register is not written, both chips are configured.
*/
    /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CONFIGSEL, 0x00);
*/

-	/* Enable all devices. */
+	/* Enable serial port(s). */
    it8718f_sio_write(IT8718F_SP1,  0x30, 0x1); /* Serial port 1 */
    it8718f_sio_write(IT8718F_SP2,  0x30, 0x1); /* Serial port 2 */

-	/* Select 24MHz CLKIN (set bit 0). */
-	it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CLOCKSEL, 0x01);
-
    /* Clear software suspend mode (clear bit 0). TODO: Needed? */
    /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_SWSUSP, 0x00); */

/* (3) Exit the configuration state (MB PnP mode). */
-	it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CC, 0x02);
+	it8718f_exit_conf();
 }

[patch]: it8718f, sometime we use 48Mhz.

[ron minnich]

If you have done an abuild run and tested this on hardware, this is

Acked-by; Ronald G. Minnich

But please verify that it works :-)

ron

[patch]: it8718f, sometime we use 48Mhz.

[Bao, Zheng]

It is verified on AMD/mahogany board.
Zheng

-----Original Message-----
From: ron minnich [mailto:[e-mail]] 
Sent: Monday, May 11, 2009 12:15 PM
To: Bao, Zheng
Cc: [e-mail]
Subject: Re: [coreboot] [patch]: it8718f, sometime we use 48Mhz.

If you have done an abuild run and tested this on hardware, this is

Acked-by; Ronald G. Minnich

But please verify that it works :-)

ron

[patch]: it8718f, sometime we use 48Mhz.

[Uwe Hermann]

Hi,

On Mon, May 11, 2009 at 12:29:19PM +0800, Bao, Zheng wrote:
> It is verified on AMD/mahogany board.

Thanks, committed in r4267.

The code will need some more work to make it more generic (so that
it can handle config port 0x4e too, for example). I'll post some
patches for that.
> -----Original Message-----
> From: ron minnich [mailto:[e-mail]] 
> Sent: Monday, May 11, 2009 12:15 PM
> To: Bao, Zheng
> Cc: [e-mail]
> Subject: Re: [coreboot] [patch]: it8718f, sometime we use 48Mhz.
>
> If you have done an abuild run and tested this on hardware, this is
>
> Acked-by; Ronald G. Minnich
>
> But please verify that it works :-)

The code looks ok, but we don't yet have an IT8718F board in svn which
we could use for additional tests.

Uwe.