i440bx PARALLEL_MP testing WAS: Re: Suggestion for deprecation: LEGACY_SMP_INIT & RESOURCE_ALLOCATOR_V3

[Branden Waldner]

On 11/30/21, Keith Hui  wrote:
> I suffered an unexpected exception after applying the patch train.
> Serial log at the end of this email. I probably could leave out
> bootblock/romstage/postcar, but it's here for completeness. Next:
> bisect.

I had a similar result testing on my P2B. I'm working on recovering it
and I was planning on trying a build with log level spew on the P2-99
since it is easy for me to recover with the way I have it setup right
now.

Branden Waldner

[Keith Hui]

Hi guys,

Just a heads-up. Soon after I confirmed the issue with Arthur's
patches (and he told us of his fix), I ran into major stability issues
with all my boards to the point I couldn't reliably boot any of them.
Granted they were sitting naked between a desk lamp and the power
supply so EMI could be an issue. I don't know, and I probably won't
find out for sure until next week when I can house them properly.

Branden, I'll appreciate if you can confirm whether Arthur's SSE2
workaround fix the issue.

Thanks
Keith

On Tue, 30 Nov 2021 at 15:15, Branden Waldner  wrote:
> On 11/30/21, Keith Hui  wrote:
> > I suffered an unexpected exception after applying the patch train.
> > Serial log at the end of this email. I probably could leave out
> > bootblock/romstage/postcar, but it's here for completeness. Next:
> > bisect.
>
> I had a similar result testing on my P2B. I'm working on recovering it
> and I was planning on trying a build with log level spew on the P2-99
> since it is easy for me to recover with the way I have it setup right
> now.
>
> Branden Waldner

[Branden Waldner]

I tested https://review.coreboot.org/c/coreboot/+/59693/
nb/intel/i440bx: Use PARALLEL_MP patchset 6 on my p2-99 and it appears
to work properly.

The work around of disabling including the config in the rom to free
up space wasn't enough with this patchset though, so I just disabled
including microcode updates for now. I'm hoping the LTO and romstage
sources inside the bootblock will make in it yet, since they both
saved s[pace.

I only attached a specific portion of the log, since it got rather
long with spew set.

Branden Waldner

Initializing devices...
CPU_CLUSTER: 0 init
CPU: .
Setting up local APIC 0x0
Initializing CPU #0
CPU: vendor Intel device 681
CPU: family 06, model 08, stepping 01
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x0000000020000000 size 0x1ff40000 type 6
0x0000000020000000 - 0x0000000040000000 size 0x20000000 type 1
0x0000000040000000 - 0x0000000100000000 size 0xc0000000 type 0
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits
MTRR: default type WB/UC MTRR counts: 3/2.
MTRR: UC selected as default type.
MTRR: 0 base 0x0000000000000000 mask 0x0000000fe0000000 type 6
MTRR: 1 base 0x0000000020000000 mask 0x0000000fe0000000 type 1

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

FMAP: area COREBOOT found @ 200 (261632 bytes)
CBFS: 'cpu_microcode_blob.bin' not found.
CPU #0 initialized

On 11/30/21, Keith Hui  wrote:
> Hi guys,
>
> Just a heads-up. Soon after I confirmed the issue with Arthur's
> patches (and he told us of his fix), I ran into major stability issues
> with all my boards to the point I couldn't reliably boot any of them.
> Granted they were sitting naked between a desk lamp and the power
> supply so EMI could be an issue. I don't know, and I probably won't
> find out for sure until next week when I can house them properly.
>
> Branden, I'll appreciate if you can confirm whether Arthur's SSE2
> workaround fix the issue.
>
> Thanks
> Keith
>
> On Tue, 30 Nov 2021 at 15:15, Branden Waldner  wrote:
> > On 11/30/21, Keith Hui  wrote:
> > > I suffered an unexpected exception after applying the patch train.
> > > Serial log at the end of this email. I probably could leave out
> > > bootblock/romstage/postcar, but it's here for completeness. Next:
> > > bisect.
> >
> > I had a similar result testing on my P2B. I'm working on recovering it
> > and I was planning on trying a build with log level spew on the P2-99
> > since it is easy for me to recover with the way I have it setup right
> > now.
> >
> > Branden Waldner