Add support for S2/S3 sleep (resume from reset vector).
Part1 adds the get_acpi_sleep_type() function to read the sleep type and sets acpi_slp_type.
Part2 adds generic infrastructure to save a pointer to cbmem_toc in the ACPI memory area. This could also replace the vt8237 solution of using special nvram (which the I82371EB chipset doesn't have).
Part3 adds the necessary code to save the memory area overwritten by ramstage into the reserved backup memory space.
All three patches are abuild-tested and should be applied after the ssdt cpu generation patch (http://www.coreboot.org/pipermail/coreboot/2010-December/062229.html).
I tested the complete stack on both the P2B board which I wrote it for and the amd am2 base M2V board to check that it doesn't break anything there.
Keith: It should probably be rather simple to enable this on P2B-LS/P3B-F too if you'd like to test.
Here is the serial log (cold boot, s3, poweroff). Note: While S5 poweroff works and does poweroff the power supply, S3 seems to still need some magic to really power off, even though we tell the chipset to go to S3 sleep. However investigating this will have to wait since I won't have access to these boards, starting tomorrow, for the next month or so.
coreboot-4.0-r6132M Wed Dec 1 21:51:49 CET 2010 starting... Wakeup from ACPI sleep type S5 (PMCNTRL=0000) v_esp=000cffc8 testx = 5a5a5a5a resume_backup_memory=00000000 Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a After cache as ram disabled resume_backup_memory=00000000 Clearing initial memory region: Done Loading image. Check CBFS header at fffffc9e magic is 4f524243 Found CBFS header at fffffc9e Check fallback/romstage CBFS: follow chain: fffc0000 + 38 + 3699 + align -> fffc3700 Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (212992 bytes), entry @ 0x100000 Stage: done loading. Jumping to image. coreboot-4.0-r6132M Wed Dec 1 21:51:49 CET 2010 booting... clocks_per_usec: 502 Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:04.0: enabled 1 PNP: 03f0.0: enabled 1 PNP: 03f0.1: enabled 1 PNP: 03f0.2: enabled 1 PNP: 03f0.3: enabled 1 PNP: 03f0.5: enabled 1 PNP: 03f0.7: enabled 1 PNP: 03f0.8: enabled 1 PNP: 03f0.9: enabled 1 PNP: 03f0.a: enabled 1 PCI: 00:04.1: enabled 1 PCI: 00:04.2: enabled 1 PCI: 00:04.3: enabled 1 Compare with tree... Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:04.0: enabled 1 PNP: 03f0.0: enabled 1 PNP: 03f0.1: enabled 1 PNP: 03f0.2: enabled 1 PNP: 03f0.3: enabled 1 PNP: 03f0.5: enabled 1 PNP: 03f0.7: enabled 1 PNP: 03f0.8: enabled 1 PNP: 03f0.9: enabled 1 PNP: 03f0.a: enabled 1 PCI: 00:04.1: enabled 1 PCI: 00:04.2: enabled 1 PCI: 00:04.3: enabled 1 scan_static_bus for Root Device APIC_CLUSTER: 0 enabled Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/7190] ops PCI: 00:00.0 [8086/7190] enabled PCI: 00:01.0 [8086/7191] enabled PCI: 00:04.0 [8086/7110] bus ops PCI: 00:04.0 [8086/7110] enabled PCI: 00:04.1 [8086/7111] ops PCI: 00:04.1 [8086/7111] enabled PCI: 00:04.2 [8086/7112] ops PCI: 00:04.2 [8086/7112] enabled PCI: 00:04.3 [8086/7113] bus ops Wakeup from ACPI sleep type S5 (PMCNTRL=0000) PCI: 00:04.3 [8086/7113] enabled PCI: 00:09.0 [10ec/8169] enabled PCI: 00:0c.0 [102b/0519] enabled do_pci_scan_bridge for PCI: 00:01.0 PCI: pci_scan_bus for bus 01 PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 scan_static_bus for PCI: 00:04.0 PNP: 03f0.0 enabled PNP: 03f0.1 enabled PNP: 03f0.2 enabled PNP: 03f0.3 enabled PNP: 03f0.5 enabled PNP: 03f0.7 enabled PNP: 03f0.8 enabled PNP: 03f0.9 enabled PNP: 03f0.a enabled PNP: 03f0.6 enabled scan_static_bus for PCI: 00:04.0 done scan_static_bus for PCI: 00:04.3 scan_static_bus for PCI: 00:04.3 done PCI: pci_scan_bus returning with max=001 scan_static_bus for Root Device done done Setting up VGA for PCI: 00:0c.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:04.0 read_resources bus 0 link: 0 PNP: 03f0.8 missing read_resources PNP: 03f0.9 missing read_resources PCI: 00:04.0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 10 PCI: 00:01.0 PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24 PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:04.0 child on link 0 PNP: 03f0.0 PCI: 00:04.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:04.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags d0000200 index 2 PNP: 03f0.0 PNP: 03f0.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 03f0.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 03f0.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 03f0.1 PNP: 03f0.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 03f0.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 03f0.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 03f0.2 PNP: 03f0.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 03f0.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 03f0.3 PNP: 03f0.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 03f0.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 03f0.5 PNP: 03f0.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60 PNP: 03f0.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62 PNP: 03f0.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 03f0.5 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 72 PNP: 03f0.7 PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 PNP: 03f0.7 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 62 PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 03f0.8 PNP: 03f0.9 PNP: 03f0.a PNP: 03f0.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 03f0.6 PNP: 03f0.6 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 PNP: 03f0.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PCI: 00:04.1 PCI: 00:04.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:04.2 PCI: 00:04.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:04.3 PCI: 00:04.3 resource base e400 size 40 align 0 gran 0 limit ffff flags d0000100 index 1 PCI: 00:04.3 resource base f00 size 10 align 0 gran 0 limit ffff flags d0000100 index 2 PCI: 00:09.0 PCI: 00:09.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 PCI: 00:09.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 14 PCI: 00:09.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30 PCI: 00:0c.0 PCI: 00:0c.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10 PCI: 00:0c.0 resource base 0 size 800000 align 23 gran 23 limit ffffffff flags 1200 index 14 PCI: 00:0c.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:09.0 10 * [0x0 - 0xff] io PCI: 00:04.2 20 * [0x400 - 0x41f] io PCI: 00:04.1 20 * [0x420 - 0x42f] io PCI_DOMAIN: 0000 compute_resources_io: base: 430 size: 430 align: 8 gran: 0 limit: ffff done PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:00.0 10 * [0x0 - 0xfffffff] prefmem PCI: 00:0c.0 14 * [0x10000000 - 0x107fffff] prefmem PCI: 00:09.0 30 * [0x10800000 - 0x1081ffff] mem PCI: 00:0c.0 30 * [0x10820000 - 0x1082ffff] mem PCI: 00:0c.0 10 * [0x10830000 - 0x10833fff] mem PCI: 00:09.0 14 * [0x10834000 - 0x108340ff] mem PCI_DOMAIN: 0000 compute_resources_mem: base: 10834100 size: 10834100 align: 28 gran: 0 limit: ffffffff done avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:01.0 constrain_resources: PCI: 00:04.0 constrain_resources: PNP: 03f0.0 constrain_resources: PNP: 03f0.1 constrain_resources: PNP: 03f0.2 constrain_resources: PNP: 03f0.3 constrain_resources: PNP: 03f0.5 constrain_resources: PNP: 03f0.7 constrain_resources: PNP: 03f0.8 constrain_resources: PNP: 03f0.9 constrain_resources: PNP: 03f0.a constrain_resources: PNP: 03f0.6 constrain_resources: PCI: 00:04.1 constrain_resources: PCI: 00:04.2 constrain_resources: PCI: 00:04.3 constrain_resources: PCI: 00:09.0 constrain_resources: PCI: 00:0c.0 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff lim->base 00001000 lim->limit 0000e3ff avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff lim->base 00000000 lim->limit ff7fffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:430 align:8 gran:0 limit:e3ff Assigned: PCI: 00:09.0 10 * [0x1000 - 0x10ff] io Assigned: PCI: 00:04.2 20 * [0x1400 - 0x141f] io Assigned: PCI: 00:04.1 20 * [0x1420 - 0x142f] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 1430 size: 430 align: 8 gran: 0 done PCI: 00:01.0 allocate_resources_io: base:e3ff size:0 align:12 gran:12 limit:e3ff PCI: 00:01.0 allocate_resources_io: next_base: e3ff size: 0 align: 12 gran: 12 done PCI_DOMAIN: 0000 allocate_resources_mem: base:e0000000 size:10834100 align:28 gran:0 limit:ff7fffff Assigned: PCI: 00:00.0 10 * [0xe0000000 - 0xefffffff] prefmem Assigned: PCI: 00:0c.0 14 * [0xf0000000 - 0xf07fffff] prefmem Assigned: PCI: 00:09.0 30 * [0xf0800000 - 0xf081ffff] mem Assigned: PCI: 00:0c.0 30 * [0xf0820000 - 0xf082ffff] mem Assigned: PCI: 00:0c.0 10 * [0xf0830000 - 0xf0833fff] mem Assigned: PCI: 00:09.0 14 * [0xf0834000 - 0xf08340ff] mem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: f0834100 size: 10834100 align: 28 gran: 0 done PCI: 00:01.0 allocate_resources_prefmem: base:ff7fffff size:0 align:20 gran:20 limit:ff7fffff PCI: 00:01.0 allocate_resources_prefmem: next_base: ff7fffff size: 0 align: 20 gran: 20 done PCI: 00:01.0 allocate_resources_mem: base:ff7fffff size:0 align:20 gran:20 limit:ff7fffff PCI: 00:01.0 allocate_resources_mem: next_base: ff7fffff size: 0 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 Setting RAM size to 512 MB PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:00.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem PCI: 00:01.0 1c <- [0x000000e3ff - 0x000000e3fe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:01.0 24 <- [0x00ff7fffff - 0x00ff7ffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:01.0 20 <- [0x00ff7fffff - 0x00ff7ffffe] size 0x00000000 gran 0x14 bus 01 mem PCI: 00:04.0 assign_resources, bus 0 link: 0 PNP: 03f0.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 io PNP: 03f0.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00 irq PNP: 03f0.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00 drq PNP: 03f0.1 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io PNP: 03f0.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq ERROR: PNP: 03f0.1 74 drq size: 0x0000000001 not assigned PNP: 03f0.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 03f0.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 03f0.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io PNP: 03f0.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq PNP: 03f0.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io PNP: 03f0.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io PNP: 03f0.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq PNP: 03f0.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq ERROR: PNP: 03f0.7 60 io size: 0x0000000001 not assigned ERROR: PNP: 03f0.7 62 io size: 0x0000000002 not assigned ERROR: PNP: 03f0.7 70 irq size: 0x0000000001 not assigned ERROR: PNP: 03f0.a 70 irq size: 0x0000000001 not assigned ERROR: PNP: 03f0.6 60 io size: 0x0000000008 not assigned ERROR: PNP: 03f0.6 70 irq size: 0x0000000001 not assigned PCI: 00:04.0 assign_resources, bus 0 link: 0 PCI: 00:04.1 20 <- [0x0000001420 - 0x000000142f] size 0x00000010 gran 0x04 io PCI: 00:04.2 20 <- [0x0000001400 - 0x000000141f] size 0x00000020 gran 0x05 io PCI: 00:09.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 00:09.0 14 <- [0x00f0834000 - 0x00f08340ff] size 0x00000100 gran 0x08 mem PCI: 00:09.0 30 <- [0x00f0800000 - 0x00f081ffff] size 0x00020000 gran 0x11 romem PCI: 00:0c.0 10 <- [0x00f0830000 - 0x00f0833fff] size 0x00004000 gran 0x0e mem PCI: 00:0c.0 14 <- [0x00f0000000 - 0x00f07fffff] size 0x00800000 gran 0x17 prefmem PCI: 00:0c.0 30 <- [0x00f0820000 - 0x00f082ffff] size 0x00010000 gran 0x10 romem PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0 PCI_DOMAIN: 0000 resource base 1000 size 430 align 8 gran 0 limit e3ff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base e0000000 size 10834100 align 28 gran 0 limit ff7fffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a PCI_DOMAIN: 0000 resource base c0000 size 1ff40000 align 0 gran 0 limit 0 flags e0004200 index b PCI: 00:00.0 PCI: 00:00.0 resource base e0000000 size 10000000 align 28 gran 28 limit ff7fffff flags 60001200 index 10 PCI: 00:01.0 PCI: 00:01.0 resource base e3ff size 0 align 12 gran 12 limit e3ff flags 60080102 index 1c PCI: 00:01.0 resource base ff7fffff size 0 align 20 gran 20 limit ff7fffff flags 60081202 index 24 PCI: 00:01.0 resource base ff7fffff size 0 align 20 gran 20 limit ff7fffff flags 60080202 index 20 PCI: 00:04.0 child on link 0 PNP: 03f0.0 PCI: 00:04.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:04.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags d0000200 index 2 PNP: 03f0.0 PNP: 03f0.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 03f0.0 resource base 6 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 03f0.0 resource base 2 size 1 align 0 gran 0 limit 0 flags e0000800 index 74 PNP: 03f0.1 PNP: 03f0.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 03f0.1 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 03f0.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 03f0.2 PNP: 03f0.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 03f0.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 03f0.3 PNP: 03f0.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 03f0.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 03f0.5 PNP: 03f0.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60 PNP: 03f0.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62 PNP: 03f0.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 03f0.5 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 72 PNP: 03f0.7 PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 PNP: 03f0.7 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 62 PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 03f0.8 PNP: 03f0.9 PNP: 03f0.a PNP: 03f0.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 03f0.6 PNP: 03f0.6 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 PNP: 03f0.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PCI: 00:04.1 PCI: 00:04.1 resource base 1420 size 10 align 4 gran 4 limit e3ff flags 60000100 index 20 PCI: 00:04.2 PCI: 00:04.2 resource base 1400 size 20 align 5 gran 5 limit e3ff flags 60000100 index 20 PCI: 00:04.3 PCI: 00:04.3 resource base e400 size 40 align 0 gran 0 limit ffff flags d0000100 index 1 PCI: 00:04.3 resource base f00 size 10 align 0 gran 0 limit ffff flags d0000100 index 2 PCI: 00:09.0 PCI: 00:09.0 resource base 1000 size 100 align 8 gran 8 limit e3ff flags 60000100 index 10 PCI: 00:09.0 resource base f0834000 size 100 align 8 gran 8 limit ff7fffff flags 60000200 index 14 PCI: 00:09.0 resource base f0800000 size 20000 align 17 gran 17 limit ff7fffff flags 60002200 index 30 PCI: 00:0c.0 PCI: 00:0c.0 resource base f0830000 size 4000 align 14 gran 14 limit ff7fffff flags 60000200 index 10 PCI: 00:0c.0 resource base f0000000 size 800000 align 23 gran 23 limit ff7fffff flags 60001200 index 14 PCI: 00:0c.0 resource base f0820000 size 10000 align 16 gran 16 limit ff7fffff flags 60002200 index 30 Done allocating resources. Enabling resources... PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 bridge ctrl <- 0083 PCI: 00:01.0 cmd <- 00 PCI: 00:04.0 cmd <- 07 PCI: 00:04.1 cmd <- 01 PCI: 00:04.2 cmd <- 01 PCI: 00:04.3 cmd <- 01 PCI: 00:09.0 cmd <- 03 PCI: 00:0c.0 cmd <- 83 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init Initializing CPU #0 CPU: vendor Intel device 672 CPU: family 06, model 07, stepping 02 microcode_info: sig = 0x00000672 pf=0x00000001 rev = 0x00000000 microcode updated to revision: 00000010 from revision 00000000 Enabling cache
Setting fixed MTRRs(0-88) Type: UC Setting fixed MTRRs(0-16) Type: WB Setting fixed MTRRs(24-88) Type: WB DONE fixed MTRRs call enable_fixed_mtrr() Setting variable MTRR 0, base: 0MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xf Zero-sized MTRR range @0KB DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs
MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled
Disabling local apic...done. CPU #0 initialized PCI: 00:00.0 init Northbridge Init PCI: 00:04.0 init RTC Init PCI: 00:04.1 init IDE: Primary IDE interface: on IDE: Secondary IDE interface: on IDE: Access to legacy IDE ports: on IDE: Primary IDE interface, drive 0: UDMA/33: off IDE: Primary IDE interface, drive 1: UDMA/33: off IDE: Secondary IDE interface, drive 0: UDMA/33: off IDE: Secondary IDE interface, drive 1: UDMA/33: off PCI: 00:04.2 init PCI: 00:09.0 init PCI: 00:0c.0 init PNP: 03f0.0 init PNP: 03f0.1 init PNP: 03f0.2 init PNP: 03f0.3 init PNP: 03f0.5 init Keyboard init... Keyboard selftest failed ACK: 0xaa PNP: 03f0.7 init PNP: 03f0.a init PNP: 03f0.6 init Devices initialized Show all devs...After init. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:04.0: enabled 1 PNP: 03f0.0: enabled 1 PNP: 03f0.1: enabled 1 PNP: 03f0.2: enabled 1 PNP: 03f0.3: enabled 1 PNP: 03f0.5: enabled 1 PNP: 03f0.7: enabled 1 PNP: 03f0.8: enabled 1 PNP: 03f0.9: enabled 1 PNP: 03f0.a: enabled 1 PCI: 00:04.1: enabled 1 PCI: 00:04.2: enabled 1 PCI: 00:04.3: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:0c.0: enabled 1 PNP: 03f0.6: enabled 1 CPU: 00: enabled 1 Initializing CBMEM area to 0x1feefc00 (1115136 bytes) Adding CBMEM entry as no. 1 Moving GDT to 1feefe00...ok High Tables Base is 1feefc00. Copying Interrupt Routing Table to 0x000f0000... done. Adding CBMEM entry as no. 2 Copying Interrupt Routing Table to 0x1fef0000... done. PIRQ table: 128 bytes. Adding CBMEM entry as no. 3 ACPI: Writing ACPI tables at 1fef1000... ACPI: Writing cbmem_toc pointer at 1fef1024... ACPI: * FACS ACPI: * DSDT @ 1fef1140 Length 683 ACPI: * FADT ACPI: added table 1/32, length now 40 ACPI: * MADT ACPI: * SSDT Found 1 CPU(s). ACPI: added table 2/32, length now 44 ACPI: done. ACPI tables: 2354 bytes. Adding CBMEM entry as no. 4 Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500 - 00000518 checksum 13ef New low_table_end: 0x00000518 Now going to write high coreboot table at 0x1fefcc00 rom_table_end = 0x1fefcc00 Adjust low_table_end from 0x00000518 to 0x00001000 Adjust rom_table_end from 0x1fefcc00 to 0x1ff00000 Adding high table area coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-000000001feefbff: RAM 3. 000000001feefc00-000000001fffffff: CONFIGURATION TABLES 4. 00000000ff800000-00000000ffffffff: RESERVED Wrote coreboot table at: 1fefcc00 - 1fefcdbc checksum ad8c coreboot table: 444 bytes. Adding CBMEM entry as no. 5 Multiboot Information structure has been written. 0. FREE SPACE 1fffec00 00001400 1. GDT 1feefe00 00000200 2. IRQ TABLE 1fef0000 00001000 3. ACPI 1fef1000 0000bc00 4. COREBOOT 1fefcc00 00002000 5. ACPI RESUME1fefec00 00100000 Check CBFS header at fffffc9e magic is 4f524243 Found CBFS header at fffffc9e Check fallback/romstage CBFS: follow chain: fffc0000 + 38 + 3699 + align -> fffc3700 Check fallback/coreboot_ram CBFS: follow chain: fffc3700 + 38 + 148bf + align -> fffd8000 Check fallback/payload Got a payload Loading segment from rom address 0xfffd8038 data (compression=1) New segment dstaddr 0xe9368 memsize 0x16c98 srcaddr 0xfffd8070 filesize 0xb69e (cleaned up) New segment addr 0xe9368 size 0x16c98 offset 0xfffd8070 filesize 0xb69e Loading segment from rom address 0xfffd8054 Entry Point 0x000fc9ef Loading Segment: addr: 0x00000000000e9368 memsz: 0x0000000000016c98 filesz: 0x000000000000b69e lb: [0x0000000000100000, 0x0000000000134000) Post relocation: addr: 0x00000000000e9368 memsz: 0x0000000000016c98 filesz: 0x000000000000b69e using LZMA [ 0x000e9368, 00100000, 0x00100000) <- fffd8070 dest 000e9368, end 00100000, bouncebuffer 1fe87c00 Loaded segments Jumping to boot code at fc9ef entry = 0x000fc9ef lb_start = 0x00100000 lb_size = 0x00034000 adjust = 0x1fdbbc00 buffer = 0x1fe87c00 elf_boot_notes = 0x00124aa0 adjusted_boot_notes = 0x1fee06a0 Start bios (version pre-0.6.2-20101129_001420-nukunuku) Found mainboard ASUS P2B Found CBFS header at 0xfffffc9e Ram Size=0x1feefc00 (0x0000000000000000 high) Relocating init from 0x000e9800 to 0x1fed6500 (size 38360) CPU Mhz=501 No apic - only the main cpu is present. Copying PIR from 0x1fef0000 to 0x000fdc70 Copying ACPI RSDP from 0x1fef1000 to 0x000fdc50 SMBIOS ptr=0x000fdc30 table=0x1feefaf0 Scan for VGA option rom Running option rom at c000:0003 Turning on vga text mode console SeaBIOS (version pre-0.6.2-20101129_001420-nukunuku)
UHCI init on dev 00:04.2 (io=1400) Found 1 lpt ports Found 2 serial ports ATA controller 0 at 1f0/3f4/0 (irq 14 dev 21) ATA controller 1 at 170/374/0 (irq 15 dev 21) ata0-0: WDC WD1200JB-00DUA0 ATA-6 Hard-Disk (111 GiBytes) drive 0x000fdbe0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=234441648 ebda moved from 9fc00 to 9f800 USB mouse initialized Got ps2 nak (status=51) All threads complete. Scan for option roms Press F12 for boot menu.
Returned 57344 bytes of ZoneHigh e820 map has 6 items: 0: 0000000000000000 - 000000000009f800 = 1 1: 000000000009f800 - 00000000000a0000 = 2 2: 00000000000f0000 - 0000000000100000 = 2 3: 0000000000100000 - 000000001feedc00 = 1 4: 000000001feedc00 - 0000000020000000 = 2 5: 00000000ff800000 - 0000000100000000 = 2 enter handle_19: NULL Booting from Floppy... Boot failed: could not read the boot disk
enter handle_18: NULL Booting from DVD/CD... Boot failed: Could not read from CDROM (code 0001) enter handle_18: NULL Booting from Hard Disk... Booting from 0000:7c00 [ 0.000000] Linux version 2.6.35.8-netboot (ranma@nukunuku) (gcc version 4.4.5 (Debian 4.4.5-6) ) #55 Thu Nov 25 16:34:16 CET 2010 [ 0.000000] BIOS-provided physical RAM map: [ 0.000000] BIOS-e820: 0000000000000000 - 000000000009f800 (usable) [ 0.000000] BIOS-e820: 000000000009f800 - 00000000000a0000 (reserved) [ 0.000000] BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved) [ 0.000000] BIOS-e820: 0000000000100000 - 000000001feedc00 (usable) [ 0.000000] BIOS-e820: 000000001feedc00 - 0000000020000000 (reserved) [ 0.000000] BIOS-e820: 00000000ff800000 - 0000000100000000 (reserved) [ 0.000000] Notice: NX (Execute Disable) protection missing in CPU or disabled in BIOS! [ 0.000000] DMI 2.4 present. [ 0.000000] last_pfn = 0x1feed max_arch_pfn = 0x1000000 [ 0.000000] PAT not supported by CPU. [ 0.000000] get_mtrr(0): base hi=00000000 lo=00000006, mask hi=0000000f lo=e0000800 [ 0.000000] init_memory_mapping: 0000000000000000-000000001feed000 [ 0.000000] ACPI: RSDP 000fdc50 00014 (v00 CORE ) [ 0.000000] ACPI: RSDT 1fef102c 0002C (v01 CORE COREBOOT 00000000 CORE 00000000) [ 0.000000] ACPI: FACP 1fef17c3 000F4 (v01 CORE COREBOOT 00000000 CORE 0000002A) [ 0.000000] ACPI: DSDT 1fef1140 00683 (v02 CORE COREBOOT 00000001 INTL 20100528) [ 0.000000] ACPI: FACS 1fef1100 00040 [ 0.000000] ACPI: SSDT 1fef18b7 0007B (v02 CORE DYNADATA 0000002A CORE 0000002A) [ 0.000000] 0MB HIGHMEM available. [ 0.000000] 510MB LOWMEM available. [ 0.000000] mapped low ram: 0 - 1feed000 [ 0.000000] low ram: 0 - 1feed000 [ 0.000000] Zone PFN ranges: [ 0.000000] DMA 0x00000001 -> 0x00001000 [ 0.000000] Normal 0x00001000 -> 0x0001feed [ 0.000000] HighMem empty [ 0.000000] Movable zone start PFN for each node [ 0.000000] early_node_map[2] active PFN ranges [ 0.000000] 0: 0x00000001 -> 0x0000009f [ 0.000000] 0: 0x00000100 -> 0x0001feed [ 0.000000] Using APIC driver default [ 0.000000] ACPI: PM-Timer IO Port: 0xe408 [ 0.000000] Local APIC disabled by BIOS -- you can enable it with "lapic" [ 0.000000] APIC: disable apic facility [ 0.000000] APIC: switched to apic NOOP [ 0.000000] PM: Registered nosave memory: 000000000009f000 - 00000000000a0000 [ 0.000000] PM: Registered nosave memory: 00000000000a0000 - 00000000000f0000 [ 0.000000] PM: Registered nosave memory: 00000000000f0000 - 0000000000100000 [ 0.000000] Allocating PCI resources starting at 20000000 (gap: 20000000:df800000) [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 129677 [ 0.000000] Kernel command line: console=tty0 vga=ext root=/dev/sda2 ro radeon.modeset=1 console=ttyS0,115200 no_console_suspend video=matroxfb:off [ 0.000000] PID hash table entries: 2048 (order: 1, 8192 bytes) [ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes) [ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes) [ 0.000000] Enabling fast FPU save and restore... done. [ 0.000000] Enabling unmasked SIMD FPU exception support... done. [ 0.000000] Initializing CPU#0 [ 0.000000] Subtract (24 early reservations) [ 0.000000] #0 [0001000000 - 00018314f4] TEXT DATA BSS [ 0.000000] #1 [000009f800 - 0000100000] BIOS reserved [ 0.000000] #2 [0001832000 - 0001840049] BRK [ 0.000000] #3 [0000001000 - 0000005000] ACPI WAKEUP [ 0.000000] #4 [0000007000 - 0000008000] PGTABLE [ 0.000000] #5 [0001841000 - 0001842000] BOOTMEM [ 0.000000] #6 [0001842000 - 0001c42000] BOOTMEM [ 0.000000] #7 [0001831500 - 0001831504] BOOTMEM [ 0.000000] #8 [0001831540 - 00018315c0] BOOTMEM [ 0.000000] #9 [00018315c0 - 00018315f0] BOOTMEM [ 0.000000] #10 [0001c42000 - 0001c43000] BOOTMEM [ 0.000000] #11 [0001831600 - 00018316fc] BOOTMEM [ 0.000000] #12 [0001831700 - 0001831740] BOOTMEM [ 0.000000] #13 [0001831740 - 0001831780] BOOTMEM [ 0.000000] #14 [0001831780 - 00018317c0] BOOTMEM [ 0.000000] #15 [00018317c0 - 0001831800] BOOTMEM [ 0.000000] #16 [0001831800 - 0001831840] BOOTMEM [ 0.000000] #17 [0001831840 - 0001831880] BOOTMEM [ 0.000000] #18 [0001831880 - 0001831890] BOOTMEM [ 0.000000] #19 [00018318c0 - 0001831933] BOOTMEM [ 0.000000] #20 [0001831940 - 00018319b3] BOOTMEM [ 0.000000] #21 [0001c43000 - 0001c45000] BOOTMEM [ 0.000000] #22 [0001c45000 - 0001c85000] BOOTMEM [ 0.000000] #23 [0001c85000 - 0001ca5000] BOOTMEM [ 0.000000] Initializing HighMem for node 0 (00000000:00000000) [ 0.000000] Memory: 509828k/523188k available (5091k kernel code, 12968k reserved, 2440k data, 356k init, 0k highmem) [ 0.000000] virtual kernel memory layout: [ 0.000000] fixmap : 0xfffa3000 - 0xfffff000 ( 368 kB) [ 0.000000] pkmap : 0xffc00000 - 0xffe00000 (2048 kB) [ 0.000000] vmalloc : 0xe06ed000 - 0xffbfe000 ( 501 MB) [ 0.000000] lowmem : 0xc0000000 - 0xdfeed000 ( 510 MB) [ 0.000000] .init : 0xc175c000 - 0xc17b5000 ( 356 kB) [ 0.000000] .data : 0xc14f8e35 - 0xc175afe4 (2440 kB) [ 0.000000] .text : 0xc1000000 - 0xc14f8e35 (5091 kB) [ 0.000000] Checking if this processor honours the WP bit even in supervisor mode...Ok. [ 0.000000] Hierarchical RCU implementation. [ 0.000000] RCU-based detection of stalled CPUs is disabled. [ 0.000000] Verbose stalled-CPUs detection is disabled. [ 0.000000] NR_IRQS:288 [ 0.000000] Console: colour VGA+ 80x50 [ 0.000000] console [tty0] enabled [ 0.000000] console [ttyS0] enabled [ 0.000000] Fast TSC calibration using PIT [ 0.000000] Detected 501.221 MHz processor. [ 0.020014] Calibrating delay loop (skipped), value calculated using timer frequency.. 1002.44 BogoMIPS (lpj=5012210) [ 0.033010] pid_max: default: 32768 minimum: 301 [ 0.040245] Mount-cache hash table entries: 512 [ 0.045477] CPU serial number disabled. [ 0.050037] mce: CPU supports 5 MCE banks [ 0.054251] Performance Events: [ 0.057342] no APIC, boot with the "lapic" boot parameter to force-enable it. [ 0.060024] no hardware sampling interrupt available. [ 0.070021] p6 PMU driver. [ 0.072926] ... version: 0 [ 0.077129] ... bit width: 32 [ 0.080022] ... generic registers: 2 [ 0.084244] ... value mask: 00000000ffffffff [ 0.090021] ... max period: 000000007fffffff [ 0.095478] ... fixed-purpose events: 0 [ 0.100020] ... event mask: 0000000000000003 [ 0.105533] CPU: Intel Pentium III (Katmai) stepping 02 [ 0.114924] ACPI: Core revision 20100428 [ 0.125968] ACPI: setting ELCR to 0200 (from 0000) [ 0.130032] ACPI: FADT smi_command is not set, mode transitions not supported. [ 0.137646] ACPI: SCI_EN status: 1 [ 0.140024] ACPI: FADT smi_command is not set, mode transitions not supported. [ 0.147644] ACPI: SCI_EN status: 1 [ 0.150841] devtmpfs: initialized [ 0.155904] NET: Registered protocol family 16 [ 0.163413] ACPI: bus type pci registered [ 0.171702] PCI: PCI BIOS revision 2.10 entry at 0xffe77, last bus=1 [ 0.178271] PCI: Using configuration type 1 for base access [ 0.276065] bio: create slab <bio-0> at 0 [ 0.289230] ACPI: Interpreter enabled [ 0.290147] ACPI: (supports S0 S1 S2 S3 S5) [ 0.295061] ACPI: Using PIC for interrupt routing [ 0.319114] ACPI: No dock devices found. [ 0.320114] PCI: DMI: pci_use_crs=1 pci_probe=0000000b [ 0.325407] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug [ 0.331781] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff]) [ 0.343577] pci_root PNP0A03:00: host bridge window [io 0x0000-0x0cf7] [ 0.350113] pci_root PNP0A03:00: host bridge window [io 0x0d00-0xffff] [ 0.360038] pci_root PNP0A03:00: host bridge window [mem 0x20000000-0xffffffff] [ 0.370566] * Found PM-Timer Bug on the chipset. Due to workarounds for a bug, [ 0.370574] * this clock source is slow. Consider trying other clock sources [ 0.380096] pci 0000:00:04.3: quirk: [io 0xe400-0xe43f] claimed by PIIX4 ACPI [ 0.390036] pci 0000:00:04.3: quirk: [io 0x0f00-0x0f0f] claimed by PIIX4 SMB [ 0.400527] pci 0000:00:01.0: PCI bridge to [bus 01-01] [ 0.417502] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 10 11 12) *0, disabled. [ 0.425108] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 10 11 12) *0, disabled. [ 0.435050] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 7 10 11 12) *0, disabled. [ 0.445057] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 10 11 12) *0, disabled. [ 0.455640] vgaarb: device added: PCI:0000:00:0c.0,decodes=io+mem,owns=io+mem,locks=none [ 0.460096] vgaarb: loaded [ 0.464385] SCSI subsystem initialized [ 0.472061] usbcore: registered new interface driver usbfs [ 0.480474] usbcore: registered new interface driver hub [ 0.486473] usbcore: registered new device driver usb [ 0.492657] Advanced Linux Sound Architecture Driver Version 1.0.23. [ 0.500422] PCI: Using ACPI for IRQ routing [ 0.506809] cfg80211: Calling CRDA to update world regulatory domain [ 0.510567] Switching to clocksource tsc [ 0.520250] pnp: PnP ACPI init [ 0.523568] ACPI: bus type pnp registered [ 0.530439] ERROR: Unable to locate IOAPIC for GSI 1 [ 0.536605] ERROR: Unable to locate IOAPIC for GSI 12 [ 0.542893] ERROR: Unable to locate IOAPIC for GSI 6 [ 0.550609] pnp: PnP ACPI: found 5 devices [ 0.554863] ACPI: ACPI bus type pnp unregistered [ 0.559822] system 00:04: [io 0xe400-0xe43f] has been reserved [ 0.565953] system 00:04: [io 0x0f00-0x0f0f] has been reserved [ 0.572157] system 00:04: [mem 0xff800000-0xffffffff] has been reserved [ 0.653284] pci 0000:00:01.0: PCI bridge to [bus 01-01] [ 0.658730] pci 0000:00:01.0: bridge window [io disabled] [ 0.664639] pci 0000:00:01.0: bridge window [mem disabled] [ 0.670550] pci 0000:00:01.0: bridge window [mem pref disabled] [ 0.677091] NET: Registered protocol family 2 [ 0.681913] IP route cache hash table entries: 4096 (order: 2, 16384 bytes) [ 0.689638] TCP established hash table entries: 16384 (order: 5, 131072 bytes) [ 0.697862] TCP bind hash table entries: 16384 (order: 4, 65536 bytes) [ 0.704980] TCP: Hash tables configured (established 16384 bind 16384) [ 0.711710] TCP reno registered [ 0.715075] UDP hash table entries: 256 (order: 0, 4096 bytes) [ 0.721180] UDP-Lite hash table entries: 256 (order: 0, 4096 bytes) [ 0.727928] NET: Registered protocol family 1 [ 0.732959] RPC: Registered udp transport module. [ 0.737875] RPC: Registered tcp transport module. [ 0.742935] RPC: Registered tcp NFSv4.1 backchannel transport module. [ 0.749649] pci 0000:00:00.0: Limiting direct PCI/PCI transfers [ 0.756186] kvm: no hardware support [ 0.760076] has_svm: not amd [ 0.763161] kvm: no hardware support [ 0.768562] platform rtc_cmos: registered platform RTC device (no PNP device found) [ 0.783023] VFS: Disk quotas dquot_6.5.2 [ 0.787238] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes) [ 0.795198] fuse init (API version 7.14) [ 0.800786] Btrfs loaded [ 0.803572] msgmni has been set to 995 [ 0.809702] io scheduler noop registered [ 0.813838] io scheduler deadline registered [ 0.818385] io scheduler cfq registered (default) [ 0.827368] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input0 [ 0.835241] ACPI: Power Button [PWRF] [ 1.387649] lp: driver loaded but no devices found [ 1.392977] Linux agpgart interface v0.103 [ 1.397556] agpgart-intel 0000:00:00.0: Intel 440BX Chipset [ 1.421908] agpgart-intel 0000:00:00.0: AGP aperture is 256M @ 0xe0000000 [ 1.430195] [drm] Initialized drm 1.1.0 20060810 [ 1.435404] [drm] radeon kernel modesetting enabled. [ 1.441523] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled [ 1.448620] serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A [ 1.456233] serial8250: ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A [ 1.469916] parport0: PC-style at 0x378 (0x778) [PCSPP,TRISTATE,EPP] [ 1.477276] parport0: irq 7 detected [ 1.560065] lp0: using parport0 (polling). [ 1.573877] loop: module loaded [ 1.580950] scsi0 : ata_piix [ 1.585086] scsi1 : ata_piix [ 1.588981] ata1: PATA max UDMA/33 cmd 0x1f0 ctl 0x3f6 bmdma 0x1420 irq 14 [ 1.596158] ata2: PATA max UDMA/33 cmd 0x170 ctl 0x376 bmdma 0x1428 irq 15 [ 1.609413] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k6-NAPI [ 1.616678] e1000: Copyright (c) 1999-2006 Intel Corporation. [ 1.623186] e1000e: Intel(R) PRO/1000 Network Driver - 1.0.2-k4 [ 1.629395] e1000e: Copyright (c) 1999 - 2009 Intel Corporation. [ 1.637221] e100: Intel(R) PRO/100 Network Driver, 3.5.24-k2-NAPI [ 1.643612] e100: Copyright(c) 1999-2006 Intel Corporation [ 1.654073] tun: Universal TUN/TAP device driver, 1.6 [ 1.659458] tun: (C) 1999-2004 Max Krasnyansky maxk@qualcomm.com [ 1.666843] r8169 Gigabit Ethernet driver 2.3LK-NAPI loaded [ 1.674388] ACPI: PCI Interrupt Link [LNKD] enabled at IRQ 11 [ 1.689610] r8169 0000:00:09.0: PCI INT A -> Link[LNKD] -> GSI 11 (level, low) -> IRQ 11 [ 1.698168] r8169 0000:00:09.0: (unregistered net_device): no PCI Express capability [ 1.707107] r8169 0000:00:09.0: eth0: RTL8110s at 0xe0704000, 00:08:54:38:a1:44, XID 04000000 IRQ 11 [ 1.722213] console [netcon0] enabled [ 1.726084] netconsole: network logging started [ 1.730926] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver [ 1.738046] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver [ 1.744970] uhci_hcd: USB Universal Host Controller Interface driver [ 1.751812] uhci_hcd 0000:00:04.2: PCI INT D -> Link[LNKD] -> GSI 11 (level, low) -> IRQ 11 [ 1.760657] uhci_hcd 0000:00:04.2: UHCI Host Controller [ 1.766160] uhci_hcd 0000:00:04.2: new USB bus registered, assigned bus number 1 [ 1.774070] uhci_hcd 0000:00:04.2: irq 11, io base 0x00001400 [ 1.782234] hub 1-0:1.0: USB hub found [ 1.786230] hub 1-0:1.0: 2 ports detected [ 1.791224] Initializing USB Mass Storage driver... [ 1.796765] usbcore: registered new interface driver usb-storage [ 1.803095] USB Mass Storage support registered. [ 1.809199] PNP: PS/2 Controller [PNP0303:KBD,PNP0f13:MOU] at 0x60,0x64 irq 1,12 [ 1.817389] ata1.00: ATA-6: WDC WD1200JB-00DUA0, 65.13G65, max UDMA/100 [ 1.824264] ata1.00: 234441648 sectors, multi 0: LBA48 [ 1.832453] serio: i8042 KBD port at 0x60,0x64 irq 1 [ 1.837625] serio: i8042 AUX port at 0x60,0x64 irq 12 [ 1.845732] mice: PS/2 mouse device common for all mice [ 1.853133] input: PC Speaker as /devices/platform/pcspkr/input/input1 [ 1.860802] rtc_cmos rtc_cmos: RTC can wake from S4 [ 1.866788] rtc_cmos rtc_cmos: rtc core: registered rtc_cmos as rtc0 [ 1.873560] rtc0: alarms up to one month, 114 bytes nvram [ 1.879842] i2c /dev entries driver [ 1.883982] ata1.00: configured for UDMA/33 [ 1.889217] scsi 0:0:0:0: Direct-Access ATA WDC WD1200JB-00D 65.1 PQ: 0 ANSI: 5 [ 1.901906] sd 0:0:0:0: [sda] 234441648 512-byte logical blocks: (120 GB/111 GiB) [ 1.911646] piix4_smbus 0000:00:04.3: SMBus Host Controller at 0xf00, revision 0 [ 1.919817] input: AT Raw Set 2 keyboard as /devices/platform/i8042/serio0/input/input2 [ 1.928927] sd 0:0:0:0: Attached scsi generic sg0 type 0 [ 1.935157] sd 0:0:0:0: [sda] Write Protect is off [ 1.941860] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA [ 1.955158] coretemp: CPU (model=0x7) has no thermal sensor. [ 1.961398] sda: sda1 sda2 sda3 < sda5 > sda4 [ 2.024169] sd 0:0:0:0: [sda] Attached SCSI disk [ 2.110100] usb 1-1: new low speed USB device using uhci_hcd and address 2 [ 2.342160] Software Watchdog Timer: 0.07 initialized. soft_noboot=0 soft_margin=60 sec (nowayout= 0) [ 2.351723] md: raid1 personality registered for level 1 [ 2.358459] device-mapper: ioctl: 4.17.0-ioctl (2010-03-05) initialised: dm-devel@redhat.com [ 2.367679] cpuidle: using governor ladder [ 2.372082] cpuidle: using governor menu [ 2.409011] input: Microsoft Microsoft 5-Button Mouse with IntelliEye(TM) as /devices/pci0000:00/0000:00:04.2/usb1/1-1/1-1:1.0/input/input3 [ 2.422751] generic-usb 0003:045E:0047.0001: input: USB HID v1.10 Mouse [Microsoft Microsoft 5-Button Mouse with IntelliEye(TM)] on usb-0000:00:04.2-1/input0 [ 2.437597] usbcore: registered new interface driver usbhid [ 2.443477] usbhid: USB HID core driver [ 2.447528] ramzswap: num_devices not specified. Using default: 1 [ 2.453864] ramzswap: Creating 1 devices ... [ 2.462241] ALSA device list: [ 2.465365] No soundcards found. [ 2.468987] u32 classifier [ 2.471991] Actions configured [ 2.475612] Netfilter messages via NETLINK v0.30. [ 2.480650] nf_conntrack version 0.5.0 (7966 buckets, 31864 max) [ 2.487494] ctnetlink v0.93: registering with nfnetlink. [ 2.493259] IPv4 over IPv4 tunneling driver [ 2.498974] ip_tables: (C) 2000-2006 Netfilter Core Team [ 2.504777] TCP bic registered [ 2.507995] TCP cubic registered [ 2.511487] TCP westwood registered [ 2.515183] TCP vegas registered [ 2.518837] NET: Registered protocol family 10 [ 2.525549] ip6_tables: (C) 2000-2006 Netfilter Core Team [ 2.531403] IPv6 over IPv4 tunneling driver [ 2.537852] NET: Registered protocol family 17 [ 2.542668] lib80211: common routines for IEEE802.11 drivers [ 2.548627] Using IPI Shortcut mode [ 2.555356] rtc_cmos rtc_cmos: setting system clock to 2010-12-01 21:56:43 UTC (1291240603) [ 2.564577] md: Waiting for all devices to be available before autodetect [ 2.571727] md: If you don't use raid, use raid=noautodetect [ 2.578890] md: Autodetecting RAID arrays. [ 2.583339] md: Scanned 0 and added 0 devices. [ 2.588039] md: autorun ... [ 2.591107] md: ... autorun DONE. [ 2.623263] EXT4-fs (sda2): mounted filesystem with ordered data mode. Opts: (null) [ 2.631628] VFS: Mounted root (ext2 filesystem) readonly on device 8:2. [ 2.655607] devtmpfs: mounted [ 2.658915] Freeing unused kernel memory: 356k freed [ 2.666126] Write protecting the kernel text: 5092k [ 2.671612] Write protecting the kernel read-only data: 1896k
INIT: version 2.88 booting booting... Starting the hotplug events dispatcher: udevd[ 4.537857] udev[1260]: starting version 163
Build fix for src/arch/i386/boot/acpi.c if !CONFIG_SMP Also check for acpi_slp_type 2 in acpi_is_wakeup, since S2 uses the same acpi wakeup vector as S3. Add _PTS/_WAK methods to turn off/on the CPU/case fans and blink the power LED while sleeping. acpi_get_sleep_type() is in a seperate file i82371eb_wakeup.c because it is used in both romstage and ramstage after patch 3/3, whereas i82371eb_early_pm.c is used only in romstage. I used the name acpi_get_sleep_type instead of acpi_is_wakeup_early because I think acpi_is_wakeup_early is a bit misleading as a name since it doesn't return a boolean value.
Other chipsets so far only ever set acpi_slp_type to 0 and 3, so the added check for acpi_slp_type == 2 (resume from S2) should not change behaviour of other boards: northbridge/intel/i945/northbridge.c:256:extern u8 acpi_slp_type; northbridge/intel/i945/northbridge.c:263: acpi_slp_type=0; northbridge/intel/i945/northbridge.c:267: acpi_slp_type=3; northbridge/intel/i945/northbridge.c:271: acpi_slp_type=0; southbridge/intel/i82801gx/i82801gx_lpc.c:171:extern u8 acpi_slp_type; southbridge/via/vt8237r/vt8237r_lpc.c:149:extern u8 acpi_slp_type; southbridge/via/vt8237r/vt8237r_lpc.c:238: acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; southbridge/via/vt8237r/vt8237r_lpc.c:239: printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type);
Signed-off-by: Tobias Diedrich ranma+coreboot@tdiedrich.de
---
Index: src/arch/i386/boot/acpi.c =================================================================== --- src/arch/i386/boot/acpi.c.orig 2010-12-01 17:50:18.000000000 +0100 +++ src/arch/i386/boot/acpi.c 2010-12-01 17:54:01.000000000 +0100 @@ -481,7 +481,8 @@
static int acpi_is_wakeup(void) { - return (acpi_slp_type == 3); + /* Both resume from S2 and resume from S3 restart at CPU reset */ + return (acpi_slp_type == 3 || acpi_slp_type == 2); }
static acpi_rsdp_t *valid_rsdp(acpi_rsdp_t *rsdp) @@ -567,9 +568,11 @@ return wake_vec; }
+#if CONFIG_SMP extern char *lowmem_backup; extern char *lowmem_backup_ptr; extern int lowmem_backup_size; +#endif
#define WAKEUP_BASE 0x600
@@ -588,12 +591,14 @@ return; }
+#if CONFIG_SMP // FIXME: This should go into the ACPI backup memory, too. No pork saussages. /* * Just restore the SMP trampoline and continue with wakeup on * assembly level. */ memcpy(lowmem_backup_ptr, lowmem_backup, lowmem_backup_size); +#endif
/* Copy wakeup trampoline in place. */ memcpy((void *)WAKEUP_BASE, &__wakeup, (size_t)&__wakeup_size); Index: src/southbridge/intel/i82371eb/Kconfig =================================================================== --- src/southbridge/intel/i82371eb/Kconfig.orig 2010-12-01 17:50:18.000000000 +0100 +++ src/southbridge/intel/i82371eb/Kconfig 2010-12-01 17:53:27.000000000 +0100 @@ -1,6 +1,7 @@ config SOUTHBRIDGE_INTEL_I82371EB bool select TINY_BOOTBLOCK + select HAVE_ACPI_RESUME if HAVE_ACPI_TABLES
config BOOTBLOCK_SOUTHBRIDGE_INIT string Index: src/southbridge/intel/i82371eb/i82371eb_smbus.c =================================================================== --- src/southbridge/intel/i82371eb/i82371eb_smbus.c.orig 2010-12-01 17:50:26.000000000 +0100 +++ src/southbridge/intel/i82371eb/i82371eb_smbus.c 2010-12-01 17:57:09.000000000 +0100 @@ -22,6 +22,7 @@ */
#include <arch/io.h> +#include <arch/acpi.h> #include <console/console.h> #include <stdint.h> #include <device/device.h> @@ -87,7 +88,13 @@ outw(0xffff, DEFAULT_PMBASE + GLBSTS); outl(0xffffffff, DEFAULT_PMBASE + DEVSTS);
- /* set pmcntrl default */ +#if CONFIG_HAVE_ACPI_RESUME == 1 + /* this reads PMCNTRL, so we have to call it before writing the + * default value */ + acpi_slp_type = acpi_get_sleep_type(); +#endif + + /* set PMCNTRL default */ outw(SUS_TYP_S0|SCI_EN, DEFAULT_PMBASE + PMCNTRL); }
Index: src/lib/cbmem.c =================================================================== --- src/lib/cbmem.c.orig 2010-12-01 17:50:18.000000000 +0100 +++ src/lib/cbmem.c 2010-12-01 17:54:01.000000000 +0100 @@ -198,8 +198,10 @@ void cbmem_initialize(void) { #if CONFIG_HAVE_ACPI_RESUME - if (acpi_slp_type == 3) { + /* Both resume from S2 and resume from S3 restart at CPU reset */ + if (acpi_slp_type == 3 || acpi_slp_type == 2) { if (!cbmem_reinit(high_tables_base)) { + printk(BIOS_DEBUG, "cbmem_reinit failed\n"); /* Something went wrong, our high memory area got wiped */ acpi_slp_type = 0; cbmem_init(high_tables_base, high_tables_size); Index: src/southbridge/intel/i82371eb/i82371eb_wakeup.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ src/southbridge/intel/i82371eb/i82371eb_wakeup.c 2010-12-01 17:53:27.000000000 +0100 @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Uwe Hermann uwe@hermann-uwe.de + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/io.h> +#include <console/console.h> +#include "i82371eb.h" + +int acpi_get_sleep_type(void); + +/* + * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142 + * + * 0: soft off/suspend to disk S5 + * 1: suspend to ram S3 + * 2: powered on suspend, context lost S2 + * Note: 'context lost' means the CPU restarts at the reset + * vector + * 3: powered on suspend, CPU context lost S1 + * Note: Looks like 'CPU context lost' does _not_ mean the + * CPU restarts at the reset vector. Most likely only + * caches are lost, so both 0x3 and 0x4 map to acpi S1 + * 4: powered on suspend, context maintained S1 + * 5: working (clock control) S0 + * 6: reserved + * 7: reserved + */ +static const u8 acpi_sus_to_slp_typ[8] = { + 5, 3, 2, 1, 1, 0, 0, 0 +}; + +int acpi_get_sleep_type(void) +{ + u16 reg, result; + + reg = inw(DEFAULT_PMBASE + PMCNTRL); + result = acpi_sus_to_slp_typ[(reg >> 10) & 7]; + + printk(BIOS_DEBUG, "Wakeup from ACPI sleep type S%d (PMCNTRL=%04x)\n", result, reg); + + return result; +} Index: src/southbridge/intel/i82371eb/Makefile.inc =================================================================== --- src/southbridge/intel/i82371eb/Makefile.inc.orig 2010-12-01 17:50:18.000000000 +0100 +++ src/southbridge/intel/i82371eb/Makefile.inc 2010-12-01 17:53:54.000000000 +0100 @@ -26,6 +26,7 @@ driver-y += i82371eb_reset.c driver-$(CONFIG_HAVE_ACPI_TABLES) += i82371eb_fadt.c driver-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.c +driver-$(CONFIG_HAVE_ACPI_RESUME) += i82371eb_wakeup.c
romstage-y += i82371eb_early_pm.c romstage-y += i82371eb_early_smbus.c Index: src/mainboard/asus/p2b/dsdt.asl =================================================================== --- src/mainboard/asus/p2b/dsdt.asl.orig 2010-12-01 17:51:01.000000000 +0100 +++ src/mainboard/asus/p2b/dsdt.asl 2010-12-01 17:53:53.000000000 +0100 @@ -21,27 +21,51 @@
DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) { - /* For now only define 2 power states: - * - S0 which is fully on - * - S5 which is soft off - * Any others would involve declaring the wake up methods. - */ - - /* intel i82371eb (piix4e) datasheet, section 7.2.3, page 142 */ /* - 000b / 0x0: soft off/suspend to disk (soff/std) s5 - 001b / 0x1: suspend to ram (str) s3 - 010b / 0x2: powered on suspend, context lost (poscl) s1 - 011b / 0x3: powered on suspend, cpu context lost (posccl) s2 - 100b / 0x4: powered on suspend, context maintained (pos) s4 - 101b / 0x5: working (clock control) s0 - 110b / 0x6: reserved - 111b / 0x7: reserved - */ + * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142 + * + * 0: soft off/suspend to disk S5 + * 1: suspend to ram S3 + * 2: powered on suspend, context lost S2 + * Note: 'context lost' means the CPU restarts at the reset + * vector + * 3: powered on suspend, CPU context lost S1 + * Note: Looks like 'CPU context lost' does _not_ mean the + * CPU restarts at the reset vector. Most likely only + * caches are lost, so both 0x3 and 0x4 map to acpi S1 + * 4: powered on suspend, context maintained S1 + * 5: working (clock control) S0 + * 6: reserved + * 7: reserved + */ Name (_S0, Package () { 0x05, 0x05, 0x00, 0x00 }) Name (_S1, Package () { 0x03, 0x03, 0x00, 0x00 }) Name (_S5, Package () { 0x00, 0x00, 0x00, 0x00 })
+ OperationRegion (SIO1, SystemIO, Add(DEFAULT_PMBASE, GPO0), 2) + Field (SIO1, ByteAcc, NoLock, Preserve) + { + FANP, 1, /* CPU/case fan power */ + Offset (0x01), + PLED, 1, + } + + Method (_PTS, 1, NotSerialized) + { + /* Disable fan, blink power led */ + Store (Zero, FANP) + Store (Zero, PLED) + } + + Method (_WAK, 1, NotSerialized) + { + /* Re-enable fan, stop power led blinking */ + Store (One, FANP) + Store (One, PLED) + /* wake OK */ + Return(Package(0x02){0x00, 0x00}) + } + /* Root of the bus hierarchy */ Scope (_SB) {
On Wed, Dec 01, 2010 at 08:46:56PM +0100, Tobias Diedrich wrote:
Signed-off-by: Tobias Diedrich ranma+coreboot@tdiedrich.de
Looks good (though not tested on hardware by me).
Acked-by: Uwe Hermann uwe@hermann-uwe.de
Index: src/arch/i386/boot/acpi.c
--- src/arch/i386/boot/acpi.c.orig 2010-12-01 17:50:18.000000000 +0100 +++ src/arch/i386/boot/acpi.c 2010-12-01 17:54:01.000000000 +0100
Hm, are you diffing this stuff by hand? If so, "svn diff > foo.patch" from the top-level dir is much simpler.
Index: src/southbridge/intel/i82371eb/i82371eb_smbus.c
--- src/southbridge/intel/i82371eb/i82371eb_smbus.c.orig 2010-12-01 17:50:26.000000000 +0100 +++ src/southbridge/intel/i82371eb/i82371eb_smbus.c 2010-12-01 17:57:09.000000000 +0100 @@ -87,7 +88,13 @@ outw(0xffff, DEFAULT_PMBASE + GLBSTS); outl(0xffffffff, DEFAULT_PMBASE + DEVSTS);
- /* set pmcntrl default */
+#if CONFIG_HAVE_ACPI_RESUME == 1
No "== 1" needed.
Index: src/lib/cbmem.c
--- src/lib/cbmem.c.orig 2010-12-01 17:50:18.000000000 +0100 +++ src/lib/cbmem.c 2010-12-01 17:54:01.000000000 +0100 @@ -198,8 +198,10 @@ void cbmem_initialize(void) { #if CONFIG_HAVE_ACPI_RESUME
- if (acpi_slp_type == 3) {
- /* Both resume from S2 and resume from S3 restart at CPU reset */
- if (acpi_slp_type == 3 || acpi_slp_type == 2) { if (!cbmem_reinit(high_tables_base)) {
printk(BIOS_DEBUG, "cbmem_reinit failed\n");
Does printk work at this stage already? Hm, guess it should.
Index: src/southbridge/intel/i82371eb/i82371eb_wakeup.c
--- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ src/southbridge/intel/i82371eb/i82371eb_wakeup.c 2010-12-01 17:53:27.000000000 +0100 @@ -0,0 +1,59 @@ +/*
- This file is part of the coreboot project.
- Copyright (C) 2010 Uwe Hermann uwe@hermann-uwe.de
Nope, (C) Tobias Diedrich, I didn't write any of this.
Uwe.
Uwe Hermann wrote:
On Wed, Dec 01, 2010 at 08:46:56PM +0100, Tobias Diedrich wrote:
Signed-off-by: Tobias Diedrich ranma+coreboot@tdiedrich.de
Looks good (though not tested on hardware by me).
Acked-by: Uwe Hermann uwe@hermann-uwe.de
Great :)
Index: src/arch/i386/boot/acpi.c
--- src/arch/i386/boot/acpi.c.orig 2010-12-01 17:50:18.000000000 +0100 +++ src/arch/i386/boot/acpi.c 2010-12-01 17:54:01.000000000 +0100
Hm, are you diffing this stuff by hand? If so, "svn diff > foo.patch" from the top-level dir is much simpler.
No, I'm using quilt.
Index: src/southbridge/intel/i82371eb/i82371eb_smbus.c
--- src/southbridge/intel/i82371eb/i82371eb_smbus.c.orig 2010-12-01 17:50:26.000000000 +0100 +++ src/southbridge/intel/i82371eb/i82371eb_smbus.c 2010-12-01 17:57:09.000000000 +0100 @@ -87,7 +88,13 @@ outw(0xffff, DEFAULT_PMBASE + GLBSTS); outl(0xffffffff, DEFAULT_PMBASE + DEVSTS);
- /* set pmcntrl default */
+#if CONFIG_HAVE_ACPI_RESUME == 1
No "== 1" needed.
Ah, missed that one.
Index: src/lib/cbmem.c
--- src/lib/cbmem.c.orig 2010-12-01 17:50:18.000000000 +0100 +++ src/lib/cbmem.c 2010-12-01 17:54:01.000000000 +0100 @@ -198,8 +198,10 @@ void cbmem_initialize(void) { #if CONFIG_HAVE_ACPI_RESUME
- if (acpi_slp_type == 3) {
- /* Both resume from S2 and resume from S3 restart at CPU reset */
- if (acpi_slp_type == 3 || acpi_slp_type == 2) { if (!cbmem_reinit(high_tables_base)) {
printk(BIOS_DEBUG, "cbmem_reinit failed\n");Does printk work at this stage already? Hm, guess it should.
Yes, it does. :)
Index: src/southbridge/intel/i82371eb/i82371eb_wakeup.c
--- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ src/southbridge/intel/i82371eb/i82371eb_wakeup.c 2010-12-01 17:53:27.000000000 +0100 @@ -0,0 +1,59 @@ +/*
- This file is part of the coreboot project.
- Copyright (C) 2010 Uwe Hermann uwe@hermann-uwe.de
Nope, (C) Tobias Diedrich, I didn't write any of this.
Ah, that's still in there because I first added the function to i82371eb_pm.c, and later split it up and just copied the copyright header from that file...
Rediff against r6176 to account for file renames and p2b dsdt fix.
Build fix for src/arch/i386/boot/acpi.c if !CONFIG_SMP Also check for acpi_slp_type 2 in acpi_is_wakeup, since S2 uses the same acpi wakeup vector as S3. Add _PTS/_WAK methods to turn off/on the CPU/case fans and blink the power LED while sleeping. acpi_get_sleep_type() is in a seperate file i82371eb_wakeup.c because it is used in both romstage and ramstage after patch 3/3, whereas i82371eb_early_pm.c is used only in romstage. I used the name acpi_get_sleep_type instead of acpi_is_wakeup_early because I think acpi_is_wakeup_early is a bit misleading as a name since it doesn't return a boolean value.
Other chipsets so far only ever set acpi_slp_type to 0 and 3, so the added check for acpi_slp_type == 2 (resume from S2) should not change behaviour of other boards: northbridge/intel/i945/northbridge.c:256:extern u8 acpi_slp_type; northbridge/intel/i945/northbridge.c:263: acpi_slp_type=0; northbridge/intel/i945/northbridge.c:267: acpi_slp_type=3; northbridge/intel/i945/northbridge.c:271: acpi_slp_type=0; southbridge/intel/i82801gx/i82801gx_lpc.c:171:extern u8 acpi_slp_type; southbridge/via/vt8237r/vt8237r_lpc.c:149:extern u8 acpi_slp_type; southbridge/via/vt8237r/vt8237r_lpc.c:238: acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; southbridge/via/vt8237r/vt8237r_lpc.c:239: printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type);
Signed-off-by: Tobias Diedrich ranma+coreboot@tdiedrich.de
---
Index: src/arch/x86/boot/acpi.c =================================================================== --- src/arch/x86/boot/acpi.c.orig 2010-12-13 23:10:14.000000000 +0100 +++ src/arch/x86/boot/acpi.c 2010-12-13 23:19:19.857939851 +0100 @@ -481,7 +481,8 @@
static int acpi_is_wakeup(void) { - return (acpi_slp_type == 3); + /* Both resume from S2 and resume from S3 restart at CPU reset */ + return (acpi_slp_type == 3 || acpi_slp_type == 2); }
static acpi_rsdp_t *valid_rsdp(acpi_rsdp_t *rsdp) @@ -567,9 +568,11 @@ return wake_vec; }
+#if CONFIG_SMP extern char *lowmem_backup; extern char *lowmem_backup_ptr; extern int lowmem_backup_size; +#endif
#define WAKEUP_BASE 0x600
@@ -588,12 +591,14 @@ return; }
+#if CONFIG_SMP // FIXME: This should go into the ACPI backup memory, too. No pork saussages. /* * Just restore the SMP trampoline and continue with wakeup on * assembly level. */ memcpy(lowmem_backup_ptr, lowmem_backup, lowmem_backup_size); +#endif
/* Copy wakeup trampoline in place. */ memcpy((void *)WAKEUP_BASE, &__wakeup, (size_t)&__wakeup_size); Index: src/southbridge/intel/i82371eb/Kconfig =================================================================== --- src/southbridge/intel/i82371eb/Kconfig.orig 2010-12-13 23:17:19.000000000 +0100 +++ src/southbridge/intel/i82371eb/Kconfig 2010-12-13 23:19:19.857939851 +0100 @@ -1,6 +1,7 @@ config SOUTHBRIDGE_INTEL_I82371EB bool select TINY_BOOTBLOCK + select HAVE_ACPI_RESUME if HAVE_ACPI_TABLES
config BOOTBLOCK_SOUTHBRIDGE_INIT string Index: src/lib/cbmem.c =================================================================== --- src/lib/cbmem.c.orig 2010-12-13 23:17:19.000000000 +0100 +++ src/lib/cbmem.c 2010-12-13 23:19:19.857939851 +0100 @@ -191,8 +191,10 @@ void cbmem_initialize(void) { #if CONFIG_HAVE_ACPI_RESUME - if (acpi_slp_type == 3) { + printk(BIOS_DEBUG, "%s: acpi_slp_type=%d\n", __func__, acpi_slp_type); + if (acpi_slp_type == 3 || acpi_slp_type == 2) { if (!cbmem_reinit(high_tables_base)) { + printk(BIOS_DEBUG, "cbmem_reinit failed\n"); /* Something went wrong, our high memory area got wiped */ acpi_slp_type = 0; cbmem_init(high_tables_base, high_tables_size); Index: src/southbridge/intel/i82371eb/wakeup.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ src/southbridge/intel/i82371eb/wakeup.c 2010-12-13 23:19:19.861940159 +0100 @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Uwe Hermann uwe@hermann-uwe.de + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/io.h> +#include <console/console.h> +#include "i82371eb.h" + +int acpi_get_sleep_type(void); + +/* + * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142 + * + * 0: soft off/suspend to disk S5 + * 1: suspend to ram S3 + * 2: powered on suspend, context lost S2 + * Note: 'context lost' means the CPU restarts at the reset + * vector + * 3: powered on suspend, CPU context lost S1 + * Note: Looks like 'CPU context lost' does _not_ mean the + * CPU restarts at the reset vector. Most likely only + * caches are lost, so both 0x3 and 0x4 map to acpi S1 + * 4: powered on suspend, context maintained S1 + * 5: working (clock control) S0 + * 6: reserved + * 7: reserved + */ +static const u8 acpi_sus_to_slp_typ[8] = { + 5, 3, 2, 1, 1, 0, 0, 0 +}; + +int acpi_get_sleep_type(void) +{ + u16 reg, result; + + reg = inw(DEFAULT_PMBASE + PMCNTRL); + result = acpi_sus_to_slp_typ[(reg >> 10) & 7]; + + printk(BIOS_DEBUG, "Wakeup from ACPI sleep type S%d (PMCNTRL=%04x)\n", result, reg); + + return result; +} Index: src/southbridge/intel/i82371eb/Makefile.inc =================================================================== --- src/southbridge/intel/i82371eb/Makefile.inc.orig 2010-12-13 23:17:19.000000000 +0100 +++ src/southbridge/intel/i82371eb/Makefile.inc 2010-12-13 23:19:19.861940159 +0100 @@ -26,6 +26,7 @@ driver-y += reset.c driver-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c driver-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.c +driver-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.c
romstage-y += early_pm.c romstage-y += early_smbus.c Index: src/mainboard/asus/p2b/dsdt.asl =================================================================== --- src/mainboard/asus/p2b/dsdt.asl.orig 2010-12-13 23:19:27.126498947 +0100 +++ src/mainboard/asus/p2b/dsdt.asl 2010-12-13 23:20:38.374976945 +0100 @@ -21,27 +21,51 @@
DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) { - /* For now only define 2 power states: - * - S0 which is fully on - * - S5 which is soft off - * Any others would involve declaring the wake up methods. - */ - - /* intel i82371eb (piix4e) datasheet, section 7.2.3, page 142 */ /* - 000b / 0x0: soft off/suspend to disk (soff/std) s5 - 001b / 0x1: suspend to ram (str) s3 - 010b / 0x2: powered on suspend, context lost (poscl) s1 - 011b / 0x3: powered on suspend, cpu context lost (posccl) s2 - 100b / 0x4: powered on suspend, context maintained (pos) s4 - 101b / 0x5: working (clock control) s0 - 110b / 0x6: reserved - 111b / 0x7: reserved - */ + * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142 + * + * 0: soft off/suspend to disk S5 + * 1: suspend to ram S3 + * 2: powered on suspend, context lost S2 + * Note: 'context lost' means the CPU restarts at the reset + * vector + * 3: powered on suspend, CPU context lost S1 + * Note: Looks like 'CPU context lost' does _not_ mean the + * CPU restarts at the reset vector. Most likely only + * caches are lost, so both 0x3 and 0x4 map to acpi S1 + * 4: powered on suspend, context maintained S1 + * 5: working (clock control) S0 + * 6: reserved + * 7: reserved + */ Name (_S0, Package () { 0x05, 0x05, 0x00, 0x00 }) Name (_S1, Package () { 0x03, 0x03, 0x00, 0x00 }) Name (_S5, Package () { 0x00, 0x00, 0x00, 0x00 })
+ OperationRegion (SIO1, SystemIO, Add(DEFAULT_PMBASE, GPO0), 2) + Field (SIO1, ByteAcc, NoLock, Preserve) + { + FANP, 1, /* CPU/case fan power */ + Offset (0x01), + PLED, 1, + } + + Method (_PTS, 1, NotSerialized) + { + /* Disable fan, blink power led */ + Store (Zero, FANP) + Store (Zero, PLED) + } + + Method (_WAK, 1, NotSerialized) + { + /* Re-enable fan, stop power led blinking */ + Store (One, FANP) + Store (One, PLED) + /* wake OK */ + Return(Package(0x02){0x00, 0x00}) + } + /* Root of the bus hierarchy */ Scope (_SB) { Index: src/southbridge/intel/i82371eb/smbus.c =================================================================== --- src/southbridge/intel/i82371eb/smbus.c.orig 2010-12-13 23:24:51.421203666 +0100 +++ src/southbridge/intel/i82371eb/smbus.c 2010-12-13 23:24:55.048796200 +0100 @@ -31,6 +31,11 @@ #include "i82371eb.h" #include "smbus.h"
+#if CONFIG_HAVE_ACPI_RESUME == 1 +extern u8 acpi_slp_type; +int acpi_get_sleep_type(void); +#endif + static void pwrmgt_enable(struct device *dev) { struct southbridge_intel_i82371eb_config *sb = dev->chip_info; @@ -87,7 +92,13 @@ outw(0xffff, DEFAULT_PMBASE + GLBSTS); outl(0xffffffff, DEFAULT_PMBASE + DEVSTS);
- /* set pmcntrl default */ +#if CONFIG_HAVE_ACPI_RESUME == 1 + /* this reads PMCNTRL, so we have to call it before writing the + * default value */ + acpi_slp_type = acpi_get_sleep_type(); +#endif + + /* set PMCNTRL default */ outw(SUS_TYP_S0|SCI_EN, DEFAULT_PMBASE + PMCNTRL); }
This adds a cbmem_toc_ptr_t structure, which is written just below the FADT, so we can find it using the FADP information. The actual writing is only implemented for the Intel 82371EB southbridge.
Also adds code to acpi.c resume codepath to use this pointer when the chipset has not overridden the weak get_cbmem_toc() function.
Effectively the latter part affects all boards that already implement ACPI S2 or S3 resume, but shouldn't change behaviour since none of them generate the structure:
asus/m2v asus/m4a785-m asus/m2v-mx_se gigabyte/ma78gm gigabyte/ma785gmt jetway/pa78vm5 iwill/dk8_htx asrock/939a785gmh amd/dbm690t amd/mahogany amd/tilapia_fam10 amd/pistachio amd/serengeti_cheetah_fam10 amd/serengeti_cheetah amd/mahogany_fam10 kontron/kt690 iei/kino-780am2-fam10 technexion/tim5690 technexion/tim8690
BTW, via/epia-m700 defines HAVE_ACPI_TABLES, but does not supply a dsdt.asl (only a get_dsdt script)
Signed-off-by: Tobias Diedrich ranma+coreboot@tdiedrich.de
---
Index: src/arch/i386/boot/acpi.c =================================================================== --- src/arch/i386/boot/acpi.c.orig 2010-12-01 19:11:35.000000000 +0100 +++ src/arch/i386/boot/acpi.c 2010-12-01 19:11:36.000000000 +0100 @@ -517,6 +517,7 @@ acpi_rsdt_t *rsdt; acpi_facs_t *facs; acpi_fadt_t *fadt; + cbmem_toc_ptr_t *cbmem_tocp; void *wake_vec; int i;
@@ -537,11 +538,22 @@ return NULL;
printk(BIOS_DEBUG, "RSDP found at %p\n", rsdp); + cbmem_tocp = (cbmem_toc_ptr_t *)(rsdp->rsdt_address - sizeof(cbmem_toc_ptr_t)); rsdt = (acpi_rsdt_t *) rsdp->rsdt_address;
end = (char *)rsdt + rsdt->header.length; printk(BIOS_DEBUG, "RSDT found at %p ends at %p\n", rsdt, end);
+ if (get_cbmem_toc() == 0) { /* Only use cbmem_tocp if there is no chipset override */ + if (cbmem_tocp->sig != CBMEM_TOC_PTR_SIG) { + printk(BIOS_DEBUG, "cbmem toc pointer not found at %p (sig %08x sz %d)\n", cbmem_tocp, cbmem_tocp->sig, sizeof(cbmem_toc_ptr_t)); + return NULL; + } + set_cbmem_toc(cbmem_tocp->ptr); + } else { + printk(BIOS_DEBUG, "cbmem toc is at %p\n", get_cbmem_toc()); + } + for (i = 0; ((char *)&rsdt->entry[i]) < end; i++) { fadt = (acpi_fadt_t *)rsdt->entry[i]; if (strncmp((char *)fadt, "FACP", 4) == 0) Index: src/southbridge/intel/i82371eb/acpi_tables.c =================================================================== --- src/southbridge/intel/i82371eb/acpi_tables.c.orig 2010-12-01 19:11:35.000000000 +0100 +++ src/southbridge/intel/i82371eb/acpi_tables.c 2010-12-01 19:11:36.000000000 +0100 @@ -26,6 +26,7 @@ #include <arch/smp/mpspec.h> #include <device/device.h> #include <device/pci_ids.h> +#include <cbmem.h> #include "i82371eb.h"
extern const unsigned char AmlCode[]; @@ -104,6 +105,7 @@ unsigned long __attribute__((weak)) write_acpi_tables(unsigned long start) { unsigned long current; + cbmem_toc_ptr_t *cbmem_tocp; acpi_rsdp_t *rsdp; acpi_rsdt_t *rsdt; acpi_fadt_t *fadt; @@ -113,20 +115,28 @@ acpi_header_t *dsdt;
/* Align ACPI tables to 16 byte. */ - start = (start + 0x0f) & -0x10; - current = start; + current = ALIGN(start, 16);
printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
/* We need at least an RSDP and an RSDT table. */ rsdp = (acpi_rsdp_t *) current; current += sizeof(acpi_rsdp_t); + + /* put cbmem toc ptr structure directly below rsdt */ + printk(BIOS_INFO, "ACPI: Writing cbmem_toc pointer at %lx...\n", current); + cbmem_tocp = (cbmem_toc_ptr_t *) current; + current += sizeof(cbmem_toc_ptr_t); + rsdt = (acpi_rsdt_t *) current; current += sizeof(acpi_rsdt_t);
/* Clear all table memory. */ memset((void *) start, 0, current - start);
+ cbmem_tocp->sig = CBMEM_TOC_PTR_SIG; + cbmem_tocp->ptr = get_cbmem_toc(); + acpi_write_rsdp(rsdp, rsdt, NULL); acpi_write_rsdt(rsdt);
Index: src/include/cbmem.h =================================================================== --- src/include/cbmem.h.orig 2010-12-01 19:11:35.000000000 +0100 +++ src/include/cbmem.h 2010-12-01 19:11:36.000000000 +0100 @@ -39,6 +39,13 @@ #define CBMEM_ID_RESUME 0x5245534d #define CBMEM_ID_NONE 0x00000000
+#define CBMEM_TOC_PTR_SIG 0x43425443 + +typedef struct cbmem_toc_ptr { + u32 sig; + void *ptr; +} __attribute__((packed)) cbmem_toc_ptr_t; + void cbmem_initialize(void);
void cbmem_init(u64 baseaddr, u64 size); Index: src/lib/cbmem.c =================================================================== --- src/lib/cbmem.c.orig 2010-12-01 19:11:35.000000000 +0100 +++ src/lib/cbmem.c 2010-12-01 19:11:36.000000000 +0100 @@ -52,6 +52,9 @@
static struct cbmem_entry *bss_cbmem_toc;
+/* chipset can override get/set_cbmem_toc to store the cbmem_toc address + * in nvram if available */ + struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) { return bss_cbmem_toc; @@ -59,7 +62,7 @@
void __attribute__((weak)) set_cbmem_toc(struct cbmem_entry * x) { - /* do nothing, this should be called by chipset to save TOC in NVRAM */ + bss_cbmem_toc = x; }
#endif
Hi,
In fact I was thinking that we can add custom "OEMx" tables to ACPI and dump them using acpi tools. I mean we can add the hooks to ACPI so cbmem stuff is available per table in ACPI.
The AMD chipsets needs to use NVRAM because there is stored DQS driving values for memory controller. Also the cbmem address is stored there because one cannot find it very easily if there is frambuffer (and on AMD all access is uncached that time). This NVRAM is not CMOS it is just 256 bytes of storage which survives S3 state.
Thanks, Rudolf
On 01.12.2010, at 11:46, Tobias Diedrich ranma+coreboot@tdiedrich.de wrote:
This adds a cbmem_toc_ptr_t structure, which is written just below the FADT, so we can find it using the FADP information. The actual writing is only implemented for the Intel 82371EB southbridge.
Why is that needed?
Stefan
Stefan Reinauer wrote:
On 01.12.2010, at 11:46, Tobias Diedrich ranma+coreboot@tdiedrich.de wrote:
This adds a cbmem_toc_ptr_t structure, which is written just below the FADT, so we can find it using the FADP information. The actual writing is only implemented for the Intel 82371EB southbridge.
Why is that needed?
There needs to be some way to find the backup area needed for saving the memory parts that will be overwritten by coreboot after disabling CAR. I chose to add a structure relative to the FADT address, because thats rather easy to find. And as Rudolf already said, maybe this should be exported as a coreboot-specific ACPI table (but that would make finding it a tad bit more complex I think). Another option would be to always use a fixed area directly after 1MB (as this should not be affected by framebuffers in main memory) instead of below TOM.
Another option would be to always use a fixed area directly after 1MB (as this should not be affected by framebuffers in main memory) instead of below TOM.
Nope the memory must be free (and not reserved) all bootloaders expect that it is free. ACPI specs says first hole can be 15-16MB.
Thanks, Rudolf
Rediffed against r6176 to account for renames.
This adds a cbmem_toc_ptr_t structure, which is written just below the FADT, so we can find it using the FADP information. The actual writing is only implemented for the Intel 82371EB southbridge.
Also adds code to acpi.c resume codepath to use this pointer when the chipset has not overridden the weak get_cbmem_toc() function.
Effectively the latter part affects all boards that already implement ACPI S2 or S3 resume, but shouldn't change behaviour since none of them generate the structure:
asus/m2v asus/m4a785-m asus/m2v-mx_se gigabyte/ma78gm gigabyte/ma785gmt jetway/pa78vm5 iwill/dk8_htx asrock/939a785gmh amd/dbm690t amd/mahogany amd/tilapia_fam10 amd/pistachio amd/serengeti_cheetah_fam10 amd/serengeti_cheetah amd/mahogany_fam10 kontron/kt690 iei/kino-780am2-fam10 technexion/tim5690 technexion/tim8690
BTW, via/epia-m700 defines HAVE_ACPI_TABLES, but does not supply a dsdt.asl (only a get_dsdt script)
Signed-off-by: Tobias Diedrich ranma+coreboot@tdiedrich.de
---
Index: src/arch/x86/boot/acpi.c =================================================================== --- src/arch/x86/boot/acpi.c.orig 2010-12-13 23:25:40.000000000 +0100 +++ src/arch/x86/boot/acpi.c 2010-12-13 23:26:07.781494511 +0100 @@ -517,6 +517,7 @@ acpi_rsdt_t *rsdt; acpi_facs_t *facs; acpi_fadt_t *fadt; + cbmem_toc_ptr_t *cbmem_tocp; void *wake_vec; int i;
@@ -537,11 +538,22 @@ return NULL;
printk(BIOS_DEBUG, "RSDP found at %p\n", rsdp); + cbmem_tocp = (cbmem_toc_ptr_t *)(rsdp->rsdt_address - sizeof(cbmem_toc_ptr_t)); rsdt = (acpi_rsdt_t *) rsdp->rsdt_address;
end = (char *)rsdt + rsdt->header.length; printk(BIOS_DEBUG, "RSDT found at %p ends at %p\n", rsdt, end);
+ if (get_cbmem_toc() == 0) { + if (cbmem_tocp->sig != CBMEM_TOC_PTR_SIG) { + printk(BIOS_DEBUG, "cbmem toc pointer not found at %p (sig %08x sz %d)\n", cbmem_tocp, cbmem_tocp->sig, sizeof(cbmem_toc_ptr_t)); + return NULL; + } + set_cbmem_toc(cbmem_tocp->ptr); + } else { + printk(BIOS_DEBUG, "cbmem toc is at %p\n", get_cbmem_toc()); + } + for (i = 0; ((char *)&rsdt->entry[i]) < end; i++) { fadt = (acpi_fadt_t *)rsdt->entry[i]; if (strncmp((char *)fadt, "FACP", 4) == 0) Index: src/southbridge/intel/i82371eb/acpi_tables.c =================================================================== --- src/southbridge/intel/i82371eb/acpi_tables.c.orig 2010-12-13 23:14:37.000000000 +0100 +++ src/southbridge/intel/i82371eb/acpi_tables.c 2010-12-13 23:26:39.262811755 +0100 @@ -26,6 +26,7 @@ #include <arch/smp/mpspec.h> #include <device/device.h> #include <device/pci_ids.h> +#include <cbmem.h> #include "i82371eb.h"
extern const unsigned char AmlCode[]; @@ -104,6 +105,7 @@ unsigned long __attribute__((weak)) write_acpi_tables(unsigned long start) { unsigned long current; + cbmem_toc_ptr_t *cbmem_tocp; acpi_rsdp_t *rsdp; acpi_rsdt_t *rsdt; acpi_fadt_t *fadt; @@ -113,20 +115,28 @@ acpi_header_t *dsdt;
/* Align ACPI tables to 16 byte. */ - start = (start + 0x0f) & -0x10; - current = start; + current = ALIGN(start, 16);
printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
/* We need at least an RSDP and an RSDT table. */ rsdp = (acpi_rsdp_t *) current; current += sizeof(acpi_rsdp_t); + + /* put cbmem toc ptr structure directly below rsdt */ + printk(BIOS_INFO, "ACPI: Writing cbmem_toc pointer at %lx...\n", current); + cbmem_tocp = (cbmem_toc_ptr_t *) current; + current += sizeof(cbmem_toc_ptr_t); + rsdt = (acpi_rsdt_t *) current; current += sizeof(acpi_rsdt_t);
/* Clear all table memory. */ memset((void *) start, 0, current - start);
+ cbmem_tocp->sig = CBMEM_TOC_PTR_SIG; + cbmem_tocp->ptr = get_cbmem_toc(); + acpi_write_rsdp(rsdp, rsdt, NULL); acpi_write_rsdt(rsdt);
Index: src/include/cbmem.h =================================================================== --- src/include/cbmem.h.orig 2010-12-13 23:10:11.000000000 +0100 +++ src/include/cbmem.h 2010-12-13 23:26:07.781494511 +0100 @@ -40,6 +40,13 @@ #define CBMEM_ID_RESUME 0x5245534d #define CBMEM_ID_NONE 0x00000000
+#define CBMEM_TOC_PTR_SIG 0x43425443 + +typedef struct cbmem_toc_ptr { + u32 sig; + void *ptr; +} __attribute__((packed)) cbmem_toc_ptr_t; + void cbmem_initialize(void);
void cbmem_init(u64 baseaddr, u64 size); Index: src/lib/cbmem.c =================================================================== --- src/lib/cbmem.c.orig 2010-12-13 23:25:40.000000000 +0100 +++ src/lib/cbmem.c 2010-12-13 23:26:07.781494511 +0100 @@ -39,6 +39,9 @@ #ifndef __PRE_RAM__ static struct cbmem_entry *bss_cbmem_toc;
+/* chipset can override get/set_cbmem_toc to store the cbmem_toc address + * in nvram if available */ + struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) { return bss_cbmem_toc; @@ -46,7 +49,7 @@
void __attribute__((weak)) set_cbmem_toc(struct cbmem_entry * x) { - /* do nothing, this should be called by chipset to save TOC in NVRAM */ + bss_cbmem_toc = x; } #else
On 13.12.2010, at 14:42, Tobias Diedrich ranma+coreboot@tdiedrich.de wrote:
BTW, via/epia-m700 defines HAVE_ACPI_TABLES, but does not supply a dsdt.asl (only a get_dsdt script)
We should disable that and drop the script. Using foreign DSDTs might be legally problematic..
Stefan
Slot-1 boards: asus/p3b-f asus/p2b-ds asus/p2b-f asus/p2b-d asus/p2b asus/p2b-ls azza/pt-6ibd gigabyte/ga-6bxc gigabyte/ga-6bxe compaq/deskpro_en_sff_p600 a-trend/atc-6220 a-trend/atc-6240 tyan/s1846 msi/ms6119 msi/ms6147 msi/ms6156 soyo/sy-6ba-plus-iii abit/be6-ii_v2_0 biostar/m6tba
Slot-1 boards with HAVE_ACPI_TABLES: asus/p2b
Abuild-tested. Tested on P2B (Slot1 440BX/82371EB). Tested on M2V (Socket AM2/K8T890/VT8237A) to make sure S3 still works with all 3 patches applied.
Signed-off-by: Tobias Diedrich ranma+coreboot@tdiedrich.de
---
Index: src/northbridge/intel/i440bx/northbridge.c =================================================================== --- src/northbridge/intel/i440bx/northbridge.c.orig 2010-12-01 19:11:34.000000000 +0100 +++ src/northbridge/intel/i440bx/northbridge.c 2010-12-01 19:11:40.000000000 +0100 @@ -9,6 +9,7 @@ #include <bitops.h> #include <cpu/cpu.h> #include <pc80/keyboard.h> +#include <cbmem.h> #include "chip.h" #include "northbridge.h" #include "i440bx.h" @@ -34,7 +35,7 @@ };
#if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +#define HIGH_TABLES_SIZE ((HIGH_MEMORY_SIZE + 1024) / 1024) extern uint64_t high_tables_base, high_tables_size; #endif
Index: src/cpu/intel/car/post_cache_as_ram.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ src/cpu/intel/car/post_cache_as_ram.c 2010-12-01 19:11:40.000000000 +0100 @@ -0,0 +1,248 @@ +/* + * This file is part of the coreboot project. + * + * original idea yhlu 6.2005 (assembler code) + * + * Copyright (C) 2010 Rudolf Marek r.marek@assembler.cz + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * be warned, this file will be used other cores and core 0 / node 0 + */ +#include <string.h> +#include <arch/stages.h> +#include <console/console.h> +#include <cpu/x86/mtrr.h> +#include <arch/acpi.h> +#define get_cbmem_toc get_cbmem_toc +#include <cbmem.h> +#include "cpu/x86/mtrr/earlymtrr.c" +// Now, this needs to be included because it relies on the symbol +// __PRE_RAM__ being set during CAR stage (in order to compile the +// BSS free versions of the functions). Either rewrite the code +// to be always BSS free, or invent a flag that's better suited than +// __PRE_RAM__ to determine whether we're in ram init stage (stage 1) +// +#include "lib/cbmem.c" + +#if CONFIG_RAMTOP <= 0x100000 + #error "You need to set CONFIG_RAMTOP greater than 1M" +#endif + +#define DCACHE_RAM_BASE (CONFIG_DCACHE_RAM_TOP - CONFIG_DCACHE_RAM_SIZE) + +static inline void print_debug_pcar(const char *strval, uint32_t val) +{ + printk(BIOS_DEBUG, "%s%08x\n", strval, val); +} + +/* from linux kernel 2.6.32 asm/string_32.h */ + +static void inline __attribute__((always_inline)) memcopy(void *dest, const void *src, unsigned long bytes) +{ + int d0, d1, d2; + asm volatile("cld ; rep ; movsl\n\t" + "movl %4,%%ecx\n\t" + "andl $3,%%ecx\n\t" + "jz 1f\n\t" + "rep ; movsb\n\t" + "1:" + : "=&c" (d0), "=&D" (d1), "=&S" (d2) + : "0" (bytes / 4), "g" (bytes), "1" ((long)dest), "2" ((long)src) + : "memory", "cc"); +} + +static u8 acpi_checksum(u8 *table, u32 length) +{ + u8 ret = 0; + while (length--) { + ret += *table; + table++; + } + return -ret; +} + +static int valid_rsdp(acpi_rsdp_t *rsdp) +{ + unsigned *sig; + sig = (void*)rsdp; + if (*sig != 0x20445352) + return 0; + sig++; + if (*sig != 0x20525450) + return 0; + + print_debug("Looking on "); + print_debug_hex32((u32)rsdp); + print_debug(" for valid checksum\n"); + + if (acpi_checksum((void *)rsdp, 20) != 0) + return 0; + print_debug("Checksum 1 passed\n"); + + if ((rsdp->revision > 1) && + (acpi_checksum((void *)rsdp, rsdp->length) != 0)) + return 0; + print_debug("Checksum 2 passed all OK\n"); + + return 1; +} + +struct cbmem_entry *get_cbmem_toc(void) +{ + char *p; + acpi_rsdp_t *rsdp; + cbmem_toc_ptr_t *cbmem_tocp; + + print_debug("Trying to find the backup area pointer...\n"); + + /* Find RSDP. */ + rsdp = NULL; + for (p = (char *)0xe0000; p < (char *)0xfffff; p += 16) { + rsdp = (acpi_rsdp_t *)p; + if (valid_rsdp(rsdp)) + break; + rsdp = NULL; + } + + if (rsdp == NULL) { + print_debug("RSDP not found\n"); + return NULL; + } + + cbmem_tocp = (cbmem_toc_ptr_t *)(rsdp->rsdt_address - sizeof(cbmem_toc_ptr_t)); + if (cbmem_tocp->sig != CBMEM_TOC_PTR_SIG) { + printk(BIOS_DEBUG, "cbmem toc pointer not found at %p (sig %08x sz %d)\n", cbmem_tocp, cbmem_tocp->sig, sizeof(cbmem_toc_ptr_t)); + return NULL; + } + + return cbmem_tocp->ptr; +} + +static inline void *backup_resume(void) { + unsigned long high_ram_base; + void *resume_backup_memory; + + /* Start address of high memory tables */ + high_ram_base = (u32) get_cbmem_toc(); + + print_debug_pcar("CBMEM TOC is at: ", high_ram_base); + print_debug_pcar("CBMEM TOC 0-size: ", (high_ram_base + HIGH_MEMORY_SIZE + 4096)); + + cbmem_reinit((u64)high_ram_base); + + resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + + /* copy 1MB - 64K to high tables ram_base to prevent memory corruption + * through stage 2. We could keep stuff like stack and heap in high tables + * memory completely, but that's a wonderful clean up task for another + * day. + */ + + if (resume_backup_memory) { + print_debug_pcar("Will copy coreboot region to: ", (uint32_t) resume_backup_memory); + /* copy only backup only memory used for CAR */ + memcopy(resume_backup_memory+HIGH_MEMORY_SAVE-CONFIG_DCACHE_RAM_SIZE, + (void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), + CONFIG_DCACHE_RAM_SIZE); //inline + } + + return resume_backup_memory; +} + +void enable_pm(void); +int acpi_get_sleep_type(void); + +void* acpi_resume_post_main(void); +void acpi_resume_post_cache_as_ram(void *resume_backup_memory); + +void* acpi_resume_post_main(void) +{ + int sleep_type; + void *resume_backup_memory = NULL; + + enable_pm(); + sleep_type = acpi_get_sleep_type(); + +#if 1 + { + /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */ + unsigned v_esp; + __asm__ volatile ( + "movl %%esp, %0\n\t" + : "=a" (v_esp) + ); + print_debug_pcar("v_esp=", v_esp); + } +#endif + + unsigned testx = 0x5a5a5a5a; + print_debug_pcar("testx = ", testx); + + /* copy data from cache as ram to + ram need to set CONFIG_RAMTOP to 2M and use var mtrr instead. + */ + if (sleep_type == 2 || sleep_type == 3) + resume_backup_memory = backup_resume(); + + printk(BIOS_DEBUG, "resume_backup_memory=%p\n", resume_backup_memory); + + print_debug("Copying data from cache to RAM -- switching to use RAM as stack... "); + + memcopy((void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), (void *)DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline + + __asm__ volatile ( + /* set new esp */ /* before CONFIG_RAMBASE */ + "subl %0, %%esp\n\t" + ::"a"( (DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) ) + /* discard all registers (eax is used for %0), so gcc redo everything + after the stack is moved */ + : "cc", "memory", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp" + ); + + /* We can put data to stack again */ + + /* only global variable sysinfo in cache need to be offset */ + print_debug("Done\n"); + print_debug_pcar("testx = ", testx); + + return resume_backup_memory; +} + +void acpi_resume_post_cache_as_ram(void *resume_backup_memory) +{ + print_debug("After cache as ram disabled \n"); + printk(BIOS_DEBUG, "resume_backup_memory=%p\n", resume_backup_memory); + + /* now copy the rest of the area, using the WB method because we already + run normal RAM */ + if (resume_backup_memory) { + memcopy(resume_backup_memory, + (void *)(CONFIG_RAMBASE), + (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE); + } + + print_debug("Clearing initial memory region: "); + + /* clear only coreboot used region of memory. Note: this may break ECC enabled boards */ + memset((void*) CONFIG_RAMBASE, 0, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE); + print_debug("Done\n"); + + /*copy and execute coreboot_ram */ + copy_and_run(0); + /* We will not return */ + + print_debug("should not be here -\n"); + for (;;); +} Index: src/cpu/intel/car/cache_as_ram.inc =================================================================== --- src/cpu/intel/car/cache_as_ram.inc.orig 2010-12-01 19:11:34.000000000 +0100 +++ src/cpu/intel/car/cache_as_ram.inc 2010-12-01 19:11:40.000000000 +0100 @@ -26,8 +26,12 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/lapic_def.h>
+#ifndef CONFIG_DCACHE_RAM_TOP +#define CONFIG_DCACHE_RAM_TOP 0xd0000 +#endif + #define CacheSize CONFIG_DCACHE_RAM_SIZE -#define CacheBase (0xd0000 - CacheSize) +#define CacheBase (CONFIG_DCACHE_RAM_TOP - CacheSize)
save_bist_result()
@@ -325,6 +329,11 @@ pushl %eax /* BIST */ call main
+#if CONFIG_HAVE_ACPI_RESUME && CONFIG_POST_CAR_RESUME + call acpi_resume_post_main + pushl %eax /* save resume_backup_memory pointer */ +#endif + /* We don't need CAR from now on. */
disable_cache() @@ -351,6 +360,13 @@
enable_cache();
+#if CONFIG_HAVE_ACPI_RESUME && CONFIG_POST_CAR_RESUME + popl %eax + movl %esp, %ebp + pushl %eax /* resume_backup_memory pointer */ + call acpi_resume_post_cache_as_ram +#endif + /* Clear boot_complete flag. */ xorl %ebp, %ebp __main: Index: src/arch/i386/include/arch/acpi.h =================================================================== --- src/arch/i386/include/arch/acpi.h.orig 2010-12-01 19:11:34.000000000 +0100 +++ src/arch/i386/include/arch/acpi.h 2010-12-01 19:11:40.000000000 +0100 @@ -357,6 +357,8 @@ u8 ec_id[]; /* EC ID */ } __attribute__ ((packed)) acpi_ecdt_t;
+#if !defined(__PRE_RAM__) + /* These are implemented by the target port or north/southbridge. */ unsigned long write_acpi_tables(unsigned long addr); unsigned long acpi_fill_madt(unsigned long current); @@ -431,6 +433,8 @@ /* cpu/intel/speedstep/acpi.c */ void generate_cpu_entries(void);
+#endif // __PRE_RAM__ + #else // CONFIG_GENERATE_ACPI_TABLES
#define write_acpi_tables(start) (start) Index: src/cpu/intel/Makefile.inc =================================================================== --- src/cpu/intel/Makefile.inc.orig 2010-12-01 19:11:34.000000000 +0100 +++ src/cpu/intel/Makefile.inc 2010-12-01 19:11:40.000000000 +0100 @@ -16,6 +16,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_PGA370) += socket_PGA370 subdirs-$(CONFIG_CPU_INTEL_SLOT_2) += slot_2 subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 +subdirs-$(CONFIG_CPU_INTEL) += car
#socket_mPGA604_533Mhz #socket_mPGA604_800Mhz Index: src/cpu/intel/car/Makefile.inc =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ src/cpu/intel/car/Makefile.inc 2010-12-01 19:11:40.000000000 +0100 @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Tobias Diedrich ranma+coreboot@tdiedrich.de +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-$(CONFIG_POST_CAR_RESUME) += post_cache_as_ram.c Index: src/cpu/intel/Kconfig =================================================================== --- src/cpu/intel/Kconfig.orig 2010-12-01 19:11:34.000000000 +0100 +++ src/cpu/intel/Kconfig 2010-12-01 19:11:40.000000000 +0100 @@ -28,3 +28,17 @@ source src/cpu/intel/socket_mPGA604/Kconfig source src/cpu/intel/socket_PGA370/Kconfig source src/cpu/intel/socket_441/Kconfig + +config CPU_INTEL + bool + default n + +config POST_CAR_RESUME + bool + default n + +config DCACHE_RAM_TOP + hex + default 0xd0000 + depends on CACHE_AS_RAM + depends on CPU_INTEL Index: src/mainboard/asus/p2b/dsdt.asl =================================================================== --- src/mainboard/asus/p2b/dsdt.asl.orig 2010-12-01 19:11:34.000000000 +0100 +++ src/mainboard/asus/p2b/dsdt.asl 2010-12-01 19:11:40.000000000 +0100 @@ -40,6 +40,11 @@ */ Name (_S0, Package () { 0x05, 0x05, 0x00, 0x00 }) Name (_S1, Package () { 0x03, 0x03, 0x00, 0x00 }) + Name (_S2, Package () { 0x02, 0x02, 0x00, 0x00 }) + Name (_S3, Package () { 0x01, 0x01, 0x00, 0x00 }) + /* Note: S4 would be suspend to disk, which would require smm code, + * but Linux and Windows handle suspend to disk themselves, so we + * don't need this */ Name (_S5, Package () { 0x00, 0x00, 0x00, 0x00 })
OperationRegion (SIO1, SystemIO, Add(DEFAULT_PMBASE, GPO0), 2) Index: src/southbridge/intel/i82371eb/Makefile.inc =================================================================== --- src/southbridge/intel/i82371eb/Makefile.inc.orig 2010-12-01 19:11:34.000000000 +0100 +++ src/southbridge/intel/i82371eb/Makefile.inc 2010-12-01 19:11:40.000000000 +0100 @@ -30,3 +30,4 @@
romstage-y += i82371eb_early_pm.c romstage-y += i82371eb_early_smbus.c +romstage-$(CONFIG_HAVE_ACPI_RESUME) += i82371eb_wakeup.c Index: src/cpu/intel/slot_1/Kconfig =================================================================== --- src/cpu/intel/slot_1/Kconfig.orig 2010-12-01 19:11:34.000000000 +0100 +++ src/cpu/intel/slot_1/Kconfig 2010-12-01 19:25:18.000000000 +0100 @@ -20,6 +20,9 @@ config CPU_INTEL_SLOT_1 bool select CACHE_AS_RAM + select CPU_INTEL + select POST_CAR_RESUME if GENERATE_ACPI_TABLES +
config DCACHE_RAM_SIZE hex
Rediffed against r6176 to account for renames.
Slot-1 boards: asus/p3b-f asus/p2b-ds asus/p2b-f asus/p2b-d asus/p2b asus/p2b-ls azza/pt-6ibd gigabyte/ga-6bxc gigabyte/ga-6bxe compaq/deskpro_en_sff_p600 a-trend/atc-6220 a-trend/atc-6240 tyan/s1846 msi/ms6119 msi/ms6147 msi/ms6156 soyo/sy-6ba-plus-iii abit/be6-ii_v2_0 biostar/m6tba
Slot-1 boards with HAVE_ACPI_TABLES: asus/p2b
Abuild-tested. Tested on P2B (Slot1 440BX/82371EB). Tested on M2V (Socket AM2/K8T890/VT8237A) to make sure S3 still works with all 3 patches applied.
(Rediffed patchset only non-abuild compile-tested due to hw currently not being accessible).
Signed-off-by: Tobias Diedrich ranma+coreboot@tdiedrich.de
---
Index: src/northbridge/intel/i440bx/northbridge.c =================================================================== --- src/northbridge/intel/i440bx/northbridge.c.orig 2010-12-13 23:34:06.190921624 +0100 +++ src/northbridge/intel/i440bx/northbridge.c 2010-12-13 23:34:14.042912591 +0100 @@ -9,6 +9,7 @@ #include <bitops.h> #include <cpu/cpu.h> #include <pc80/keyboard.h> +#include <cbmem.h> #include "chip.h" #include "northbridge.h" #include "i440bx.h" Index: src/cpu/intel/car/post_cache_as_ram.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ src/cpu/intel/car/post_cache_as_ram.c 2010-12-13 23:35:22.327299572 +0100 @@ -0,0 +1,240 @@ +/* + * This file is part of the coreboot project. + * + * original idea yhlu 6.2005 (assembler code) + * + * Copyright (C) 2010 Rudolf Marek r.marek@assembler.cz + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * be warned, this file will be used other cores and core 0 / node 0 + */ +#include <string.h> +#include <arch/stages.h> +#include <console/console.h> +#include <cpu/x86/mtrr.h> +#include <arch/acpi.h> +#include <cbmem.h> +#include "cpu/x86/mtrr/earlymtrr.c" + +#if CONFIG_RAMTOP <= 0x100000 + #error "You need to set CONFIG_RAMTOP greater than 1M" +#endif + +#define DCACHE_RAM_BASE (CONFIG_DCACHE_RAM_TOP - CONFIG_DCACHE_RAM_SIZE) + +static inline void print_debug_pcar(const char *strval, uint32_t val) +{ + printk(BIOS_DEBUG, "%s%08x\n", strval, val); +} + +/* from linux kernel 2.6.32 asm/string_32.h */ + +static void inline __attribute__((always_inline)) memcopy(void *dest, const void *src, unsigned long bytes) +{ + int d0, d1, d2; + asm volatile("cld ; rep ; movsl\n\t" + "movl %4,%%ecx\n\t" + "andl $3,%%ecx\n\t" + "jz 1f\n\t" + "rep ; movsb\n\t" + "1:" + : "=&c" (d0), "=&D" (d1), "=&S" (d2) + : "0" (bytes / 4), "g" (bytes), "1" ((long)dest), "2" ((long)src) + : "memory", "cc"); +} + +static u8 acpi_checksum(u8 *table, u32 length) +{ + u8 ret = 0; + while (length--) { + ret += *table; + table++; + } + return -ret; +} + +static int valid_rsdp(acpi_rsdp_t *rsdp) +{ + unsigned *sig; + sig = (void*)rsdp; + if (*sig != 0x20445352) + return 0; + sig++; + if (*sig != 0x20525450) + return 0; + + print_debug("Looking on "); + print_debug_hex32((u32)rsdp); + print_debug(" for valid checksum\n"); + + if (acpi_checksum((void *)rsdp, 20) != 0) + return 0; + print_debug("Checksum 1 passed\n"); + + if ((rsdp->revision > 1) && + (acpi_checksum((void *)rsdp, rsdp->length) != 0)) + return 0; + print_debug("Checksum 2 passed all OK\n"); + + return 1; +} + +struct cbmem_entry *get_cbmem_toc(void) +{ + char *p; + acpi_rsdp_t *rsdp; + cbmem_toc_ptr_t *cbmem_tocp; + + print_debug("Trying to find the backup area pointer...\n"); + + /* Find RSDP. */ + rsdp = NULL; + for (p = (char *)0xe0000; p < (char *)0xfffff; p += 16) { + rsdp = (acpi_rsdp_t *)p; + if (valid_rsdp(rsdp)) + break; + rsdp = NULL; + } + + if (rsdp == NULL) { + print_debug("RSDP not found\n"); + return NULL; + } + + cbmem_tocp = (cbmem_toc_ptr_t *)(rsdp->rsdt_address - sizeof(cbmem_toc_ptr_t)); + if (cbmem_tocp->sig != CBMEM_TOC_PTR_SIG) { + printk(BIOS_DEBUG, "cbmem toc pointer not found at %p (sig %08x sz %d)\n", cbmem_tocp, cbmem_tocp->sig, sizeof(cbmem_toc_ptr_t)); + return NULL; + } + + return cbmem_tocp->ptr; +} + +static inline void *backup_resume(void) { + unsigned long high_ram_base; + void *resume_backup_memory; + + /* Start address of high memory tables */ + high_ram_base = (u32) get_cbmem_toc(); + + print_debug_pcar("CBMEM TOC is at: ", high_ram_base); + print_debug_pcar("CBMEM TOC 0-size: ", (high_ram_base + HIGH_MEMORY_SIZE + 4096)); + + cbmem_reinit((u64)high_ram_base); + + resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + + /* copy 1MB - 64K to high tables ram_base to prevent memory corruption + * through stage 2. We could keep stuff like stack and heap in high tables + * memory completely, but that's a wonderful clean up task for another + * day. + */ + + if (resume_backup_memory) { + print_debug_pcar("Will copy coreboot region to: ", (uint32_t) resume_backup_memory); + /* copy only backup only memory used for CAR */ + memcopy(resume_backup_memory+HIGH_MEMORY_SAVE-CONFIG_DCACHE_RAM_SIZE, + (void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), + CONFIG_DCACHE_RAM_SIZE); //inline + } + + return resume_backup_memory; +} + +void enable_pm(void); +int acpi_get_sleep_type(void); + +void* acpi_resume_post_main(void); +void acpi_resume_post_cache_as_ram(void *resume_backup_memory); + +void* acpi_resume_post_main(void) +{ + int sleep_type; + void *resume_backup_memory = NULL; + + enable_pm(); + sleep_type = acpi_get_sleep_type(); + +#if 1 + { + /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */ + unsigned v_esp; + __asm__ volatile ( + "movl %%esp, %0\n\t" + : "=a" (v_esp) + ); + print_debug_pcar("v_esp=", v_esp); + } +#endif + + unsigned testx = 0x5a5a5a5a; + print_debug_pcar("testx = ", testx); + + /* copy data from cache as ram to + ram need to set CONFIG_RAMTOP to 2M and use var mtrr instead. + */ + if (sleep_type == 2 || sleep_type == 3) + resume_backup_memory = backup_resume(); + + printk(BIOS_DEBUG, "resume_backup_memory=%p\n", resume_backup_memory); + + print_debug("Copying data from cache to RAM -- switching to use RAM as stack... "); + + memcopy((void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), (void *)DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline + + __asm__ volatile ( + /* set new esp */ /* before CONFIG_RAMBASE */ + "subl %0, %%esp\n\t" + ::"a"( (DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) ) + /* discard all registers (eax is used for %0), so gcc redo everything + after the stack is moved */ + : "cc", "memory", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp" + ); + + /* We can put data to stack again */ + + /* only global variable sysinfo in cache need to be offset */ + print_debug("Done\n"); + print_debug_pcar("testx = ", testx); + + return resume_backup_memory; +} + +void acpi_resume_post_cache_as_ram(void *resume_backup_memory) +{ + print_debug("After cache as ram disabled \n"); + printk(BIOS_DEBUG, "resume_backup_memory=%p\n", resume_backup_memory); + + /* now copy the rest of the area, using the WB method because we already + run normal RAM */ + if (resume_backup_memory) { + memcopy(resume_backup_memory, + (void *)(CONFIG_RAMBASE), + (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE); + } + + print_debug("Clearing initial memory region: "); + + /* clear only coreboot used region of memory. Note: this may break ECC enabled boards */ + memset((void*) CONFIG_RAMBASE, 0, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE); + print_debug("Done\n"); + + /*copy and execute coreboot_ram */ + copy_and_run(0); + /* We will not return */ + + print_debug("should not be here -\n"); + for (;;); +} Index: src/cpu/intel/car/cache_as_ram.inc =================================================================== --- src/cpu/intel/car/cache_as_ram.inc.orig 2010-12-13 23:34:06.238921550 +0100 +++ src/cpu/intel/car/cache_as_ram.inc 2010-12-13 23:34:14.042912591 +0100 @@ -26,8 +26,12 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/lapic_def.h>
+#ifndef CONFIG_DCACHE_RAM_TOP +#define CONFIG_DCACHE_RAM_TOP 0xd0000 +#endif + #define CacheSize CONFIG_DCACHE_RAM_SIZE -#define CacheBase (0xd0000 - CacheSize) +#define CacheBase (CONFIG_DCACHE_RAM_TOP - CacheSize)
save_bist_result()
@@ -325,6 +329,11 @@ pushl %eax /* BIST */ call main
+#if CONFIG_HAVE_ACPI_RESUME && CONFIG_POST_CAR_RESUME + call acpi_resume_post_main + pushl %eax /* save resume_backup_memory pointer */ +#endif + /* We don't need CAR from now on. */
disable_cache() @@ -351,6 +360,13 @@
enable_cache();
+#if CONFIG_HAVE_ACPI_RESUME && CONFIG_POST_CAR_RESUME + popl %eax + movl %esp, %ebp + pushl %eax /* resume_backup_memory pointer */ + call acpi_resume_post_cache_as_ram +#endif + /* Clear boot_complete flag. */ xorl %ebp, %ebp __main: Index: src/arch/x86/include/arch/acpi.h =================================================================== --- src/arch/x86/include/arch/acpi.h.orig 2010-12-13 23:34:06.214921588 +0100 +++ src/arch/x86/include/arch/acpi.h 2010-12-13 23:34:14.042912591 +0100 @@ -357,6 +357,8 @@ u8 ec_id[]; /* EC ID */ } __attribute__ ((packed)) acpi_ecdt_t;
+#if !defined(__PRE_RAM__) + /* These are implemented by the target port or north/southbridge. */ unsigned long write_acpi_tables(unsigned long addr); unsigned long acpi_fill_madt(unsigned long current); @@ -431,6 +433,8 @@ /* cpu/intel/speedstep/acpi.c */ void generate_cpu_entries(void);
+#endif // __PRE_RAM__ + #else // CONFIG_GENERATE_ACPI_TABLES
#define write_acpi_tables(start) (start) Index: src/cpu/intel/Makefile.inc =================================================================== --- src/cpu/intel/Makefile.inc.orig 2010-12-13 23:34:06.298921457 +0100 +++ src/cpu/intel/Makefile.inc 2010-12-13 23:34:14.042912591 +0100 @@ -16,6 +16,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_PGA370) += socket_PGA370 subdirs-$(CONFIG_CPU_INTEL_SLOT_2) += slot_2 subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 +subdirs-$(CONFIG_CPU_INTEL) += car
#socket_mPGA604_533Mhz #socket_mPGA604_800Mhz Index: src/cpu/intel/car/Makefile.inc =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ src/cpu/intel/car/Makefile.inc 2010-12-13 23:34:14.042912591 +0100 @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Tobias Diedrich ranma+coreboot@tdiedrich.de +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-$(CONFIG_POST_CAR_RESUME) += post_cache_as_ram.c Index: src/cpu/intel/Kconfig =================================================================== --- src/cpu/intel/Kconfig.orig 2010-12-13 23:34:06.290921469 +0100 +++ src/cpu/intel/Kconfig 2010-12-13 23:34:14.042912591 +0100 @@ -28,3 +28,17 @@ source src/cpu/intel/socket_mPGA604/Kconfig source src/cpu/intel/socket_PGA370/Kconfig source src/cpu/intel/socket_441/Kconfig + +config CPU_INTEL + bool + default n + +config POST_CAR_RESUME + bool + default n + +config DCACHE_RAM_TOP + hex + default 0xd0000 + depends on CACHE_AS_RAM + depends on CPU_INTEL Index: src/mainboard/asus/p2b/dsdt.asl =================================================================== --- src/mainboard/asus/p2b/dsdt.asl.orig 2010-12-13 23:34:06.146921691 +0100 +++ src/mainboard/asus/p2b/dsdt.asl 2010-12-13 23:34:14.042912591 +0100 @@ -40,6 +40,11 @@ */ Name (_S0, Package () { 0x05, 0x05, 0x00, 0x00 }) Name (_S1, Package () { 0x03, 0x03, 0x00, 0x00 }) + Name (_S2, Package () { 0x02, 0x02, 0x00, 0x00 }) + Name (_S3, Package () { 0x01, 0x01, 0x00, 0x00 }) + /* Note: S4 would be suspend to disk, which would require smm code, + * but Linux and Windows handle suspend to disk themselves, so we + * don't need this */ Name (_S5, Package () { 0x00, 0x00, 0x00, 0x00 })
OperationRegion (SIO1, SystemIO, Add(DEFAULT_PMBASE, GPO0), 2) Index: src/southbridge/intel/i82371eb/Makefile.inc =================================================================== --- src/southbridge/intel/i82371eb/Makefile.inc.orig 2010-12-13 23:34:06.166921662 +0100 +++ src/southbridge/intel/i82371eb/Makefile.inc 2010-12-13 23:34:14.042912591 +0100 @@ -30,3 +30,4 @@
romstage-y += early_pm.c romstage-y += early_smbus.c +romstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.c Index: src/cpu/intel/slot_1/Kconfig =================================================================== --- src/cpu/intel/slot_1/Kconfig.orig 2010-12-13 23:34:06.330921409 +0100 +++ src/cpu/intel/slot_1/Kconfig 2010-12-13 23:34:14.042912591 +0100 @@ -20,6 +20,8 @@ config CPU_INTEL_SLOT_1 bool select CACHE_AS_RAM + select CPU_INTEL + select POST_CAR_RESUME
config DCACHE_RAM_SIZE hex
Hi Tobias,
thanks a lot for your work. It's good to see people bringing new features into more coreboot boards.
However, unfortunately, I have to put a big NACK on this one...
The below is very ugly, sorry to say. Please rework that code. I know it's taken from the AMD cache as ram code, and I've been spending quite some time of getting rid of post_cache_as_ram.c on all platforms. I skipped AMD because I had no test platform and the code was harder to transform than on the other platforms, but I'm very unhappy about seeing this might sneak back in... There has to be a better way.
* Tobias Diedrich ranma+coreboot@tdiedrich.de [101213 23:46]:
Index: src/cpu/intel/car/post_cache_as_ram.c
--- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ src/cpu/intel/car/post_cache_as_ram.c 2010-12-13 23:35:22.327299572 +0100 @@ -0,0 +1,240 @@ +/*
- This file is part of the coreboot project.
- original idea yhlu 6.2005 (assembler code)
- Copyright (C) 2010 Rudolf Marek r.marek@assembler.cz
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; version 2 of the License.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- be warned, this file will be used other cores and core 0 / node 0
- */
+#include <string.h> +#include <arch/stages.h> +#include <console/console.h> +#include <cpu/x86/mtrr.h> +#include <arch/acpi.h> +#include <cbmem.h> +#include "cpu/x86/mtrr/earlymtrr.c"
+#if CONFIG_RAMTOP <= 0x100000
- #error "You need to set CONFIG_RAMTOP greater than 1M"
+#endif
RAMTOP should actually be set to exactly 1M. But this is not a good place for this check.
+#define DCACHE_RAM_BASE (CONFIG_DCACHE_RAM_TOP - CONFIG_DCACHE_RAM_SIZE)
Isn't the BASE defined somewhere already?
+static inline void print_debug_pcar(const char *strval, uint32_t val) +{
- printk(BIOS_DEBUG, "%s%08x\n", strval, val);
+}
Why this wrapper?
+/* from linux kernel 2.6.32 asm/string_32.h */
+static void inline __attribute__((always_inline)) memcopy(void *dest, const void *src, unsigned long bytes) +{
- int d0, d1, d2;
- asm volatile("cld ; rep ; movsl\n\t"
"movl %4,%%ecx\n\t""andl $3,%%ecx\n\t""jz 1f\n\t""rep ; movsb\n\t""1:": "=&c" (d0), "=&D" (d1), "=&S" (d2): "0" (bytes / 4), "g" (bytes), "1" ((long)dest), "2" ((long)src): "memory", "cc");+}
This is unneeded and was introduced to work around some shortcomings in the AMD code that have been fixed since. If anything, it should be dropped from the AMD code, too.
+static u8 acpi_checksum(u8 *table, u32 length) +{
- u8 ret = 0;
- while (length--) {
ret += *table;table++;- }
- return -ret;
+}
+static int valid_rsdp(acpi_rsdp_t *rsdp) +{
- unsigned *sig;
- sig = (void*)rsdp;
- if (*sig != 0x20445352)
return 0;- sig++;
- if (*sig != 0x20525450)
return 0;- print_debug("Looking on ");
- print_debug_hex32((u32)rsdp);
- print_debug(" for valid checksum\n");
- if (acpi_checksum((void *)rsdp, 20) != 0)
return 0;- print_debug("Checksum 1 passed\n");
- if ((rsdp->revision > 1) &&
(acpi_checksum((void *)rsdp, rsdp->length) != 0))return 0;- print_debug("Checksum 2 passed all OK\n");
- return 1;
+}
+struct cbmem_entry *get_cbmem_toc(void) +{
- char *p;
- acpi_rsdp_t *rsdp;
- cbmem_toc_ptr_t *cbmem_tocp;
- print_debug("Trying to find the backup area pointer...\n");
- /* Find RSDP. */
- rsdp = NULL;
- for (p = (char *)0xe0000; p < (char *)0xfffff; p += 16) {
rsdp = (acpi_rsdp_t *)p;if (valid_rsdp(rsdp))break;rsdp = NULL;- }
- if (rsdp == NULL) {
print_debug("RSDP not found\n");return NULL;- }
- cbmem_tocp = (cbmem_toc_ptr_t *)(rsdp->rsdt_address - sizeof(cbmem_toc_ptr_t));
- if (cbmem_tocp->sig != CBMEM_TOC_PTR_SIG) {
printk(BIOS_DEBUG, "cbmem toc pointer not found at %p (sig %08x sz %d)\n", cbmem_tocp, cbmem_tocp->sig, sizeof(cbmem_toc_ptr_t));return NULL;- }
- return cbmem_tocp->ptr;
+}
+static inline void *backup_resume(void) {
function curly brackets go on the next line
- unsigned long high_ram_base;
- void *resume_backup_memory;
- /* Start address of high memory tables */
- high_ram_base = (u32) get_cbmem_toc();
- print_debug_pcar("CBMEM TOC is at: ", high_ram_base);
- print_debug_pcar("CBMEM TOC 0-size: ", (high_ram_base + HIGH_MEMORY_SIZE + 4096));
- cbmem_reinit((u64)high_ram_base);
- resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
- /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
* through stage 2. We could keep stuff like stack and heap in high tables* memory completely, but that's a wonderful clean up task for another* day.*/- if (resume_backup_memory) {
print_debug_pcar("Will copy coreboot region to: ", (uint32_t) resume_backup_memory);/* copy only backup only memory used for CAR */memcopy(resume_backup_memory+HIGH_MEMORY_SAVE-CONFIG_DCACHE_RAM_SIZE,(void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE),CONFIG_DCACHE_RAM_SIZE); //inline- }
- return resume_backup_memory;
+}
Can't this code be called from romstage.c?
+void enable_pm(void); +int acpi_get_sleep_type(void);
+void* acpi_resume_post_main(void); +void acpi_resume_post_cache_as_ram(void *resume_backup_memory);
+void* acpi_resume_post_main(void) +{
- int sleep_type;
- void *resume_backup_memory = NULL;
- enable_pm();
- sleep_type = acpi_get_sleep_type();
+#if 1
- {
- /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
- unsigned v_esp;
- __asm__ volatile (
"movl %%esp, %0\n\t": "=a" (v_esp)- );
- print_debug_pcar("v_esp=", v_esp);
- }
+#endif
- unsigned testx = 0x5a5a5a5a;
- print_debug_pcar("testx = ", testx);
- /* copy data from cache as ram to
ram need to set CONFIG_RAMTOP to 2M and use var mtrr instead.*/- if (sleep_type == 2 || sleep_type == 3)
resume_backup_memory = backup_resume();- printk(BIOS_DEBUG, "resume_backup_memory=%p\n", resume_backup_memory);
- print_debug("Copying data from cache to RAM -- switching to use RAM as stack... ");
- memcopy((void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), (void *)DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline
- __asm__ volatile (
/* set new esp */ /* before CONFIG_RAMBASE */"subl %0, %%esp\n\t"::"a"( (DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) )/* discard all registers (eax is used for %0), so gcc redo everythingafter the stack is moved */: "cc", "memory", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp"- );
This is very ugly and should be done completely in assembler, if it's needed at all. It's awfully fragile and ugly
- /* We can put data to stack again */
- /* only global variable sysinfo in cache need to be offset */
- print_debug("Done\n");
- print_debug_pcar("testx = ", testx);
- return resume_backup_memory;
+}
+void acpi_resume_post_cache_as_ram(void *resume_backup_memory) +{
- print_debug("After cache as ram disabled \n");
- printk(BIOS_DEBUG, "resume_backup_memory=%p\n", resume_backup_memory);
- /* now copy the rest of the area, using the WB method because we already
run normal RAM */- if (resume_backup_memory) {
memcopy(resume_backup_memory,(void *)(CONFIG_RAMBASE),(CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE);- }
- print_debug("Clearing initial memory region: ");
- /* clear only coreboot used region of memory. Note: this may break ECC enabled boards */
- memset((void*) CONFIG_RAMBASE, 0, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE);
- print_debug("Done\n");
- /*copy and execute coreboot_ram */
- copy_and_run(0);
- /* We will not return */
- print_debug("should not be here -\n");
- for (;;);
+}
Please have a look at how getac/p470 does resume.
Index: src/cpu/intel/Makefile.inc
--- src/cpu/intel/Makefile.inc.orig 2010-12-13 23:34:06.298921457 +0100 +++ src/cpu/intel/Makefile.inc 2010-12-13 23:34:14.042912591 +0100 @@ -16,6 +16,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_PGA370) += socket_PGA370 subdirs-$(CONFIG_CPU_INTEL_SLOT_2) += slot_2 subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 +subdirs-$(CONFIG_CPU_INTEL) += car
#socket_mPGA604_533Mhz #socket_mPGA604_800Mhz
This should only be added from the socket directory of a given CPU
Index: src/cpu/intel/Kconfig
--- src/cpu/intel/Kconfig.orig 2010-12-13 23:34:06.290921469 +0100 +++ src/cpu/intel/Kconfig 2010-12-13 23:34:14.042912591 +0100 @@ -28,3 +28,17 @@ source src/cpu/intel/socket_mPGA604/Kconfig source src/cpu/intel/socket_PGA370/Kconfig source src/cpu/intel/socket_441/Kconfig
+config CPU_INTEL
- bool
- default n
This sounds too generic. Not all Intel CPUs use this.
+config DCACHE_RAM_TOP
- hex
- default 0xd0000
- depends on CACHE_AS_RAM
- depends on CPU_INTEL
It looks like this value could be calculated from the cache as ram base + size. Should not be part of Kconfig, as it's another variable that will get copied blindly over time.
Stefan
2010/12/1 Tobias Diedrich ranma+coreboot@tdiedrich.de:
Add support for S2/S3 sleep (resume from reset vector).
Part1 adds the get_acpi_sleep_type() function to read the sleep type and sets acpi_slp_type.
Part2 adds generic infrastructure to save a pointer to cbmem_toc in the ACPI memory area. This could also replace the vt8237 solution of using special nvram (which the I82371EB chipset doesn't have).
Part3 adds the necessary code to save the memory area overwritten by ramstage into the reserved backup memory space.
All three patches are abuild-tested and should be applied after the ssdt cpu generation patch (http://www.coreboot.org/pipermail/coreboot/2010-December/062229.html).
I tested the complete stack on both the P2B board which I wrote it for and the amd am2 base M2V board to check that it doesn't break anything there.
Keith: It should probably be rather simple to enable this on P2B-LS/P3B-F too if you'd like to test.
Tested on my P2B, findings can be found later in this message.
Here is the serial log (cold boot, s3, poweroff). Note: While S5 poweroff works and does poweroff the power supply, S3 seems to still need some magic to really power off, even though we tell the chipset to go to S3 sleep. However investigating this will have to wait since I won't have access to these boards, starting tomorrow, for the next month or so.
coreboot-4.0-r6132M Wed Dec 1 21:51:49 CET 2010 starting... Wakeup from ACPI sleep type S5 (PMCNTRL=0000) v_esp=000cffc8 testx = 5a5a5a5a resume_backup_memory=00000000 Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a After cache as ram disabled resume_backup_memory=00000000 Clearing initial memory region: Done Loading image. Check CBFS header at fffffc9e magic is 4f524243 Found CBFS header at fffffc9e Check fallback/romstage CBFS: follow chain: fffc0000 + 38 + 3699 + align -> fffc3700 Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (212992 bytes), entry @ 0x100000 Stage: done loading. Jumping to image. coreboot-4.0-r6132M Wed Dec 1 21:51:49 CET 2010 booting... clocks_per_usec: 502 Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:04.0: enabled 1 PNP: 03f0.0: enabled 1 PNP: 03f0.1: enabled 1 PNP: 03f0.2: enabled 1 PNP: 03f0.3: enabled 1 PNP: 03f0.5: enabled 1 PNP: 03f0.7: enabled 1 PNP: 03f0.8: enabled 1 PNP: 03f0.9: enabled 1 PNP: 03f0.a: enabled 1 PCI: 00:04.1: enabled 1 PCI: 00:04.2: enabled 1 PCI: 00:04.3: enabled 1 Compare with tree... Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:04.0: enabled 1 PNP: 03f0.0: enabled 1 PNP: 03f0.1: enabled 1 PNP: 03f0.2: enabled 1 PNP: 03f0.3: enabled 1 PNP: 03f0.5: enabled 1 PNP: 03f0.7: enabled 1 PNP: 03f0.8: enabled 1 PNP: 03f0.9: enabled 1 PNP: 03f0.a: enabled 1 PCI: 00:04.1: enabled 1 PCI: 00:04.2: enabled 1 PCI: 00:04.3: enabled 1 scan_static_bus for Root Device APIC_CLUSTER: 0 enabled Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/7190] ops PCI: 00:00.0 [8086/7190] enabled PCI: 00:01.0 [8086/7191] enabled PCI: 00:04.0 [8086/7110] bus ops PCI: 00:04.0 [8086/7110] enabled PCI: 00:04.1 [8086/7111] ops PCI: 00:04.1 [8086/7111] enabled PCI: 00:04.2 [8086/7112] ops PCI: 00:04.2 [8086/7112] enabled PCI: 00:04.3 [8086/7113] bus ops Wakeup from ACPI sleep type S5 (PMCNTRL=0000) PCI: 00:04.3 [8086/7113] enabled PCI: 00:09.0 [10ec/8169] enabled PCI: 00:0c.0 [102b/0519] enabled do_pci_scan_bridge for PCI: 00:01.0 PCI: pci_scan_bus for bus 01 PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 scan_static_bus for PCI: 00:04.0 PNP: 03f0.0 enabled PNP: 03f0.1 enabled PNP: 03f0.2 enabled PNP: 03f0.3 enabled PNP: 03f0.5 enabled PNP: 03f0.7 enabled PNP: 03f0.8 enabled PNP: 03f0.9 enabled PNP: 03f0.a enabled PNP: 03f0.6 enabled scan_static_bus for PCI: 00:04.0 done scan_static_bus for PCI: 00:04.3 scan_static_bus for PCI: 00:04.3 done PCI: pci_scan_bus returning with max=001 scan_static_bus for Root Device done done Setting up VGA for PCI: 00:0c.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:04.0 read_resources bus 0 link: 0 PNP: 03f0.8 missing read_resources PNP: 03f0.9 missing read_resources PCI: 00:04.0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 10 PCI: 00:01.0 PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24 PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:04.0 child on link 0 PNP: 03f0.0 PCI: 00:04.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:04.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags d0000200 index 2 PNP: 03f0.0 PNP: 03f0.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 03f0.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 03f0.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 03f0.1 PNP: 03f0.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 03f0.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 03f0.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 03f0.2 PNP: 03f0.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 03f0.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 03f0.3 PNP: 03f0.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 03f0.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 03f0.5 PNP: 03f0.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60 PNP: 03f0.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62 PNP: 03f0.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 03f0.5 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 72 PNP: 03f0.7 PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 PNP: 03f0.7 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 62 PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 03f0.8 PNP: 03f0.9 PNP: 03f0.a PNP: 03f0.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 03f0.6 PNP: 03f0.6 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 PNP: 03f0.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PCI: 00:04.1 PCI: 00:04.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:04.2 PCI: 00:04.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:04.3 PCI: 00:04.3 resource base e400 size 40 align 0 gran 0 limit ffff flags d0000100 index 1 PCI: 00:04.3 resource base f00 size 10 align 0 gran 0 limit ffff flags d0000100 index 2 PCI: 00:09.0 PCI: 00:09.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 PCI: 00:09.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 14 PCI: 00:09.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30 PCI: 00:0c.0 PCI: 00:0c.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10 PCI: 00:0c.0 resource base 0 size 800000 align 23 gran 23 limit ffffffff flags 1200 index 14 PCI: 00:0c.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:09.0 10 * [0x0 - 0xff] io PCI: 00:04.2 20 * [0x400 - 0x41f] io PCI: 00:04.1 20 * [0x420 - 0x42f] io PCI_DOMAIN: 0000 compute_resources_io: base: 430 size: 430 align: 8 gran: 0 limit: ffff done PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:00.0 10 * [0x0 - 0xfffffff] prefmem PCI: 00:0c.0 14 * [0x10000000 - 0x107fffff] prefmem PCI: 00:09.0 30 * [0x10800000 - 0x1081ffff] mem PCI: 00:0c.0 30 * [0x10820000 - 0x1082ffff] mem PCI: 00:0c.0 10 * [0x10830000 - 0x10833fff] mem PCI: 00:09.0 14 * [0x10834000 - 0x108340ff] mem PCI_DOMAIN: 0000 compute_resources_mem: base: 10834100 size: 10834100 align: 28 gran: 0 limit: ffffffff done avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:01.0 constrain_resources: PCI: 00:04.0 constrain_resources: PNP: 03f0.0 constrain_resources: PNP: 03f0.1 constrain_resources: PNP: 03f0.2 constrain_resources: PNP: 03f0.3 constrain_resources: PNP: 03f0.5 constrain_resources: PNP: 03f0.7 constrain_resources: PNP: 03f0.8 constrain_resources: PNP: 03f0.9 constrain_resources: PNP: 03f0.a constrain_resources: PNP: 03f0.6 constrain_resources: PCI: 00:04.1 constrain_resources: PCI: 00:04.2 constrain_resources: PCI: 00:04.3 constrain_resources: PCI: 00:09.0 constrain_resources: PCI: 00:0c.0 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff lim->base 00001000 lim->limit 0000e3ff avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff lim->base 00000000 lim->limit ff7fffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:430 align:8 gran:0 limit:e3ff Assigned: PCI: 00:09.0 10 * [0x1000 - 0x10ff] io Assigned: PCI: 00:04.2 20 * [0x1400 - 0x141f] io Assigned: PCI: 00:04.1 20 * [0x1420 - 0x142f] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 1430 size: 430 align: 8 gran: 0 done PCI: 00:01.0 allocate_resources_io: base:e3ff size:0 align:12 gran:12 limit:e3ff PCI: 00:01.0 allocate_resources_io: next_base: e3ff size: 0 align: 12 gran: 12 done PCI_DOMAIN: 0000 allocate_resources_mem: base:e0000000 size:10834100 align:28 gran:0 limit:ff7fffff Assigned: PCI: 00:00.0 10 * [0xe0000000 - 0xefffffff] prefmem Assigned: PCI: 00:0c.0 14 * [0xf0000000 - 0xf07fffff] prefmem Assigned: PCI: 00:09.0 30 * [0xf0800000 - 0xf081ffff] mem Assigned: PCI: 00:0c.0 30 * [0xf0820000 - 0xf082ffff] mem Assigned: PCI: 00:0c.0 10 * [0xf0830000 - 0xf0833fff] mem Assigned: PCI: 00:09.0 14 * [0xf0834000 - 0xf08340ff] mem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: f0834100 size: 10834100 align: 28 gran: 0 done PCI: 00:01.0 allocate_resources_prefmem: base:ff7fffff size:0 align:20 gran:20 limit:ff7fffff PCI: 00:01.0 allocate_resources_prefmem: next_base: ff7fffff size: 0 align: 20 gran: 20 done PCI: 00:01.0 allocate_resources_mem: base:ff7fffff size:0 align:20 gran:20 limit:ff7fffff PCI: 00:01.0 allocate_resources_mem: next_base: ff7fffff size: 0 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 Setting RAM size to 512 MB PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:00.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem PCI: 00:01.0 1c <- [0x000000e3ff - 0x000000e3fe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:01.0 24 <- [0x00ff7fffff - 0x00ff7ffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:01.0 20 <- [0x00ff7fffff - 0x00ff7ffffe] size 0x00000000 gran 0x14 bus 01 mem PCI: 00:04.0 assign_resources, bus 0 link: 0 PNP: 03f0.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 io PNP: 03f0.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00 irq PNP: 03f0.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00 drq PNP: 03f0.1 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io PNP: 03f0.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq ERROR: PNP: 03f0.1 74 drq size: 0x0000000001 not assigned PNP: 03f0.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 03f0.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 03f0.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io PNP: 03f0.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq PNP: 03f0.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io PNP: 03f0.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io PNP: 03f0.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq PNP: 03f0.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq ERROR: PNP: 03f0.7 60 io size: 0x0000000001 not assigned ERROR: PNP: 03f0.7 62 io size: 0x0000000002 not assigned ERROR: PNP: 03f0.7 70 irq size: 0x0000000001 not assigned ERROR: PNP: 03f0.a 70 irq size: 0x0000000001 not assigned ERROR: PNP: 03f0.6 60 io size: 0x0000000008 not assigned ERROR: PNP: 03f0.6 70 irq size: 0x0000000001 not assigned PCI: 00:04.0 assign_resources, bus 0 link: 0 PCI: 00:04.1 20 <- [0x0000001420 - 0x000000142f] size 0x00000010 gran 0x04 io PCI: 00:04.2 20 <- [0x0000001400 - 0x000000141f] size 0x00000020 gran 0x05 io PCI: 00:09.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 00:09.0 14 <- [0x00f0834000 - 0x00f08340ff] size 0x00000100 gran 0x08 mem PCI: 00:09.0 30 <- [0x00f0800000 - 0x00f081ffff] size 0x00020000 gran 0x11 romem PCI: 00:0c.0 10 <- [0x00f0830000 - 0x00f0833fff] size 0x00004000 gran 0x0e mem PCI: 00:0c.0 14 <- [0x00f0000000 - 0x00f07fffff] size 0x00800000 gran 0x17 prefmem PCI: 00:0c.0 30 <- [0x00f0820000 - 0x00f082ffff] size 0x00010000 gran 0x10 romem PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0 PCI_DOMAIN: 0000 resource base 1000 size 430 align 8 gran 0 limit e3ff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base e0000000 size 10834100 align 28 gran 0 limit ff7fffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a PCI_DOMAIN: 0000 resource base c0000 size 1ff40000 align 0 gran 0 limit 0 flags e0004200 index b PCI: 00:00.0 PCI: 00:00.0 resource base e0000000 size 10000000 align 28 gran 28 limit ff7fffff flags 60001200 index 10 PCI: 00:01.0 PCI: 00:01.0 resource base e3ff size 0 align 12 gran 12 limit e3ff flags 60080102 index 1c PCI: 00:01.0 resource base ff7fffff size 0 align 20 gran 20 limit ff7fffff flags 60081202 index 24 PCI: 00:01.0 resource base ff7fffff size 0 align 20 gran 20 limit ff7fffff flags 60080202 index 20 PCI: 00:04.0 child on link 0 PNP: 03f0.0 PCI: 00:04.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:04.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags d0000200 index 2 PNP: 03f0.0 PNP: 03f0.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 03f0.0 resource base 6 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 03f0.0 resource base 2 size 1 align 0 gran 0 limit 0 flags e0000800 index 74 PNP: 03f0.1 PNP: 03f0.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 03f0.1 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 03f0.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 03f0.2 PNP: 03f0.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 03f0.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 03f0.3 PNP: 03f0.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 03f0.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 03f0.5 PNP: 03f0.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60 PNP: 03f0.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62 PNP: 03f0.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 03f0.5 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 72 PNP: 03f0.7 PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 PNP: 03f0.7 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 62 PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 03f0.8 PNP: 03f0.9 PNP: 03f0.a PNP: 03f0.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 03f0.6 PNP: 03f0.6 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 PNP: 03f0.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PCI: 00:04.1 PCI: 00:04.1 resource base 1420 size 10 align 4 gran 4 limit e3ff flags 60000100 index 20 PCI: 00:04.2 PCI: 00:04.2 resource base 1400 size 20 align 5 gran 5 limit e3ff flags 60000100 index 20 PCI: 00:04.3 PCI: 00:04.3 resource base e400 size 40 align 0 gran 0 limit ffff flags d0000100 index 1 PCI: 00:04.3 resource base f00 size 10 align 0 gran 0 limit ffff flags d0000100 index 2 PCI: 00:09.0 PCI: 00:09.0 resource base 1000 size 100 align 8 gran 8 limit e3ff flags 60000100 index 10 PCI: 00:09.0 resource base f0834000 size 100 align 8 gran 8 limit ff7fffff flags 60000200 index 14 PCI: 00:09.0 resource base f0800000 size 20000 align 17 gran 17 limit ff7fffff flags 60002200 index 30 PCI: 00:0c.0 PCI: 00:0c.0 resource base f0830000 size 4000 align 14 gran 14 limit ff7fffff flags 60000200 index 10 PCI: 00:0c.0 resource base f0000000 size 800000 align 23 gran 23 limit ff7fffff flags 60001200 index 14 PCI: 00:0c.0 resource base f0820000 size 10000 align 16 gran 16 limit ff7fffff flags 60002200 index 30 Done allocating resources. Enabling resources... PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 bridge ctrl <- 0083 PCI: 00:01.0 cmd <- 00 PCI: 00:04.0 cmd <- 07 PCI: 00:04.1 cmd <- 01 PCI: 00:04.2 cmd <- 01 PCI: 00:04.3 cmd <- 01 PCI: 00:09.0 cmd <- 03 PCI: 00:0c.0 cmd <- 83 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init Initializing CPU #0 CPU: vendor Intel device 672 CPU: family 06, model 07, stepping 02 microcode_info: sig = 0x00000672 pf=0x00000001 rev = 0x00000000 microcode updated to revision: 00000010 from revision 00000000 Enabling cache
Setting fixed MTRRs(0-88) Type: UC Setting fixed MTRRs(0-16) Type: WB Setting fixed MTRRs(24-88) Type: WB DONE fixed MTRRs call enable_fixed_mtrr() Setting variable MTRR 0, base: 0MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xf Zero-sized MTRR range @0KB DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs
MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled
Disabling local apic...done. CPU #0 initialized PCI: 00:00.0 init Northbridge Init PCI: 00:04.0 init RTC Init PCI: 00:04.1 init IDE: Primary IDE interface: on IDE: Secondary IDE interface: on IDE: Access to legacy IDE ports: on IDE: Primary IDE interface, drive 0: UDMA/33: off IDE: Primary IDE interface, drive 1: UDMA/33: off IDE: Secondary IDE interface, drive 0: UDMA/33: off IDE: Secondary IDE interface, drive 1: UDMA/33: off PCI: 00:04.2 init PCI: 00:09.0 init PCI: 00:0c.0 init PNP: 03f0.0 init PNP: 03f0.1 init PNP: 03f0.2 init PNP: 03f0.3 init PNP: 03f0.5 init Keyboard init... Keyboard selftest failed ACK: 0xaa PNP: 03f0.7 init PNP: 03f0.a init PNP: 03f0.6 init Devices initialized Show all devs...After init. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:04.0: enabled 1 PNP: 03f0.0: enabled 1 PNP: 03f0.1: enabled 1 PNP: 03f0.2: enabled 1 PNP: 03f0.3: enabled 1 PNP: 03f0.5: enabled 1 PNP: 03f0.7: enabled 1 PNP: 03f0.8: enabled 1 PNP: 03f0.9: enabled 1 PNP: 03f0.a: enabled 1 PCI: 00:04.1: enabled 1 PCI: 00:04.2: enabled 1 PCI: 00:04.3: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:0c.0: enabled 1 PNP: 03f0.6: enabled 1 CPU: 00: enabled 1 Initializing CBMEM area to 0x1feefc00 (1115136 bytes) Adding CBMEM entry as no. 1 Moving GDT to 1feefe00...ok High Tables Base is 1feefc00. Copying Interrupt Routing Table to 0x000f0000... done. Adding CBMEM entry as no. 2 Copying Interrupt Routing Table to 0x1fef0000... done. PIRQ table: 128 bytes. Adding CBMEM entry as no. 3 ACPI: Writing ACPI tables at 1fef1000... ACPI: Writing cbmem_toc pointer at 1fef1024... ACPI: * FACS ACPI: * DSDT @ 1fef1140 Length 683 ACPI: * FADT ACPI: added table 1/32, length now 40 ACPI: * MADT ACPI: * SSDT Found 1 CPU(s). ACPI: added table 2/32, length now 44 ACPI: done. ACPI tables: 2354 bytes. Adding CBMEM entry as no. 4 Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500 - 00000518 checksum 13ef New low_table_end: 0x00000518 Now going to write high coreboot table at 0x1fefcc00 rom_table_end = 0x1fefcc00 Adjust low_table_end from 0x00000518 to 0x00001000 Adjust rom_table_end from 0x1fefcc00 to 0x1ff00000 Adding high table area coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-000000001feefbff: RAM 3. 000000001feefc00-000000001fffffff: CONFIGURATION TABLES 4. 00000000ff800000-00000000ffffffff: RESERVED Wrote coreboot table at: 1fefcc00 - 1fefcdbc checksum ad8c coreboot table: 444 bytes. Adding CBMEM entry as no. 5 Multiboot Information structure has been written. 0. FREE SPACE 1fffec00 00001400 1. GDT 1feefe00 00000200 2. IRQ TABLE 1fef0000 00001000 3. ACPI 1fef1000 0000bc00 4. COREBOOT 1fefcc00 00002000 5. ACPI RESUME1fefec00 00100000 Check CBFS header at fffffc9e magic is 4f524243 Found CBFS header at fffffc9e Check fallback/romstage CBFS: follow chain: fffc0000 + 38 + 3699 + align -> fffc3700 Check fallback/coreboot_ram CBFS: follow chain: fffc3700 + 38 + 148bf + align -> fffd8000 Check fallback/payload Got a payload Loading segment from rom address 0xfffd8038 data (compression=1) New segment dstaddr 0xe9368 memsize 0x16c98 srcaddr 0xfffd8070 filesize 0xb69e (cleaned up) New segment addr 0xe9368 size 0x16c98 offset 0xfffd8070 filesize 0xb69e Loading segment from rom address 0xfffd8054 Entry Point 0x000fc9ef Loading Segment: addr: 0x00000000000e9368 memsz: 0x0000000000016c98 filesz: 0x000000000000b69e lb: [0x0000000000100000, 0x0000000000134000) Post relocation: addr: 0x00000000000e9368 memsz: 0x0000000000016c98 filesz: 0x000000000000b69e using LZMA [ 0x000e9368, 00100000, 0x00100000) <- fffd8070 dest 000e9368, end 00100000, bouncebuffer 1fe87c00 Loaded segments Jumping to boot code at fc9ef entry = 0x000fc9ef lb_start = 0x00100000 lb_size = 0x00034000 adjust = 0x1fdbbc00 buffer = 0x1fe87c00 elf_boot_notes = 0x00124aa0 adjusted_boot_notes = 0x1fee06a0 Start bios (version pre-0.6.2-20101129_001420-nukunuku) Found mainboard ASUS P2B Found CBFS header at 0xfffffc9e Ram Size=0x1feefc00 (0x0000000000000000 high) Relocating init from 0x000e9800 to 0x1fed6500 (size 38360) CPU Mhz=501 No apic - only the main cpu is present. Copying PIR from 0x1fef0000 to 0x000fdc70 Copying ACPI RSDP from 0x1fef1000 to 0x000fdc50 SMBIOS ptr=0x000fdc30 table=0x1feefaf0 Scan for VGA option rom Running option rom at c000:0003 Turning on vga text mode console SeaBIOS (version pre-0.6.2-20101129_001420-nukunuku)
UHCI init on dev 00:04.2 (io=1400) Found 1 lpt ports Found 2 serial ports ATA controller 0 at 1f0/3f4/0 (irq 14 dev 21) ATA controller 1 at 170/374/0 (irq 15 dev 21) ata0-0: WDC WD1200JB-00DUA0 ATA-6 Hard-Disk (111 GiBytes) drive 0x000fdbe0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=234441648 ebda moved from 9fc00 to 9f800 USB mouse initialized Got ps2 nak (status=51) All threads complete. Scan for option roms Press F12 for boot menu.
Returned 57344 bytes of ZoneHigh e820 map has 6 items: 0: 0000000000000000 - 000000000009f800 = 1 1: 000000000009f800 - 00000000000a0000 = 2 2: 00000000000f0000 - 0000000000100000 = 2 3: 0000000000100000 - 000000001feedc00 = 1 4: 000000001feedc00 - 0000000020000000 = 2 5: 00000000ff800000 - 0000000100000000 = 2 enter handle_19: NULL Booting from Floppy... Boot failed: could not read the boot disk
enter handle_18: NULL Booting from DVD/CD... Boot failed: Could not read from CDROM (code 0001) enter handle_18: NULL Booting from Hard Disk... Booting from 0000:7c00
coreboot-4.0-r6132M-asus-p2b-trunk Mon Dec 13 15:53:34 CET 2010 starting... Wakeup from ACPI sleep type S5 (PMCNTRL=0000) v_esp=000cffc8 testx = 5a5a5a5a resume_backup_memory=00000000 Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a After cache as ram disabled resume_backup_memory=00000000 Clearing initial memory region: Done Loading image. Check CBFS header at fffffc9e magic is 4f524243 Found CBFS header at fffffc9e Check fallback/romstage CBFS: follow chain: fffc0000 + 38 + 3525 + align -> fffc3580 Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (212992 bytes), entry @ 0x100000 Stage: done loading. Jumping to image. POST: 0x80 POST: 0x39 coreboot-4.0-r6132M-asus-p2b-trunk Mon Dec 13 15:53:34 CET 2010 booting... POST: 0x40 clocks_per_usec: 452 Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:04.0: enabled 1 PNP: 03f0.0: enabled 1 PNP: 03f0.1: enabled 1 PNP: 03f0.2: enabled 1 PNP: 03f0.3: enabled 1 PNP: 03f0.5: enabled 1 PNP: 03f0.7: enabled 1 PNP: 03f0.8: enabled 1 PNP: 03f0.9: enabled 1 PNP: 03f0.a: enabled 1 PCI: 00:04.1: enabled 1 PCI: 00:04.2: enabled 1 PCI: 00:04.3: enabled 1 Compare with tree... Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:04.0: enabled 1 PNP: 03f0.0: enabled 1 PNP: 03f0.1: enabled 1 PNP: 03f0.2: enabled 1 PNP: 03f0.3: enabled 1 PNP: 03f0.5: enabled 1 PNP: 03f0.7: enabled 1 PNP: 03f0.8: enabled 1 PNP: 03f0.9: enabled 1 PNP: 03f0.a: enabled 1 PCI: 00:04.1: enabled 1 PCI: 00:04.2: enabled 1 PCI: 00:04.3: enabled 1 scan_static_bus for Root Device APIC_CLUSTER: 0 enabled Finding PCI configuration type. PCI: Using configuration type 1 POST: 0x5f PCI_DOMAIN: 0000 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 POST: 0x24 PCI: 00:00.0 [8086/7190] ops PCI: 00:00.0 [8086/7190] enabled PCI: 00:01.0 [8086/7191] enabled PCI: 00:04.0 [8086/7110] bus ops PCI: 00:04.0 [8086/7110] enabled PCI: 00:04.1 [8086/7111] ops PCI: 00:04.1 [8086/7111] enabled PCI: 00:04.2 [8086/7112] ops PCI: 00:04.2 [8086/7112] enabled PCI: 00:04.3 [8086/7113] bus ops Wakeup from ACPI sleep type S5 (PMCNTRL=0000) PCI: 00:04.3 [8086/7113] enabled malloc Enter, size 68, free_mem_ptr 00130000 malloc 00130000 PCI: 00:0a.0 [1045/c861] enabled malloc Enter, size 68, free_mem_ptr 00130044 malloc 00130044 PCI: 00:0b.0 [5333/88f0] enabled malloc Enter, size 68, free_mem_ptr 00130088 malloc 00130088 PCI: 00:0c.0 [1106/3249] enabled POST: 0x25 do_pci_scan_bridge for PCI: 00:01.0 malloc Enter, size 24, free_mem_ptr 001300cc malloc 001300cc PCI: pci_scan_bus for bus 01 POST: 0x24 POST: 0x25 PCI: pci_scan_bus returning with max=001 POST: 0x55 do_pci_scan_bridge returns max 1 scan_static_bus for PCI: 00:04.0 malloc Enter, size 2560, free_mem_ptr 001300e4 malloc 001300e4 malloc Enter, size 68, free_mem_ptr 00130ae4 malloc 00130ae4 PNP: 03f0.0 enabled PNP: 03f0.1 enabled PNP: 03f0.2 enabled PNP: 03f0.3 enabled PNP: 03f0.5 enabled PNP: 03f0.7 enabled PNP: 03f0.8 enabled PNP: 03f0.9 enabled PNP: 03f0.a enabled PNP: 03f0.6 enabled scan_static_bus for PCI: 00:04.0 done scan_static_bus for PCI: 00:04.3 scan_static_bus for PCI: 00:04.3 done PCI: pci_scan_bus returning with max=001 POST: 0x55 scan_static_bus for Root Device done done POST: 0x66 Setting up VGA for PCI: 00:0b.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:04.0 read_resources bus 0 link: 0 PNP: 03f0.8 missing read_resources PNP: 03f0.9 missing read_resources PCI: 00:04.0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 10 PCI: 00:01.0 PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24 PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:04.0 child on link 0 PNP: 03f0.0 PCI: 00:04.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:04.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags d0000200 index 2 PNP: 03f0.0 PNP: 03f0.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 03f0.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 03f0.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 03f0.1 PNP: 03f0.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 03f0.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 03f0.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 03f0.2 PNP: 03f0.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 03f0.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 03f0.3 PNP: 03f0.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 03f0.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 03f0.5 PNP: 03f0.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60 PNP: 03f0.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62 PNP: 03f0.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 03f0.5 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 72 PNP: 03f0.7 PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 PNP: 03f0.7 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 62 PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 03f0.8 PNP: 03f0.9 PNP: 03f0.a PNP: 03f0.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 03f0.6 PNP: 03f0.6 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 PNP: 03f0.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PCI: 00:04.1 PCI: 00:04.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:04.2 PCI: 00:04.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:04.3 PCI: 00:04.3 resource base e400 size 40 align 0 gran 0 limit ffff flags d0000100 index 1 PCI: 00:04.3 resource base f00 size 10 align 0 gran 0 limit ffff flags d0000100 index 2 PCI: 00:0a.0 PCI: 00:0a.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:0b.0 PCI: 00:0b.0 resource base 0 size 2000000 align 25 gran 25 limit ffffffff flags 200 index 10 PCI: 00:0b.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI: 00:0c.0 PCI: 00:0c.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 10 PCI: 00:0c.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 14 PCI: 00:0c.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 18 PCI: 00:0c.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 1c PCI: 00:0c.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:0c.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 24 PCI: 00:0c.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:0c.0 24 * [0x0 - 0xff] io PCI: 00:04.2 20 * [0x400 - 0x41f] io PCI: 00:0c.0 20 * [0x420 - 0x43f] io PCI: 00:04.1 20 * [0x440 - 0x44f] io PCI: 00:0c.0 10 * [0x450 - 0x45f] io PCI: 00:0c.0 14 * [0x460 - 0x46f] io PCI: 00:0c.0 18 * [0x470 - 0x47f] io PCI: 00:0c.0 1c * [0x480 - 0x48f] io PCI_DOMAIN: 0000 compute_resources_io: base: 490 size: 490 align: 8 gran: 0 limit: ffff done PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:00.0 10 * [0x0 - 0xfffffff] prefmem PCI: 00:0b.0 10 * [0x10000000 - 0x11ffffff] mem PCI: 00:0b.0 30 * [0x12000000 - 0x1200ffff] mem PCI: 00:0c.0 30 * [0x12010000 - 0x1201ffff] mem PCI: 00:0a.0 10 * [0x12020000 - 0x12020fff] mem PCI_DOMAIN: 0000 compute_resources_mem: base: 12021000 size: 12021000 align: 28 gran: 0 limit: ffffffff done avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:01.0 constrain_resources: PCI: 00:04.0 constrain_resources: PNP: 03f0.0 constrain_resources: PNP: 03f0.1 constrain_resources: PNP: 03f0.2 constrain_resources: PNP: 03f0.3 constrain_resources: PNP: 03f0.5 constrain_resources: PNP: 03f0.7 constrain_resources: PNP: 03f0.8 constrain_resources: PNP: 03f0.9 constrain_resources: PNP: 03f0.a constrain_resources: PNP: 03f0.6 constrain_resources: PCI: 00:04.1 constrain_resources: PCI: 00:04.2 constrain_resources: PCI: 00:04.3 constrain_resources: PCI: 00:0a.0 constrain_resources: PCI: 00:0b.0 constrain_resources: PCI: 00:0c.0 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff lim->base 00001000 lim->limit 0000e3ff avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff lim->base 00000000 lim->limit ff7fffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:490 align:8 gran:0 limit:e3ff Assigned: PCI: 00:0c.0 24 * [0x1000 - 0x10ff] io Assigned: PCI: 00:04.2 20 * [0x1400 - 0x141f] io Assigned: PCI: 00:0c.0 20 * [0x1420 - 0x143f] io Assigned: PCI: 00:04.1 20 * [0x1440 - 0x144f] io Assigned: PCI: 00:0c.0 10 * [0x1450 - 0x145f] io Assigned: PCI: 00:0c.0 14 * [0x1460 - 0x146f] io Assigned: PCI: 00:0c.0 18 * [0x1470 - 0x147f] io Assigned: PCI: 00:0c.0 1c * [0x1480 - 0x148f] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 1490 size: 490 align: 8 gran: 0 done PCI: 00:01.0 allocate_resources_io: base:e3ff size:0 align:12 gran:12 limit:e3ff PCI: 00:01.0 allocate_resources_io: next_base: e3ff size: 0 align: 12 gran: 12 done PCI_DOMAIN: 0000 allocate_resources_mem: base:e0000000 size:12021000 align:28 gran:0 limit:ff7fffff Assigned: PCI: 00:00.0 10 * [0xe0000000 - 0xefffffff] prefmem Assigned: PCI: 00:0b.0 10 * [0xf0000000 - 0xf1ffffff] mem Assigned: PCI: 00:0b.0 30 * [0xf2000000 - 0xf200ffff] mem Assigned: PCI: 00:0c.0 30 * [0xf2010000 - 0xf201ffff] mem Assigned: PCI: 00:0a.0 10 * [0xf2020000 - 0xf2020fff] mem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: f2021000 size: 12021000 align: 28 gran: 0 done PCI: 00:01.0 allocate_resources_prefmem: base:ff7fffff size:0 align:20 gran:20 limit:ff7fffff PCI: 00:01.0 allocate_resources_prefmem: next_base: ff7fffff size: 0 align: 20 gran: 20 done PCI: 00:01.0 allocate_resources_mem: base:ff7fffff size:0 align:20 gran:20 limit:ff7fffff PCI: 00:01.0 allocate_resources_mem: next_base: ff7fffff size: 0 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 Setting RAM size to 256 MB PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:00.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem PCI: 00:01.0 1c <- [0x000000e3ff - 0x000000e3fe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:01.0 24 <- [0x00ff7fffff - 0x00ff7ffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:01.0 20 <- [0x00ff7fffff - 0x00ff7ffffe] size 0x00000000 gran 0x14 bus 01 mem PCI: 00:04.0 assign_resources, bus 0 link: 0 PNP: 03f0.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 io PNP: 03f0.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00 irq PNP: 03f0.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00 drq PNP: 03f0.1 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io PNP: 03f0.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq ERROR: PNP: 03f0.1 74 drq size: 0x0000000001 not assigned PNP: 03f0.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 03f0.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 03f0.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io PNP: 03f0.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq PNP: 03f0.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io PNP: 03f0.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io PNP: 03f0.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq PNP: 03f0.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq ERROR: PNP: 03f0.7 60 io size: 0x0000000001 not assigned ERROR: PNP: 03f0.7 62 io size: 0x0000000002 not assigned ERROR: PNP: 03f0.7 70 irq size: 0x0000000001 not assigned ERROR: PNP: 03f0.a 70 irq size: 0x0000000001 not assigned ERROR: PNP: 03f0.6 60 io size: 0x0000000008 not assigned ERROR: PNP: 03f0.6 70 irq size: 0x0000000001 not assigned PCI: 00:04.0 assign_resources, bus 0 link: 0 PCI: 00:04.1 20 <- [0x0000001440 - 0x000000144f] size 0x00000010 gran 0x04 io PCI: 00:04.2 20 <- [0x0000001400 - 0x000000141f] size 0x00000020 gran 0x05 io PCI: 00:0a.0 10 <- [0x00f2020000 - 0x00f2020fff] size 0x00001000 gran 0x0c mem PCI: 00:0b.0 10 <- [0x00f0000000 - 0x00f1ffffff] size 0x02000000 gran 0x19 mem PCI: 00:0b.0 30 <- [0x00f2000000 - 0x00f200ffff] size 0x00010000 gran 0x10 romem PCI: 00:0c.0 10 <- [0x0000001450 - 0x000000145f] size 0x00000010 gran 0x04 io PCI: 00:0c.0 14 <- [0x0000001460 - 0x000000146f] size 0x00000010 gran 0x04 io PCI: 00:0c.0 18 <- [0x0000001470 - 0x000000147f] size 0x00000010 gran 0x04 io PCI: 00:0c.0 1c <- [0x0000001480 - 0x000000148f] size 0x00000010 gran 0x04 io PCI: 00:0c.0 20 <- [0x0000001420 - 0x000000143f] size 0x00000020 gran 0x05 io PCI: 00:0c.0 24 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 00:0c.0 30 <- [0x00f2010000 - 0x00f201ffff] size 0x00010000 gran 0x10 romem PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0 PCI_DOMAIN: 0000 resource base 1000 size 490 align 8 gran 0 limit e3ff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base e0000000 size 12021000 align 28 gran 0 limit ff7fffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a PCI_DOMAIN: 0000 resource base c0000 size ff40000 align 0 gran 0 limit 0 flags e0004200 index b PCI: 00:00.0 PCI: 00:00.0 resource base e0000000 size 10000000 align 28 gran 28 limit ff7fffff flags 60001200 index 10 PCI: 00:01.0 PCI: 00:01.0 resource base e3ff size 0 align 12 gran 12 limit e3ff flags 60080102 index 1c PCI: 00:01.0 resource base ff7fffff size 0 align 20 gran 20 limit ff7fffff flags 60081202 index 24 PCI: 00:01.0 resource base ff7fffff size 0 align 20 gran 20 limit ff7fffff flags 60080202 index 20 PCI: 00:04.0 child on link 0 PNP: 03f0.0 PCI: 00:04.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:04.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags d0000200 index 2 PNP: 03f0.0 PNP: 03f0.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 03f0.0 resource base 6 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 03f0.0 resource base 2 size 1 align 0 gran 0 limit 0 flags e0000800 index 74 PNP: 03f0.1 PNP: 03f0.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 03f0.1 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 03f0.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 03f0.2 PNP: 03f0.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 03f0.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 03f0.3 PNP: 03f0.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 03f0.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 03f0.5 PNP: 03f0.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60 PNP: 03f0.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62 PNP: 03f0.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 03f0.5 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 72 PNP: 03f0.7 PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 PNP: 03f0.7 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 62 PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 03f0.8 PNP: 03f0.9 PNP: 03f0.a PNP: 03f0.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 03f0.6 PNP: 03f0.6 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 PNP: 03f0.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PCI: 00:04.1 PCI: 00:04.1 resource base 1440 size 10 align 4 gran 4 limit e3ff flags 60000100 index 20 PCI: 00:04.2 PCI: 00:04.2 resource base 1400 size 20 align 5 gran 5 limit e3ff flags 60000100 index 20 PCI: 00:04.3 PCI: 00:04.3 resource base e400 size 40 align 0 gran 0 limit ffff flags d0000100 index 1 PCI: 00:04.3 resource base f00 size 10 align 0 gran 0 limit ffff flags d0000100 index 2 PCI: 00:0a.0 PCI: 00:0a.0 resource base f2020000 size 1000 align 12 gran 12 limit ff7fffff flags 60000200 index 10 PCI: 00:0b.0 PCI: 00:0b.0 resource base f0000000 size 2000000 align 25 gran 25 limit ff7fffff flags 60000200 index 10 PCI: 00:0b.0 resource base f2000000 size 10000 align 16 gran 16 limit ff7fffff flags 60002200 index 30 PCI: 00:0c.0 PCI: 00:0c.0 resource base 1450 size 10 align 4 gran 4 limit e3ff flags 60000100 index 10 PCI: 00:0c.0 resource base 1460 size 10 align 4 gran 4 limit e3ff flags 60000100 index 14 PCI: 00:0c.0 resource base 1470 size 10 align 4 gran 4 limit e3ff flags 60000100 index 18 PCI: 00:0c.0 resource base 1480 size 10 align 4 gran 4 limit e3ff flags 60000100 index 1c PCI: 00:0c.0 resource base 1420 size 20 align 5 gran 5 limit e3ff flags 60000100 index 20 PCI: 00:0c.0 resource base 1000 size 100 align 8 gran 8 limit e3ff flags 60000100 index 24 PCI: 00:0c.0 resource base f2010000 size 10000 align 16 gran 16 limit ff7fffff flags 60002200 index 30 Done allocating resources. POST: 0x88 Enabling resources... PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 bridge ctrl <- 0083 PCI: 00:01.0 cmd <- 00 PCI: 00:04.0 cmd <- 07 PCI: 00:04.1 cmd <- 01 PCI: 00:04.2 cmd <- 01 PCI: 00:04.3 cmd <- 01 PCI: 00:0a.0 cmd <- 02 PCI: 00:0b.0 cmd <- 83 PCI: 00:0c.0 cmd <- 03 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init malloc Enter, size 68, free_mem_ptr 00130b28 malloc 00130b28 Initializing CPU #0 CPU: vendor Intel device 673 CPU: family 06, model 07, stepping 03 microcode_info: sig = 0x00000673 pf=0x00000001 rev = 0x00000000 microcode updated to revision: 0000000e from revision 00000000 POST: 0x60 Enabling cache
Setting fixed MTRRs(0-88) Type: UC Setting fixed MTRRs(0-16) Type: WB Setting fixed MTRRs(24-88) Type: WB DONE fixed MTRRs call enable_fixed_mtrr() Setting variable MTRR 0, base: 0MB, range: 256MB, type WB ADDRESS_MASK_HIGH=0xf Zero-sized MTRR range @0KB DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a
MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled
POST: 0x93 Disabling local apic...done. POST: 0x9b CPU #0 initialized PCI: 00:00.0 init Northbridge Init PCI: 00:04.0 init RTC Init PCI: 00:04.1 init IDE: Primary IDE interface: on IDE: Secondary IDE interface: on IDE: Access to legacy IDE ports: on IDE: Primary IDE interface, drive 0: UDMA/33: off IDE: Primary IDE interface, drive 1: UDMA/33: off IDE: Secondary IDE interface, drive 0: UDMA/33: off IDE: Secondary IDE interface, drive 1: UDMA/33: off PCI: 00:04.2 init PCI: 00:0a.0 init PCI: 00:0b.0 init PCI: 00:0c.0 init PNP: 03f0.0 init PNP: 03f0.1 init PNP: 03f0.2 init PNP: 03f0.3 init PNP: 03f0.5 init PNP: 03f0.7 init PNP: 03f0.a init PNP: 03f0.6 init Devices initialized Show all devs...After init. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:04.0: enabled 1 PNP: 03f0.0: enabled 1 PNP: 03f0.1: enabled 1 PNP: 03f0.2: enabled 1 PNP: 03f0.3: enabled 1 PNP: 03f0.5: enabled 1 PNP: 03f0.7: enabled 1 PNP: 03f0.8: enabled 1 PNP: 03f0.9: enabled 1 PNP: 03f0.a: enabled 1 PCI: 00:04.1: enabled 1 PCI: 00:04.2: enabled 1 PCI: 00:04.3: enabled 1 PCI: 00:0a.0: enabled 1 PCI: 00:0b.0: enabled 1 PCI: 00:0c.0: enabled 1 PNP: 03f0.6: enabled 1 CPU: 00: enabled 1 POST: 0x89 Initializing CBMEM area to 0xfeefc00 (1115136 bytes) Adding CBMEM entry as no. 1 Moving GDT to 0feefe00...ok POST: 0x8a High Tables Base is feefc00. POST: 0x9a Copying Interrupt Routing Table to 0x000f0000... done. Verifying copy of Interrupt Routing Table at 0x000f0000... done Checking Interrupt Routing Table consistency... check_pirq_routing_table(): Interrupt Routing Table located at 000f0000. done. Adding CBMEM entry as no. 2 Copying Interrupt Routing Table to 0x0fef0000... done. Verifying copy of Interrupt Routing Table at 0x0fef0000... done Checking Interrupt Routing Table consistency... check_pirq_routing_table(): Interrupt Routing Table located at 0fef0000. done. PIRQ table: 128 bytes. POST: 0x9c Adding CBMEM entry as no. 3 ACPI: Writing ACPI tables at fef1000... ACPI: Writing cbmem_toc pointer at fef1024... ACPI: * FACS ACPI: * DSDT @ 0fef1140 Length 69c ACPI: * FADT ACPI: added table 1/32, length now 40 ACPI: * MADT ACPI: * SSDT ACPI: added table 2/32, length now 44 ACPI: done. ACPI tables: 2351 bytes. POST: 0x9d Adding CBMEM entry as no. 4 Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500 - 00000518 checksum 23ef New low_table_end: 0x00000518 Now going to write high coreboot table at 0x0fefcc00 rom_table_end = 0x0fefcc00 Adjust low_table_end from 0x00000518 to 0x00001000 Adjust rom_table_end from 0x0fefcc00 to 0x0ff00000 Adding high table area coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-000000000feefbff: RAM 3. 000000000feefc00-000000000fffffff: CONFIGURATION TABLES 4. 00000000ff800000-00000000ffffffff: RESERVED Wrote coreboot table at: 0fefcc00 - 0fefcdac checksum c7f1 coreboot table: 428 bytes. POST: 0x9e Adding CBMEM entry as no. 5 POST: 0x9d Multiboot Information structure has been written. 0. FREE SPACE 0fffec00 00001400 1. GDT 0feefe00 00000200 2. IRQ TABLE 0fef0000 00001000 3. ACPI 0fef1000 0000bc00 4. COREBOOT 0fefcc00 00002000 5. ACPI RESUME0fefec00 00100000 Check CBFS header at fffffc9e magic is 4f524243 Found CBFS header at fffffc9e Check fallback/romstage CBFS: follow chain: fffc0000 + 38 + 3525 + align -> fffc3580 Check fallback/coreboot_ram CBFS: follow chain: fffc3580 + 38 + 14712 + align -> fffd7d00 Check fallback/payload Got a payload Loading segment from rom address 0xfffd7d38 data (compression=1) malloc Enter, size 36, free_mem_ptr 00130b6c malloc 00130b6c New segment dstaddr 0xe75e0 memsize 0x18a20 srcaddr 0xfffd7d70 filesize 0xc30d (cleaned up) New segment addr 0xe75e0 size 0x18a20 offset 0xfffd7d70 filesize 0xc30d Loading segment from rom address 0xfffd7d54 Entry Point 0x000fc09f Loading Segment: addr: 0x00000000000e75e0 memsz: 0x0000000000018a20 filesz: 0x000000000000c30d lb: [0x0000000000100000, 0x0000000000134000) Post relocation: addr: 0x00000000000e75e0 memsz: 0x0000000000018a20 filesz: 0x000000000000c30d using LZMA [ 0x000e75e0, 00100000, 0x00100000) <- fffd7d70 dest 000e75e0, end 00100000, bouncebuffer fe87c00 Loaded segments Jumping to boot code at fc09f POST: 0xfe entry = 0x000fc09f lb_start = 0x00100000 lb_size = 0x00034000 adjust = 0x0fdbbc00 buffer = 0x0fe87c00 elf_boot_notes = 0x001244b4 adjusted_boot_notes = 0x0fee00b4 Start bios (version 0.6.1-20101114_145528-myhost) init ivt init bda Find memory size Attempting to find coreboot table Found coreboot table forwarder. Now attempting to find coreboot memory map Add to e820 map: 00000000 00001000 2 Add to e820 map: 00001000 0009f000 1 Add to e820 map: 000c0000 0fe2fc00 1 Add to e820 map: 0feefc00 00110400 2 Add to e820 map: ff800000 00800000 2 Add to e820 map: 00000000 00004000 1 Found mainboard ASUS P2B Found CBFS header at 0xfffffc9e Add to e820 map: 000a0000 00050000 -1 Add to e820 map: 0009fc00 00000400 2 Add to e820 map: 000f0000 00010000 2 Ram Size=0x0feefc00 (0x0000000000000000 high) malloc setup Add to e820 map: 0fedfc00 00010000 2 init pic init timer tsc calibrate start=2376249850 end=2377024517 diff=774667 CPU Mhz=451 math cp init init boot device ordering init usb pmm_malloc zone=0x000f5384 handle=ffffffff size=32 align=10 ret=0x0fedfac0 (detail=0x0fedfae0) UHCI init on dev 00:04.2 (io=1400) pmm_malloc zone=0x000f5384 handle=ffffffff size=4096 align=1000 ret=0x0fede000 (detail=0x0fedfa90) /0fede000\ Start thread |0fede000| pmm_malloc zone=0x000f5378 handle=ffffffff size=16 align=10 ret=0x0feefbf0 (detail=0x0fedfa60) |0fede000| pmm_malloc zone=0x000f5378 handle=ffffffff size=4096 align=1000 ret=0x0feee000 (detail=0x0fedfa30) |0fede000| pmm_malloc zone=0x000f5378 handle=ffffffff size=8 align=10 ret=0x0feefbe0 (detail=0x0fedfa00) |0fede000| pmm_malloc zone=0x000f5378 handle=ffffffff size=8 align=10 ret=0x0feefbd0 (detail=0x0fedf9d0) |0fede000| pmm_malloc zone=0x000f5384 handle=ffffffff size=4096 align=1000 ret=0x0fedd000 (detail=0x0fedf9a0) /0fedd000\ Start thread |0fede000| pmm_malloc zone=0x000f5384 handle=ffffffff size=4096 align=1000 ret=0x0fedc000 (detail=0x0fedf970) /0fedc000\ Start thread |0fede000| pmm_free 0x0fedc000 (detail=0x0fedf970) \0fedc000/ End thread pmm_malloc zone=0x000f5384 handle=ffffffff size=20 align=10 ret=0x0fedf950 (detail=0x0fedf970) OHCI init on dev 00:0a.0 (regs=0xf2020000) pmm_malloc zone=0x000f5384 handle=ffffffff size=4096 align=1000 ret=0x0fedc000 (detail=0x0fedf920) /0fedc000\ Start thread |0fedc000| pmm_malloc zone=0x000f5378 handle=ffffffff size=256 align=100 ret=0x0feefa00 (detail=0x0fedf8f0) |0fedc000| pmm_malloc zone=0x000f5378 handle=ffffffff size=16 align=10 ret=0x0feefbc0 (detail=0x0fedf8c0) init ps2port pmm_malloc zone=0x000f5384 handle=ffffffff size=4096 align=1000 ret=0x0fedb000 (detail=0x0fedf890) /0fedb000\ Start thread |0fedb000| i8042_flush |0fedb000| i8042_command cmd=1aa |0fedb000| i8042_wait_write |0fedb000| i8042_wait_read |0fedb000| i8042 param=55 |0fedb000| i8042_command cmd=1ab |0fedb000| i8042_wait_write |0fedb000| i8042_wait_read |0fedb000| i8042 param=0 |0fedb000| ps2_command aux=0 cmd=2ff |0fedb000| i8042 ctr old=30 new=30 |0fedb000| i8042_command cmd=1060 |0fedb000| i8042_wait_write |0fedb000| i8042_wait_write init lpt Found 1 lpt ports init serial Found 2 serial ports init floppy drives init hard drives pmm_malloc zone=0x000f537c handle=ffffffff size=12 align=10 ret=0x000fd880 (detail=0x0fedf860) ATA controller 0 at 1f0/3f4/0 (irq 14 dev 21) pmm_malloc zone=0x000f5384 handle=ffffffff size=4096 align=1000 ret=0x0feda000 (detail=0x0fedf830) /0feda000\ Start thread |0feda000| powerup iobase=1f0 st=0 |0feda000| powerup iobase=1f0 st=0 |0feda000| ata_detect ata0-0: sc=4e sn=4e dh=a0 |0feda000| powerup iobase=1f0 st=4e |0feda000| powerup iobase=1f0 st=4e |0feda000| ata_detect ata0-1: sc=4e sn=4e dh=b0 pmm_free 0x0feda000 (detail=0x0fedf830) \0feda000/ End thread pmm_malloc zone=0x000f537c handle=ffffffff size=12 align=10 ret=0x000fd870 (detail=0x0fedf830) ATA controller 1 at 170/374/0 (irq 15 dev 21) pmm_malloc zone=0x000f5384 handle=ffffffff size=4096 align=1000 ret=0x0feda000 (detail=0x0fedf800) /0feda000\ Start thread |0feda000| powerup iobase=170 st=0 |0feda000| powerup iobase=170 st=0 |0feda000| ata_detect ata1-0: sc=4e sn=4e dh=a0 |0feda000| powerup iobase=170 st=4e |0feda000| powerup iobase=170 st=4e |0feda000| ata_detect ata1-1: sc=4e sn=4e dh=b0 pmm_free 0x0feda000 (detail=0x0fedf800) \0feda000/ End thread Searching CBFS for prefix floppyimg/ Found CBFS file fallback/romstage Found CBFS file fallback/coreboot_ram Found CBFS file fallback/payload Found CBFS file No apic - only the main cpu is present. init bios32 init PMM init PNPBIOS table init keyboard init mouse Relocating coreboot bios tables pmm_malloc zone=0x000f537c handle=ffffffff size=128 align=10 ret=0x000fd7f0 (detail=0x0fedf800) Copying PIR from 0x0fef0000 to 0x000fd7f0 pmm_malloc zone=0x000f537c handle=ffffffff size=20 align=10 ret=0x000fd7d0 (detail=0x0fedf7d0) Copying ACPI RSDP from 0x0fef1000 to 0x000fd7d0 init SMBIOS tables pmm_malloc zone=0x000f5384 handle=ffffffff size=32768 align=10 ret=0x0fed3000 (detail=0x0fedf7a0) pmm_malloc zone=0x000f537c handle=ffffffff size=31 align=10 ret=0x000fd7b0 (detail=0x0fedf770) pmm_malloc zone=0x000f5378 handle=ffffffff size=263 align=10 ret=0x0feef8f0 (detail=0x0fedf740) SMBIOS ptr=0x000fd7b0 table=0x0feef8f0 pmm_free 0x0fed3000 (detail=0x0fedf7a0) Scan for VGA option rom Attempting to init PCI bdf 00:0b.0 (vd 5333:88f0) Searching CBFS for prefix pci5333,88f0.rom Found CBFS file fallback/romstage Found CBFS file fallback/coreboot_ram Found CBFS file fallback/payload Found CBFS file Attempting to map option rom on dev 00:0b.0 Option rom sizing returned f2000000 ffff0000 Inspecting possible rom at 0xf2000000 (vd=5333:88f0 bdf=00:0b.0) Copying option rom (size 32768) from 0xf2000000 to c0000 |0fedd000| set_address 0x0fedfac0 |0fedd000| uhci_alloc_control_pipe 0x0fedfac0 |0fedd000| pmm_malloc zone=0x000f5384 handle=ffffffff size=28 align=10 ret=0x0fedf720 (detail=0x0fedf7a0) |0fedb000| i8042_command cmd=1060 |0fedb000| i8042_wait_write |0fedb000| i8042_wait_write |0fedb000| ps2_sendbyte aux=0 cmd=ff |0fedb000| i8042_kbd_write c=255 |0fedb000| i8042_wait_write |0fedd000| uhci_control 0x0fedf72c |0fedd000| pmm_malloc zone=0x000f5384 handle=ffffffff size=32 align=10 ret=0x0fedf6d0 (detail=0x0fedf6f0) |0fedc000| pmm_malloc zone=0x000f5384 handle=ffffffff size=4096 align=1000 ret=0x0feda000 (detail=0x0fedf6a0) /0feda000\ Start thread |0fedc000| pmm_free 0x0feda000 (detail=0x0fedf6a0) \0feda000/ End thread |0fedc000| pmm_malloc zone=0x000f5384 handle=ffffffff size=4096 align=1000 ret=0x0feda000 (detail=0x0fedf6a0) /0feda000\ Start thread |0fedc000| pmm_free 0x0feda000 (detail=0x0fedf6a0) \0feda000/ End thread |0fedc000| pmm_free 0x0feefa00 (detail=0x0fedf8f0) |0fedc000| pmm_free 0x0feefbc0 (detail=0x0fedf8c0) |0fedb000| pmm_free 0x0fedc000 (detail=0x0fedf920) \0fedc000/ End thread |0fedd000| pmm_free 0x0fedf6d0 (detail=0x0fedf6f0) |0fedd000| uhci_alloc_control_pipe 0x0fedfac0 |0fedd000| pmm_malloc zone=0x000f5384 handle=ffffffff size=28 align=10 ret=0x0fedf900 (detail=0x0fedf920) |0fedd000| config_usb: 0x0fedf90c |0fedd000| uhci_control 0x0fedf90c |0fedd000| pmm_malloc zone=0x000f5384 handle=ffffffff size=48 align=10 ret=0x0fedf6f0 (detail=0x0fedf8d0) |0fedb000| ps2 read fe |0fedb000| Got ps2 nak (status=51) |0fedb000| i8042_command cmd=1060 |0fedb000| i8042_wait_write |0fedb000| i8042_wait_write |0fedb000| ps2 command 2ff failed (aux=0) pmm_free 0x0fedb000 (detail=0x0fedf890) \0fedb000/ End thread |0fedd000| pmm_free 0x0fedf6f0 (detail=0x0fedf8d0) |0fedd000| device rev=0200 cls=00 sub=00 proto=00 size=40 |0fedd000| uhci_control 0x0fedf90c |0fedd000| pmm_malloc zone=0x000f5384 handle=ffffffff size=48 align=10 ret=0x0fedf8a0 (detail=0x0fedf8d0) |0fedd000| pmm_free 0x0fedf8a0 (detail=0x0fedf8d0) |0fedd000| pmm_malloc zone=0x000f5384 handle=ffffffff size=32 align=10 ret=0x0fedf8b0 (detail=0x0fedf8d0) |0fedd000| uhci_control 0x0fedf90c |0fedd000| pmm_malloc zone=0x000f5384 handle=ffffffff size=48 align=10 ret=0x0fedf6c0 (detail=0x0fedf6f0) Checking rom 0x000c0000 (sig aa55 size 64) Running option rom at c000:0003 |0fedd000| pmm_free 0x0fedf6c0 (detail=0x0fedf6f0) |0fedd000| pmm_free 0x0fedf8b0 (detail=0x0fedf8d0) |0fedd000| uhci_free_pipe 0x0fedf90c |0fedd000| pmm_free 0x0fedf900 (detail=0x0fedf920) |0fede000| pmm_free 0x0fedd000 (detail=0x0fedf9a0) \0fedd000/ End thread |0fede000| uhci_free_pipe 0x0fedf72c |0fede000| pmm_free 0x0fedf720 (detail=0x0fedf7a0) |0fede000| pmm_free 0x0feefbf0 (detail=0x0fedfa60) |0fede000| pmm_free 0x0feee000 (detail=0x0fedfa30) |0fede000| pmm_free 0x0feefbe0 (detail=0x0fedfa00) |0fede000| pmm_free 0x0feefbd0 (detail=0x0fedf9d0) |0fede000| pmm_free 0x0fedfac0 (detail=0x0fedfae0) pmm_free 0x0fede000 (detail=0x0fedfa90) \0fede000/ End thread All threads complete. Searching CBFS for prefix vgaroms/ Found CBFS file fallback/romstage Found CBFS file fallback/coreboot_ram Found CBFS file fallback/payload Found CBFS file Turning on vga text mode console SeaBIOS (version 0.6.1-20101114_145528-myhost)
Scan for option roms Attempting to init PCI bdf 00:00.0 (vd 8086:7190) Searching CBFS for prefix pci8086,7190.rom Found CBFS file fallback/romstage Found CBFS file fallback/coreboot_ram Found CBFS file fallback/payload Found CBFS file Attempting to map option rom on dev 00:00.0 Option rom sizing returned 0 0 Attempting to init PCI bdf 00:01.0 (vd 8086:7191) Searching CBFS for prefix pci8086,7191.rom Found CBFS file fallback/romstage Found CBFS file fallback/coreboot_ram Found CBFS file fallback/payload Found CBFS file Attempting to map option rom on dev 00:01.0 Skipping non-normal pci device (type=1) Attempting to init PCI bdf 00:04.0 (vd 8086:7110) Searching CBFS for prefix pci8086,7110.rom Found CBFS file fallback/romstage Found CBFS file fallback/coreboot_ram Found CBFS file fallback/payload Found CBFS file Attempting to map option rom on dev 00:04.0 Option rom sizing returned 0 0 Attempting to init PCI bdf 00:04.2 (vd 8086:7112) Searching CBFS for prefix pci8086,7112.rom Found CBFS file fallback/romstage Found CBFS file fallback/coreboot_ram Found CBFS file fallback/payload Found CBFS file Attempting to map option rom on dev 00:04.2 Option rom sizing returned 0 0 Attempting to init PCI bdf 00:04.3 (vd 8086:7113) Searching CBFS for prefix pci8086,7113.rom Found CBFS file fallback/romstage Found CBFS file fallback/coreboot_ram Found CBFS file fallback/payload Found CBFS file Attempting to map option rom on dev 00:04.3 Option rom sizing returned 0 0 Attempting to init PCI bdf 00:0a.0 (vd 1045:c861) Searching CBFS for prefix pci1045,c861.rom Found CBFS file fallback/romstage Found CBFS file fallback/coreboot_ram Found CBFS file fallback/payload Found CBFS file Attempting to map option rom on dev 00:0a.0 Option rom sizing returned 0 0 Attempting to init PCI bdf 00:0c.0 (vd 1106:3249) Searching CBFS for prefix pci1106,3249.rom Found CBFS file fallback/romstage Found CBFS file fallback/coreboot_ram Found CBFS file fallback/payload Found CBFS file Attempting to map option rom on dev 00:0c.0 Option rom sizing returned f2010000 ffff0000 Inspecting possible rom at 0xf2010000 (vd=1106:3249 bdf=00:0c.0) Copying option rom (size 59392) from 0xf2010000 to c8000 Checking rom 0x000c8000 (sig aa55 size 116) Running option rom at c800:0003 Searching CBFS for prefix genroms/ Found CBFS file fallback/romstage Found CBFS file fallback/coreboot_ram Found CBFS file fallback/payload Found CBFS file Checking rom 0x000c8000 (sig aa55 size 38) Press F12 for boot menu.
Checking for bootsplash Searching CBFS for prefix bootsplash.jpg Found CBFS file fallback/romstage Found CBFS file fallback/coreboot_ram Found CBFS file fallback/payload Found CBFS file Running option rom at c800:01e8 finalize PMM malloc finalize Add to e820 map: 0009f400 00000c00 2 Add to e820 map: 0fedfc00 0000f000 1 Returned 61440 bytes of ZoneHigh e820 map has 6 items: 0: 0000000000000000 - 000000000009f400 = 1 1: 000000000009f400 - 00000000000a0000 = 2 2: 00000000000f0000 - 0000000000100000 = 2 3: 0000000000100000 - 000000000feeec00 = 1 4: 000000000feeec00 - 0000000010000000 = 2 5: 00000000ff800000 - 0000000100000000 = 2 Jump to int19 enter handle_19: NULL Booting from Floppy... invalid handle_legacy_disk:809: a=00000201 b=00000000 c=00000001 d=00000000 ds=0000 es=07c0 ss=0000 si=00000000 di=00000000 bp=00000000 sp=00006f54 cs=f000 ip=bf07 f=0202 Boot failed: could not read the boot disk
enter handle_18: NULL Booting from DVD/CD... Boot failed: Could not read from CDROM (code 0001) enter handle_18: NULL Booting from Hard Disk... Booting from 0000:7c00 enter handle_12: a=00000000 b=0010acd0 c=00000000 d=00000000 ds=0000 es=0000 ss=0000 si=00106e28 di=00016c08 bp=00001ff0 sp=00001ff4 cs=0000 ip=8a9b f=0246
[ 0.000000] Linux version 2.6.35.8-netboot (ranma@nukunuku) (gcc version 4.4.5 (Debian 4.4.5-6) ) #55 Thu Nov 25 16:34:16 CET 2010 [ 0.000000] BIOS-provided physical RAM map: [ 0.000000] BIOS-e820: 0000000000000000 - 000000000009f800 (usable) [ 0.000000] BIOS-e820: 000000000009f800 - 00000000000a0000 (reserved) [ 0.000000] BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved) [ 0.000000] BIOS-e820: 0000000000100000 - 000000001feedc00 (usable) [ 0.000000] BIOS-e820: 000000001feedc00 - 0000000020000000 (reserved) [ 0.000000] BIOS-e820: 00000000ff800000 - 0000000100000000 (reserved) [ 0.000000] Notice: NX (Execute Disable) protection missing in CPU or disabled in BIOS! [ 0.000000] DMI 2.4 present. [ 0.000000] last_pfn = 0x1feed max_arch_pfn = 0x1000000 [ 0.000000] PAT not supported by CPU. [ 0.000000] get_mtrr(0): base hi=00000000 lo=00000006, mask hi=0000000f lo=e0000800 [ 0.000000] init_memory_mapping: 0000000000000000-000000001feed000 [ 0.000000] ACPI: RSDP 000fdc50 00014 (v00 CORE ) [ 0.000000] ACPI: RSDT 1fef102c 0002C (v01 CORE COREBOOT 00000000 CORE 00000000) [ 0.000000] ACPI: FACP 1fef17c3 000F4 (v01 CORE COREBOOT 00000000 CORE 0000002A) [ 0.000000] ACPI: DSDT 1fef1140 00683 (v02 CORE COREBOOT 00000001 INTL 20100528) [ 0.000000] ACPI: FACS 1fef1100 00040 [ 0.000000] ACPI: SSDT 1fef18b7 0007B (v02 CORE DYNADATA 0000002A CORE 0000002A) [ 0.000000] 0MB HIGHMEM available. [ 0.000000] 510MB LOWMEM available. [ 0.000000] mapped low ram: 0 - 1feed000 [ 0.000000] low ram: 0 - 1feed000 [ 0.000000] Zone PFN ranges: [ 0.000000] DMA 0x00000001 -> 0x00001000 [ 0.000000] Normal 0x00001000 -> 0x0001feed [ 0.000000] HighMem empty [ 0.000000] Movable zone start PFN for each node [ 0.000000] early_node_map[2] active PFN ranges [ 0.000000] 0: 0x00000001 -> 0x0000009f [ 0.000000] 0: 0x00000100 -> 0x0001feed [ 0.000000] Using APIC driver default [ 0.000000] ACPI: PM-Timer IO Port: 0xe408 [ 0.000000] Local APIC disabled by BIOS -- you can enable it with "lapic" [ 0.000000] APIC: disable apic facility [ 0.000000] APIC: switched to apic NOOP [ 0.000000] PM: Registered nosave memory: 000000000009f000 - 00000000000a0000 [ 0.000000] PM: Registered nosave memory: 00000000000a0000 - 00000000000f0000 [ 0.000000] PM: Registered nosave memory: 00000000000f0000 - 0000000000100000 [ 0.000000] Allocating PCI resources starting at 20000000 (gap: 20000000:df800000) [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 129677 [ 0.000000] Kernel command line: console=tty0 vga=ext root=/dev/sda2 ro radeon.modeset=1 console=ttyS0,115200 no_console_suspend video=matroxfb:off [ 0.000000] PID hash table entries: 2048 (order: 1, 8192 bytes) [ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes) [ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes) [ 0.000000] Enabling fast FPU save and restore... done. [ 0.000000] Enabling unmasked SIMD FPU exception support... done. [ 0.000000] Initializing CPU#0 [ 0.000000] Subtract (24 early reservations) [ 0.000000] #0 [0001000000 - 00018314f4] TEXT DATA BSS [ 0.000000] #1 [000009f800 - 0000100000] BIOS reserved [ 0.000000] #2 [0001832000 - 0001840049] BRK [ 0.000000] #3 [0000001000 - 0000005000] ACPI WAKEUP [ 0.000000] #4 [0000007000 - 0000008000] PGTABLE [ 0.000000] #5 [0001841000 - 0001842000] BOOTMEM [ 0.000000] #6 [0001842000 - 0001c42000] BOOTMEM [ 0.000000] #7 [0001831500 - 0001831504] BOOTMEM [ 0.000000] #8 [0001831540 - 00018315c0] BOOTMEM [ 0.000000] #9 [00018315c0 - 00018315f0] BOOTMEM [ 0.000000] #10 [0001c42000 - 0001c43000] BOOTMEM [ 0.000000] #11 [0001831600 - 00018316fc] BOOTMEM [ 0.000000] #12 [0001831700 - 0001831740] BOOTMEM [ 0.000000] #13 [0001831740 - 0001831780] BOOTMEM [ 0.000000] #14 [0001831780 - 00018317c0] BOOTMEM [ 0.000000] #15 [00018317c0 - 0001831800] BOOTMEM [ 0.000000] #16 [0001831800 - 0001831840] BOOTMEM [ 0.000000] #17 [0001831840 - 0001831880] BOOTMEM [ 0.000000] #18 [0001831880 - 0001831890] BOOTMEM [ 0.000000] #19 [00018318c0 - 0001831933] BOOTMEM [ 0.000000] #20 [0001831940 - 00018319b3] BOOTMEM [ 0.000000] #21 [0001c43000 - 0001c45000] BOOTMEM [ 0.000000] #22 [0001c45000 - 0001c85000] BOOTMEM [ 0.000000] #23 [0001c85000 - 0001ca5000] BOOTMEM [ 0.000000] Initializing HighMem for node 0 (00000000:00000000) [ 0.000000] Memory: 509828k/523188k available (5091k kernel code, 12968k reserved, 2440k data, 356k init, 0k highmem) [ 0.000000] virtual kernel memory layout: [ 0.000000] fixmap : 0xfffa3000 - 0xfffff000 ( 368 kB) [ 0.000000] pkmap : 0xffc00000 - 0xffe00000 (2048 kB) [ 0.000000] vmalloc : 0xe06ed000 - 0xffbfe000 ( 501 MB) [ 0.000000] lowmem : 0xc0000000 - 0xdfeed000 ( 510 MB) [ 0.000000] .init : 0xc175c000 - 0xc17b5000 ( 356 kB) [ 0.000000] .data : 0xc14f8e35 - 0xc175afe4 (2440 kB) [ 0.000000] .text : 0xc1000000 - 0xc14f8e35 (5091 kB) [ 0.000000] Checking if this processor honours the WP bit even in supervisor mode...Ok. [ 0.000000] Hierarchical RCU implementation. [ 0.000000] RCU-based detection of stalled CPUs is disabled. [ 0.000000] Verbose stalled-CPUs detection is disabled. [ 0.000000] NR_IRQS:288 [ 0.000000] Console: colour VGA+ 80x50 [ 0.000000] console [tty0] enabled [ 0.000000] console [ttyS0] enabled [ 0.000000] Fast TSC calibration using PIT [ 0.000000] Detected 501.221 MHz processor. [ 0.020014] Calibrating delay loop (skipped), value calculated using timer frequency.. 1002.44 BogoMIPS (lpj=5012210) [ 0.033010] pid_max: default: 32768 minimum: 301 [ 0.040245] Mount-cache hash table entries: 512 [ 0.045477] CPU serial number disabled. [ 0.050037] mce: CPU supports 5 MCE banks [ 0.054251] Performance Events: [ 0.057342] no APIC, boot with the "lapic" boot parameter to force-enable it. [ 0.060024] no hardware sampling interrupt available. [ 0.070021] p6 PMU driver. [ 0.072926] ... version: 0 [ 0.077129] ... bit width: 32 [ 0.080022] ... generic registers: 2 [ 0.084244] ... value mask: 00000000ffffffff [ 0.090021] ... max period: 000000007fffffff [ 0.095478] ... fixed-purpose events: 0 [ 0.100020] ... event mask: 0000000000000003 [ 0.105533] CPU: Intel Pentium III (Katmai) stepping 02 [ 0.114924] ACPI: Core revision 20100428 [ 0.125968] ACPI: setting ELCR to 0200 (from 0000) [ 0.130032] ACPI: FADT smi_command is not set, mode transitions not supported. [ 0.137646] ACPI: SCI_EN status: 1 [ 0.140024] ACPI: FADT smi_command is not set, mode transitions not supported. [ 0.147644] ACPI: SCI_EN status: 1 [ 0.150841] devtmpfs: initialized [ 0.155904] NET: Registered protocol family 16 [ 0.163413] ACPI: bus type pci registered [ 0.171702] PCI: PCI BIOS revision 2.10 entry at 0xffe77, last bus=1 [ 0.178271] PCI: Using configuration type 1 for base access [ 0.276065] bio: create slab <bio-0> at 0 [ 0.289230] ACPI: Interpreter enabled [ 0.290147] ACPI: (supports S0 S1 S2 S3 S5) [ 0.295061] ACPI: Using PIC for interrupt routing [ 0.319114] ACPI: No dock devices found. [ 0.320114] PCI: DMI: pci_use_crs=1 pci_probe=0000000b [ 0.325407] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug [ 0.331781] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff]) [ 0.343577] pci_root PNP0A03:00: host bridge window [io 0x0000-0x0cf7] [ 0.350113] pci_root PNP0A03:00: host bridge window [io 0x0d00-0xffff] [ 0.360038] pci_root PNP0A03:00: host bridge window [mem 0x20000000-0xffffffff] [ 0.370566] * Found PM-Timer Bug on the chipset. Due to workarounds for a bug, [ 0.370574] * this clock source is slow. Consider trying other clock sources [ 0.380096] pci 0000:00:04.3: quirk: [io 0xe400-0xe43f] claimed by PIIX4 ACPI [ 0.390036] pci 0000:00:04.3: quirk: [io 0x0f00-0x0f0f] claimed by PIIX4 SMB [ 0.400527] pci 0000:00:01.0: PCI bridge to [bus 01-01] [ 0.417502] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 10 11 12) *0, disabled. [ 0.425108] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 10 11 12) *0, disabled. [ 0.435050] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 7 10 11 12) *0, disabled. [ 0.445057] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 10 11 12) *0, disabled. [ 0.455640] vgaarb: device added: PCI:0000:00:0c.0,decodes=io+mem,owns=io+mem,locks=none [ 0.460096] vgaarb: loaded [ 0.464385] SCSI subsystem initialized [ 0.472061] usbcore: registered new interface driver usbfs [ 0.480474] usbcore: registered new interface driver hub [ 0.486473] usbcore: registered new device driver usb [ 0.492657] Advanced Linux Sound Architecture Driver Version 1.0.23. [ 0.500422] PCI: Using ACPI for IRQ routing [ 0.506809] cfg80211: Calling CRDA to update world regulatory domain [ 0.510567] Switching to clocksource tsc [ 0.520250] pnp: PnP ACPI init [ 0.523568] ACPI: bus type pnp registered [ 0.530439] ERROR: Unable to locate IOAPIC for GSI 1 [ 0.536605] ERROR: Unable to locate IOAPIC for GSI 12 [ 0.542893] ERROR: Unable to locate IOAPIC for GSI 6 [ 0.550609] pnp: PnP ACPI: found 5 devices [ 0.554863] ACPI: ACPI bus type pnp unregistered [ 0.559822] system 00:04: [io 0xe400-0xe43f] has been reserved [ 0.565953] system 00:04: [io 0x0f00-0x0f0f] has been reserved [ 0.572157] system 00:04: [mem 0xff800000-0xffffffff] has been reserved [ 0.653284] pci 0000:00:01.0: PCI bridge to [bus 01-01] [ 0.658730] pci 0000:00:01.0: bridge window [io disabled] [ 0.664639] pci 0000:00:01.0: bridge window [mem disabled] [ 0.670550] pci 0000:00:01.0: bridge window [mem pref disabled] [ 0.677091] NET: Registered protocol family 2 [ 0.681913] IP route cache hash table entries: 4096 (order: 2, 16384 bytes) [ 0.689638] TCP established hash table entries: 16384 (order: 5, 131072 bytes) [ 0.697862] TCP bind hash table entries: 16384 (order: 4, 65536 bytes) [ 0.704980] TCP: Hash tables configured (established 16384 bind 16384) [ 0.711710] TCP reno registered [ 0.715075] UDP hash table entries: 256 (order: 0, 4096 bytes) [ 0.721180] UDP-Lite hash table entries: 256 (order: 0, 4096 bytes) [ 0.727928] NET: Registered protocol family 1 [ 0.732959] RPC: Registered udp transport module. [ 0.737875] RPC: Registered tcp transport module. [ 0.742935] RPC: Registered tcp NFSv4.1 backchannel transport module. [ 0.749649] pci 0000:00:00.0: Limiting direct PCI/PCI transfers [ 0.756186] kvm: no hardware support [ 0.760076] has_svm: not amd [ 0.763161] kvm: no hardware support [ 0.768562] platform rtc_cmos: registered platform RTC device (no PNP device found) [ 0.783023] VFS: Disk quotas dquot_6.5.2 [ 0.787238] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes) [ 0.795198] fuse init (API version 7.14) [ 0.800786] Btrfs loaded [ 0.803572] msgmni has been set to 995 [ 0.809702] io scheduler noop registered [ 0.813838] io scheduler deadline registered [ 0.818385] io scheduler cfq registered (default) [ 0.827368] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input0 [ 0.835241] ACPI: Power Button [PWRF] [ 1.387649] lp: driver loaded but no devices found [ 1.392977] Linux agpgart interface v0.103 [ 1.397556] agpgart-intel 0000:00:00.0: Intel 440BX Chipset [ 1.421908] agpgart-intel 0000:00:00.0: AGP aperture is 256M @ 0xe0000000 [ 1.430195] [drm] Initialized drm 1.1.0 20060810 [ 1.435404] [drm] radeon kernel modesetting enabled. [ 1.441523] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled [ 1.448620] serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A [ 1.456233] serial8250: ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A [ 1.469916] parport0: PC-style at 0x378 (0x778) [PCSPP,TRISTATE,EPP] [ 1.477276] parport0: irq 7 detected [ 1.560065] lp0: using parport0 (polling). [ 1.573877] loop: module loaded [ 1.580950] scsi0 : ata_piix [ 1.585086] scsi1 : ata_piix [ 1.588981] ata1: PATA max UDMA/33 cmd 0x1f0 ctl 0x3f6 bmdma 0x1420 irq 14 [ 1.596158] ata2: PATA max UDMA/33 cmd 0x170 ctl 0x376 bmdma 0x1428 irq 15 [ 1.609413] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k6-NAPI [ 1.616678] e1000: Copyright (c) 1999-2006 Intel Corporation. [ 1.623186] e1000e: Intel(R) PRO/1000 Network Driver - 1.0.2-k4 [ 1.629395] e1000e: Copyright (c) 1999 - 2009 Intel Corporation. [ 1.637221] e100: Intel(R) PRO/100 Network Driver, 3.5.24-k2-NAPI [ 1.643612] e100: Copyright(c) 1999-2006 Intel Corporation [ 1.654073] tun: Universal TUN/TAP device driver, 1.6 [ 1.659458] tun: (C) 1999-2004 Max Krasnyansky maxk@qualcomm.com [ 1.666843] r8169 Gigabit Ethernet driver 2.3LK-NAPI loaded [ 1.674388] ACPI: PCI Interrupt Link [LNKD] enabled at IRQ 11 [ 1.689610] r8169 0000:00:09.0: PCI INT A -> Link[LNKD] -> GSI 11 (level, low) -> IRQ 11 [ 1.698168] r8169 0000:00:09.0: (unregistered net_device): no PCI Express capability [ 1.707107] r8169 0000:00:09.0: eth0: RTL8110s at 0xe0704000, 00:08:54:38:a1:44, XID 04000000 IRQ 11 [ 1.722213] console [netcon0] enabled [ 1.726084] netconsole: network logging started [ 1.730926] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver [ 1.738046] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver [ 1.744970] uhci_hcd: USB Universal Host Controller Interface driver [ 1.751812] uhci_hcd 0000:00:04.2: PCI INT D -> Link[LNKD] -> GSI 11 (level, low) -> IRQ 11 [ 1.760657] uhci_hcd 0000:00:04.2: UHCI Host Controller [ 1.766160] uhci_hcd 0000:00:04.2: new USB bus registered, assigned bus number 1 [ 1.774070] uhci_hcd 0000:00:04.2: irq 11, io base 0x00001400 [ 1.782234] hub 1-0:1.0: USB hub found [ 1.786230] hub 1-0:1.0: 2 ports detected [ 1.791224] Initializing USB Mass Storage driver... [ 1.796765] usbcore: registered new interface driver usb-storage [ 1.803095] USB Mass Storage support registered. [ 1.809199] PNP: PS/2 Controller [PNP0303:KBD,PNP0f13:MOU] at 0x60,0x64 irq 1,12 [ 1.817389] ata1.00: ATA-6: WDC WD1200JB-00DUA0, 65.13G65, max UDMA/100 [ 1.824264] ata1.00: 234441648 sectors, multi 0: LBA48 [ 1.832453] serio: i8042 KBD port at 0x60,0x64 irq 1 [ 1.837625] serio: i8042 AUX port at 0x60,0x64 irq 12 [ 1.845732] mice: PS/2 mouse device common for all mice [ 1.853133] input: PC Speaker as /devices/platform/pcspkr/input/input1 [ 1.860802] rtc_cmos rtc_cmos: RTC can wake from S4 [ 1.866788] rtc_cmos rtc_cmos: rtc core: registered rtc_cmos as rtc0 [ 1.873560] rtc0: alarms up to one month, 114 bytes nvram [ 1.879842] i2c /dev entries driver [ 1.883982] ata1.00: configured for UDMA/33 [ 1.889217] scsi 0:0:0:0: Direct-Access ATA WDC WD1200JB-00D 65.1 PQ: 0 ANSI: 5 [ 1.901906] sd 0:0:0:0: [sda] 234441648 512-byte logical blocks: (120 GB/111 GiB) [ 1.911646] piix4_smbus 0000:00:04.3: SMBus Host Controller at 0xf00, revision 0 [ 1.919817] input: AT Raw Set 2 keyboard as /devices/platform/i8042/serio0/input/input2 [ 1.928927] sd 0:0:0:0: Attached scsi generic sg0 type 0 [ 1.935157] sd 0:0:0:0: [sda] Write Protect is off [ 1.941860] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA [ 1.955158] coretemp: CPU (model=0x7) has no thermal sensor. [ 1.961398] sda: sda1 sda2 sda3 < sda5 > sda4 [ 2.024169] sd 0:0:0:0: [sda] Attached SCSI disk [ 2.110100] usb 1-1: new low speed USB device using uhci_hcd and address 2 [ 2.342160] Software Watchdog Timer: 0.07 initialized. soft_noboot=0 soft_margin=60 sec (nowayout= 0) [ 2.351723] md: raid1 personality registered for level 1 [ 2.358459] device-mapper: ioctl: 4.17.0-ioctl (2010-03-05) initialised: dm-devel@redhat.com [ 2.367679] cpuidle: using governor ladder [ 2.372082] cpuidle: using governor menu [ 2.409011] input: Microsoft Microsoft 5-Button Mouse with IntelliEye(TM) as /devices/pci0000:00/0000:00:04.2/usb1/1-1/1-1:1.0/input/input3 [ 2.422751] generic-usb 0003:045E:0047.0001: input: USB HID v1.10 Mouse [Microsoft Microsoft 5-Button Mouse with IntelliEye(TM)] on usb-0000:00:04.2-1/input0 [ 2.437597] usbcore: registered new interface driver usbhid [ 2.443477] usbhid: USB HID core driver [ 2.447528] ramzswap: num_devices not specified. Using default: 1 [ 2.453864] ramzswap: Creating 1 devices ... [ 2.462241] ALSA device list: [ 2.465365] No soundcards found. [ 2.468987] u32 classifier [ 2.471991] Actions configured [ 2.475612] Netfilter messages via NETLINK v0.30. [ 2.480650] nf_conntrack version 0.5.0 (7966 buckets, 31864 max) [ 2.487494] ctnetlink v0.93: registering with nfnetlink. [ 2.493259] IPv4 over IPv4 tunneling driver [ 2.498974] ip_tables: (C) 2000-2006 Netfilter Core Team [ 2.504777] TCP bic registered [ 2.507995] TCP cubic registered [ 2.511487] TCP westwood registered [ 2.515183] TCP vegas registered [ 2.518837] NET: Registered protocol family 10 [ 2.525549] ip6_tables: (C) 2000-2006 Netfilter Core Team [ 2.531403] IPv6 over IPv4 tunneling driver [ 2.537852] NET: Registered protocol family 17 [ 2.542668] lib80211: common routines for IEEE802.11 drivers [ 2.548627] Using IPI Shortcut mode [ 2.555356] rtc_cmos rtc_cmos: setting system clock to 2010-12-01 21:56:43 UTC (1291240603) [ 2.564577] md: Waiting for all devices to be available before autodetect [ 2.571727] md: If you don't use raid, use raid=noautodetect [ 2.578890] md: Autodetecting RAID arrays. [ 2.583339] md: Scanned 0 and added 0 devices. [ 2.588039] md: autorun ... [ 2.591107] md: ... autorun DONE. [ 2.623263] EXT4-fs (sda2): mounted filesystem with ordered data mode. Opts: (null) [ 2.631628] VFS: Mounted root (ext2 filesystem) readonly on device 8:2. [ 2.655607] devtmpfs: mounted [ 2.658915] Freeing unused kernel memory: 356k freed [ 2.666126] Write protecting the kernel text: 5092k [ 2.671612] Write protecting the kernel read-only data: 1896k
INIT: version 2.88 booting booting... Starting the hotplug events dispatcher: udevd[ 4.537857] udev[1260]: starting version 163
The kernel used is:
$ pacman -Q kernel26 kernel26 2.6.36.2-1
Something is wrong (see dmesg) and I don't have /proc/acpi/:
$ ls /sys/power/ disk image_size pm_async pm_test resume state wakeup_count
$ cat /sys/power/* test testproc [shutdown] reboot 524288000 1 [none] core processors platform devices freezer 0:0 disk 0
$ dmesg | grep -i acpi ACPI: RSDP 000fd7d0 00014 (v00 CORE ) ACPI: RSDT 0fef102c 0002C (v01 CORE COREBOOT 00000000 CORE 00000000) ACPI: FACP 0fef17dc 000F4 (v01 CORE COREBOOT 00000000 CORE 0000002A) ACPI: DSDT 0fef1140 0069C (v02 CORE COREBOOT 00000001 INTL 20101013) ACPI: FACS 0fef1100 00040 ACPI: SSDT 0fef18d0 0005F (v02 CORE DYNADATA 0000002A CORE 0000002A) ACPI: PM-Timer IO Port: 0xe408 #7 [0000011000 - 0000015000] ACPI WAKEUP ACPI: Core revision 20100702 ACPI Error: Found unknown opcode 0xE4 at AML address d06ee178 offset 0x14, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xE4 at AML address d06ee178 offset 0x14, ignoring (20100702/psloop-141) ACPI Exception: AE_CTRL_PENDING, While creating Arg 1 (20100702/dsutils-763) ACPI Error: Found unknown opcode 0xC3 at AML address 00000008 offset 0x2F911EA4, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xE2 at AML address 00000009 offset 0x2F911EA5, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xF0 at AML address 0000000b offset 0x2F911EA7, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0x2C at AML address 00000020 offset 0x2F911EBC, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xE9 at AML address 00000025 offset 0x2F911EC1, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xF0 at AML address 00000027 offset 0x2F911EC3, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xC1 at AML address 00000029 offset 0x2F911EC5, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xF0 at AML address 0000002b offset 0x2F911EC7, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xC1 at AML address 0000002d offset 0x2F911EC9, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xF0 at AML address 0000002f offset 0x2F911ECB, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xC1 at AML address 00000031 offset 0x2F911ECD, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xF0 at AML address 00000033 offset 0x2F911ECF, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xC1 at AML address 00000035 offset 0x2F911ED1, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xF0 at AML address 00000037 offset 0x2F911ED3, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xC1 at AML address 0000003d offset 0x2F911ED9, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xF0 at AML address 0000003f offset 0x2F911EDB, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xEE at AML address 00000040 offset 0x2F911EDC, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xC0 at AML address 00000043 offset 0x2F911EDF, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0x39 at AML address 00000050 offset 0x2F911EEC, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xE7 at AML address 00000051 offset 0x2F911EED, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xF0 at AML address 00000053 offset 0x2F911EEF, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xC1 at AML address 00000061 offset 0x2F911EFD, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xF0 at AML address 00000063 offset 0x2F911EFF, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xF2 at AML address 00000064 offset 0x2F911F00, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xE6 at AML address 00000065 offset 0x2F911F01, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xF0 at AML address 00000067 offset 0x2F911F03, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xFE at AML address 00000069 offset 0x2F911F05, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xF0 at AML address 0000006b offset 0x2F911F07, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xCF at AML address 00000079 offset 0x2F911F15, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xF0 at AML address 0000007b offset 0x2F911F17, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xF0 at AML address 0000008b offset 0x2F911F27, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xFE at AML address 00000100 offset 0x2F911F9C, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xE3 at AML address 00000101 offset 0x2F911F9D, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xF0 at AML address 00000103 offset 0x2F911F9F, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xF0 at AML address 00000109 offset 0x2F911FA5, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xF0 at AML address 0000010b offset 0x2F911FA7, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xF0 at AML address 00000117 offset 0x2F911FB3, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xEE at AML address 000001b4 offset 0x2F912050, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xC0 at AML address 000001b7 offset 0x2F912053, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0x5BC1 at AML address 000001d4 offset 0x2F912070, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xC1 at AML address 000001d5 offset 0x2F912071, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xF0 at AML address 000001d7 offset 0x2F912073, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0x40 at AML address 000001d8 offset 0x2F912074, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xC1 at AML address 000001d9 offset 0x2F912075, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xF0 at AML address 000001db offset 0x2F912077, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xF0 at AML address 000001e3 offset 0x2F91207F, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xF8 at AML address 00000400 offset 0x2F91229C, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0x3 at AML address 00000401 offset 0x2F91229D, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xF8 at AML address 00000402 offset 0x2F91229E, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0x2 at AML address 00000403 offset 0x2F91229F, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0x3 at AML address 00000409 offset 0x2F9122A5, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xC0 at AML address 0000040e offset 0x2F9122AA, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0x26 at AML address 00000410 offset 0x2F9122AC, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0x1E at AML address 0000041a offset 0x2F9122B6, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0x1E at AML address 0000041c offset 0x2F9122B8, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0x3 at AML address 00000449 offset 0x2F9122E5, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0x4 at AML address 00000451 offset 0x2F9122ED, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0x1B at AML address 0000046c offset 0x2F912308, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0xC0 at AML address 00000476 offset 0x2F912312, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0x1E at AML address 00000480 offset 0x2F91231C, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0x3E at AML address 00000482 offset 0x2F91231E, ignoring (20100702/psloop-141) ACPI Error: Found unknown opcode 0x18 at AML address 00000484 offset 0x2F912320, ignoring (20100702/psloop-141) ACPI Error (dswload-0677): [` ] Namespace lookup failure, AE_NOT_FOUND ACPI Exception: AE_NOT_FOUND, During name lookup/catalog (20100702/psloop-231) ACPI Exception: AE_NOT_FOUND, While loading namespace from ACPI tables (20100702/tbxface-640) ACPI: Unable to load the System Description Tables ACPI: Interpreter disabled. pci 0000:00:04.3: quirk: [io 0xe400-0xe43f] claimed by PIIX4 ACPI pnp: PnP ACPI: disabled
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Idwer Vollering -
Rudolf Marek -
Stefan Reinauer -
Stefan Reinauer -
Tobias Diedrich -
Uwe Hermann