[v2] r4809 - in trunk/coreboot-v2/src: arch/i386/boot config cpu/x86/mtrr mainboard/gigabyte/m57sli northbridge/amd/amdk8 northbridge/intel/i82810 northbridge/via/cx700 southbridge/via/vt8237r superio/ite/it8716f
Author: myles Date: 2009-10-19 18:21:30 +0200 (Mon, 19 Oct 2009) New Revision: 4809
Modified: trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c trunk/coreboot-v2/src/config/Options.lb trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Makefile.inc trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c trunk/coreboot-v2/src/northbridge/intel/i82810/raminit.c trunk/coreboot-v2/src/northbridge/via/cx700/cx700_lpc.c trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_ide.c trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_nic.c trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_usb.c trunk/coreboot-v2/src/superio/ite/it8716f/superio.c Log: Clean up some #ifdef CONFIG_* Change HAVE_FAN_CTL to be specific to the SuperIO that supports it.
Signed-off-by: Myles Watson mylesgw@gmail.com Acked-by: Uwe Hermann uwe@hermann-uwe.de
Modified: trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c 2009-10-18 18:35:50 UTC (rev 4808) +++ trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c 2009-10-19 16:21:30 UTC (rev 4809) @@ -99,7 +99,7 @@
static struct lb_serial *lb_serial(struct lb_header *header) { -#if defined(CONFIG_TTYS0_BASE) +#if CONFIG_CONSOLE_SERIAL8250 struct lb_record *rec; struct lb_serial *serial; rec = lb_new_record(header); @@ -126,22 +126,22 @@
static void lb_console(struct lb_header *header) { -#ifdef CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL8250 add_console(header, LB_TAG_CONSOLE_SERIAL8250); #endif -#ifdef CONFIG_CONSOLE_VGA +#if CONFIG_CONSOLE_VGA add_console(header, LB_TAG_CONSOLE_VGA); #endif -#ifdef CONFIG_CONSOLE_BTEXT +#if CONFIG_CONSOLE_BTEXT add_console(header, LB_TAG_CONSOLE_BTEXT); #endif -#ifdef CONFIG_CONSOLE_LOGBUF +#if CONFIG_CONSOLE_LOGBUF add_console(header, LB_TAG_CONSOLE_LOGBUF); #endif -#ifdef CONFIG_CONSOLE_SROM +#if CONFIG_CONSOLE_SROM add_console(header, LB_TAG_CONSOLE_SROM); #endif -#ifdef CONFIG_USBDEBUG_DIRECT +#if CONFIG_USBDEBUG_DIRECT add_console(header, LB_TAG_CONSOLE_EHCI); #endif }
Modified: trunk/coreboot-v2/src/config/Options.lb =================================================================== --- trunk/coreboot-v2/src/config/Options.lb 2009-10-18 18:35:50 UTC (rev 4808) +++ trunk/coreboot-v2/src/config/Options.lb 2009-10-19 16:21:30 UTC (rev 4809) @@ -712,8 +712,8 @@ comment "PCIBIOS IRQ support" end define CONFIG_IOAPIC - default none - export used + default 0 + export always comment "IOAPIC support" end
@@ -845,7 +845,7 @@ # Misc device options ###############################################
-define CONFIG_HAVE_FANCTL +define CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL default 0 export used comment "Include board specific FAN control initialization" @@ -1103,14 +1103,14 @@ end
define CONFIG_VIDEO_MB - default none - export used + default 0 + export always comment "Integrated graphics with UMA has dynamic setup" end
define CONFIG_GFXUMA - default none - export used + default 0 + export always comment "GFX UMA" end
Modified: trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c =================================================================== --- trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c 2009-10-18 18:35:50 UTC (rev 4808) +++ trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c 2009-10-19 16:21:30 UTC (rev 4809) @@ -37,7 +37,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h>
-#ifdef CONFIG_GFXUMA +#if CONFIG_GFXUMA extern uint64_t uma_memory_base, uma_memory_size; #endif
Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb 2009-10-18 18:35:50 UTC (rev 4808) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb 2009-10-19 16:21:30 UTC (rev 4809) @@ -150,7 +150,7 @@ end end
-if CONFIG_HAVE_FANCTL +if CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL object fanctl.o end
Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig 2009-10-18 18:35:50 UTC (rev 4808) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig 2009-10-19 16:21:30 UTC (rev 4809) @@ -7,6 +7,7 @@ select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_MCP55 select SUPERIO_ITE_IT8716F + select SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select USE_PRINTK_IN_CAR @@ -143,9 +144,3 @@ int default 11 depends on BOARD_GIGABYTE_M57SLI - -# not globally defined yet, so can't "select" this -config HAVE_FANCTL - bool - default y - depends on BOARD_GIGABYTE_M57SLI
Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Makefile.inc 2009-10-18 18:35:50 UTC (rev 4808) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Makefile.inc 2009-10-19 16:21:30 UTC (rev 4809) @@ -29,7 +29,7 @@ obj-$(CONFIG_AP_CODE_IN_CAR) += apc_auto.o obj-$(CONFIG_GENERATE_ACPI_TABLES) += dsdt.o obj-$(CONFIG_GENERATE_ACPI_TABLES) += acpi_tables.o -obj-$(CONFIG_HAVE_FANCTL) += fanctl.o +obj-$(CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) += fanctl.o
# This is part of the conversion to init-obj and away from included code. initobj-y += crt0.o
Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb 2009-10-18 18:35:50 UTC (rev 4808) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb 2009-10-19 16:21:30 UTC (rev 4809) @@ -115,7 +115,7 @@
uses CONFIG_USE_PRINTK_IN_CAR
-uses CONFIG_HAVE_FANCTL +uses CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL ### ### Build options ### @@ -141,7 +141,7 @@ ## ## Set-up automatic fan control ## -default CONFIG_HAVE_FANCTL=1 +default CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL=1
## ## Build code for the fallback boot
Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c 2009-10-18 18:35:50 UTC (rev 4808) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c 2009-10-19 16:21:30 UTC (rev 4809) @@ -357,7 +357,7 @@ resource->gran = log2(HT_MEM_HOST_ALIGN); resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; -#ifdef CONFIG_PCI_64BIT_PREF_MEM +#if CONFIG_PCI_64BIT_PREF_MEM resource->flags |= IORESOURCE_BRIDGE; #endif }
Modified: trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c 2009-10-18 18:35:50 UTC (rev 4808) +++ trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c 2009-10-19 16:21:30 UTC (rev 4809) @@ -147,7 +147,7 @@ /* Convert tomk from MB to KB. */ tomk = tomk << 10;
-#ifdef CONFIG_VIDEO_MB +#if CONFIG_VIDEO_MB /* Check for VGA reserved memory. */ if (CONFIG_VIDEO_MB == 512) { tomk -= 512;
Modified: trunk/coreboot-v2/src/northbridge/intel/i82810/raminit.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i82810/raminit.c 2009-10-18 18:35:50 UTC (rev 4808) +++ trunk/coreboot-v2/src/northbridge/intel/i82810/raminit.c 2009-10-19 16:21:30 UTC (rev 4809) @@ -371,7 +371,7 @@ /* Set size for onboard-VGA framebuffer. */ reg8 = pci_read_config8(PCI_DEV(0, 0, 0), SMRAM); reg8 &= 0x3f; /* Disable graphics (for now). */ -#ifdef CONFIG_VIDEO_MB +#if CONFIG_VIDEO_MB if (CONFIG_VIDEO_MB == 512) reg8 |= (1 << 7); /* Enable graphics (512KB RAM). */ else if (CONFIG_VIDEO_MB == 1)
Modified: trunk/coreboot-v2/src/northbridge/via/cx700/cx700_lpc.c =================================================================== --- trunk/coreboot-v2/src/northbridge/via/cx700/cx700_lpc.c 2009-10-18 18:35:50 UTC (rev 4808) +++ trunk/coreboot-v2/src/northbridge/via/cx700/cx700_lpc.c 2009-10-19 16:21:30 UTC (rev 4809) @@ -37,7 +37,7 @@ #define HPET_ADDR 0xfe800000UL #define IOAPIC_ADDR 0xfec00000ULL
-#ifdef CONFIG_IOAPIC +#if CONFIG_IOAPIC struct ioapicreg { unsigned int reg; unsigned int value_low, value_high; @@ -368,7 +368,7 @@ { cx700_set_lpc_registers(dev);
-#ifdef CONFIG_IOAPIC +#if CONFIG_IOAPIC setup_ioapic(); #endif
Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_ide.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_ide.c 2009-10-18 18:35:50 UTC (rev 4808) +++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_ide.c 2009-10-19 16:21:30 UTC (rev 4809) @@ -97,7 +97,7 @@ (sb->ide1_80pin_cable << 4); pci_write_config32(dev, IDE_UDMA, cablesel);
-#ifdef CONFIG_EPIA_VT8237R_INIT +#if CONFIG_EPIA_VT8237R_INIT /* Set PATA Output Drive Strength */ lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC, 0);
Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c 2009-10-18 18:35:50 UTC (rev 4808) +++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c 2009-10-19 16:21:30 UTC (rev 4809) @@ -51,7 +51,7 @@ extern void dump_south(device_t dev); static void southbridge_init_common(struct device *dev);
-#ifdef CONFIG_EPIA_VT8237R_INIT +#if CONFIG_EPIA_VT8237R_INIT /* Interrupts for INT# A B C D */ static const unsigned char pciIrqs[4] = { 10, 11, 12, 0};
@@ -119,7 +119,7 @@ ioapic_table[0].value_high = (lapicid()) << (56 - 32); l = (u32 *)ioapic_base;
-#ifdef CONFIG_EPIA_VT8237R_INIT +#if CONFIG_EPIA_VT8237R_INIT /* Set APIC to APIC Serial bus. */ l[0] = 0x3; l[4] = 0; @@ -157,7 +157,7 @@ /** Set up PCI IRQ routing, route everything through APIC. */ static void pci_routing_fixup(struct device *dev) { -#ifdef CONFIG_EPIA_VT8237R_INIT +#if CONFIG_EPIA_VT8237R_INIT device_t pdev; u8 reg; #endif @@ -171,7 +171,7 @@ /* Gate Interrupts until RAM Writes are flushed */ pci_write_config8(dev, 0x49, 0x20);
-#ifdef CONFIG_EPIA_VT8237R_INIT +#if CONFIG_EPIA_VT8237R_INIT
/* Share INTE-INTH with INTA-INTD as per stock BIOS. */ pci_write_config8(dev, 0x46, 0x00); @@ -256,7 +256,7 @@ /* Set ACPI to 9, must set IRQ 9 override to level! Set PSON gating. */ pci_write_config8(dev, 0x82, 0x40 | VT8237R_ACPI_IRQ);
-#ifdef CONFIG_EPIA_VT8237R_INIT +#if CONFIG_EPIA_VT8237R_INIT /* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */ pci_write_config16(dev, 0x84, 0x3052); #else @@ -288,7 +288,7 @@ * 0 = USB Wakeup */
-#ifdef CONFIG_EPIA_VT8237R_INIT +#if CONFIG_EPIA_VT8237R_INIT pci_write_config8(dev, 0x95, 0xc2); #else pci_write_config8(dev, 0x95, 0xcc); @@ -343,7 +343,7 @@ { u8 enables, reg8; -#ifdef CONFIG_EPIA_VT8237R_INIT +#if CONFIG_EPIA_VT8237R_INIT printk_spew("Entering vt8237r_init, for EPIA.\n"); /* * TODO: Looks like stock BIOS can do this but causes a hang @@ -386,7 +386,7 @@ enables |= 0x08; pci_write_config8(dev, 0x4f, enables);
-#ifdef CONFIG_EPIA_VT8237R_INIT +#if CONFIG_EPIA_VT8237R_INIT /* * Set Read Pass Write Control Enable */ @@ -401,7 +401,7 @@
southbridge_init_common(dev);
-#ifndef CONFIG_EPIA_VT8237R_INIT +#if !CONFIG_EPIA_VT8237R_INIT /* FIXME: Intel needs more bit set for C2/C3. */
/* @@ -460,7 +460,7 @@ pci_write_config8(dev, PCI_COMMAND, byte);
/* EPIA-N(L) Uses CN400 for BIOS Access */ -#ifndef CONFIG_EPIA_VT8237R_INIT +#if !CONFIG_EPIA_VT8237R_INIT /* Enable the internal I/O decode. */ enables = pci_read_config8(dev, 0x6C); enables |= 0x80; @@ -499,7 +499,7 @@ /* Delay transaction control */ pci_write_config8(dev, 0x43, 0xb);
-#ifdef CONFIG_EPIA_VT8237R_INIT +#if CONFIG_EPIA_VT8237R_INIT /* I/O recovery time, default IDE routing */ pci_write_config8(dev, 0x4c, 0x04);
Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_nic.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_nic.c 2009-10-18 18:35:50 UTC (rev 4808) +++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_nic.c 2009-10-19 16:21:30 UTC (rev 4809) @@ -27,7 +27,7 @@
static void vt8237_eth_read_resources(struct device *dev) { -#ifdef CONFIG_EPIA_VT8237R_INIT +#if CONFIG_EPIA_VT8237R_INIT struct resource *res;
/* Fix the I/O Resources of the USB2.0 Interface */
Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_usb.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_usb.c 2009-10-18 18:35:50 UTC (rev 4808) +++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_usb.c 2009-10-19 16:21:30 UTC (rev 4809) @@ -24,14 +24,14 @@ #include <device/pci_ids.h> #include "vt8237r.h"
-#ifdef CONFIG_EPIA_VT8237R_INIT +#if CONFIG_EPIA_VT8237R_INIT u32 usb_io_addr[4] = {0xcc00, 0xd000, 0xd400, 0xd800}; #endif
static void usb_i_init(struct device *dev) {
-#ifdef CONFIG_EPIA_VT8237R_INIT +#if CONFIG_EPIA_VT8237R_INIT u8 reg8;
printk_debug("Entering %s\n", __func__); @@ -70,7 +70,7 @@
static void vt8237_usb_i_read_resources(struct device *dev) { -#ifdef CONFIG_EPIA_VT8237R_INIT +#if CONFIG_EPIA_VT8237R_INIT struct resource *res; u8 function = (u8) dev->path.pci.devfn & 0x7;
@@ -95,7 +95,7 @@
static void usb_ii_init(struct device *dev) { -#ifdef CONFIG_EPIA_VT8237R_INIT +#if CONFIG_EPIA_VT8237R_INIT u8 reg8;
printk_debug("Entering %s\n", __func__); @@ -117,7 +117,7 @@
static void vt8237_usb_ii_read_resources(struct device *dev) { -#ifdef CONFIG_EPIA_VT8237R_INIT +#if CONFIG_EPIA_VT8237R_INIT struct resource *res;
/* Fix the I/O Resources of the USB2.0 Interface */
Modified: trunk/coreboot-v2/src/superio/ite/it8716f/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/ite/it8716f/superio.c 2009-10-18 18:35:50 UTC (rev 4808) +++ trunk/coreboot-v2/src/superio/ite/it8716f/superio.c 2009-10-19 16:21:30 UTC (rev 4809) @@ -51,7 +51,7 @@ pnp_write_config(dev, 0x02, 0x02); }
-#ifdef CONFIG_HAVE_FANCTL +#if CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL extern void init_ec(uint16_t base); #else static void pnp_write_index(uint16_t port_base, uint8_t reg, uint8_t value)
-
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