RE: [LinuxBIOS] FYI: AMD support for cache as ram.

[YhLu]

So you make the romcc to support the real function instead of all inline...?

YH
> -----Original Message-----
> From: [e-mail] [mailto:[e-mail]] 
> Sent: Thursday, June 02, 2005 10:20 PM
> To: LinuxBIOS
> Subject: [LinuxBIOS] FYI: AMD support for cache as ram.
>
> Check out the new BIOS and Kernel Developers Guide.
>
> Eric
>
> LinuxBIOS mailing list
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[LinuxBIOS] FYI: AMD support for cache as ram.

[Li-Ta Lo]

On Fri, 2005-06-03 at 10:04 -0700, YhLu wrote:
> So you make the romcc to support the real function instead of all inline...?

With cache as ram, we don't need romcc, everything can be compiled
by GCC.
> YH
> > -----Original Message-----
> > From: [e-mail] [mailto:[e-mail]] 
> > Sent: Thursday, June 02, 2005 10:20 PM
> > To: LinuxBIOS
> > Subject: [LinuxBIOS] FYI: AMD support for cache as ram.
> >
> > Check out the new BIOS and Kernel Developers Guide.
> >
> > Eric
> >
> > LinuxBIOS mailing list
> > [e-mail]
> > http://www.openbios.org/mailman/listinfo/linuxbios
>
> LinuxBIOS mailing list
> [e-mail]
> http://www.openbios.org/mailman/listinfo/linuxbios

[LinuxBIOS] FYI: AMD support for cache as ram.

[Kevin O'Connor]

On Fri, Jun 03, 2005 at 11:05:14AM -0600, Li-Ta Lo wrote:
> On Fri, 2005-06-03 at 10:04 -0700, YhLu wrote:
> > So you make the romcc to support the real function instead of all inline...?
>
> With cache as ram, we don't need romcc, everything can be compiled
> by GCC.

The AMD docs don't mention a chip revision - does this mean the trick
will work for all Athlon64 and Opterons?

-Kevin