Dear lists, I have been studying the boot process of coreboot more deeply, and following questions came out: 1. Which code clean the bss and set sp pointer to the stack? Since those addresses are defined in coreboot_ram.ld, Should it be in ramstage? If so, where are they? I don't find them. If not, where are they and how do they know the addresses of bss and stack? 2. What's the propose of romstage? Some init in romstage has been done in bootblock, and why those init are done twice?
Thanks, Hamo
Hi Hamo,
On Tue, Jun 14, 2011 at 8:44 AM, Hamo hamo.by@gmail.com wrote:
Dear lists, I have been studying the boot process of coreboot more deeply, and following questions came out:
- Which code clean the bss and set sp pointer to the stack? Since
those addresses are defined in coreboot_ram.ld, Should it be in ramstage? If so, where are they? I don't find them. If not, where are they and how do they know the addresses of bss and stack?
/* bss does not contain data, it is just a space that should be zero * initialized on startup. (typically uninitialized global variables) * crt0.S fills between _bss and _ebss with zeroes. */
As the comment says, it is handled by the ramstage crt0.S code. The stack is the same that is used by romstage until it is changed by ramstage.
- What's the propose of romstage? Some init in romstage has been done
in bootblock, and why those init are done twice?
What do you see done twice? There should be a minimal overlap. Some things need to be setup for romstage to run.
Marc
On Tue, 14 Jun 2011 22:44:20 +0800, Hamo wrote:
- What's the propose of romstage? Some init in romstage has been
done in bootblock, and why those init are done twice?
Historical reasons.
First, coreboot had two parts: bootblock/romstage (which was a single entity) and ramstage. The romstage did raminit and generally set things up so the ramstage could work. As only the top 64kb of flash are guaranteed to be mapped into memory space, it was also responsible for mapping the entire flash.
Then came AMD K8.
Its memory init was more complicated (with all the HyperTransport setup) and thus exceeded the 64kb the romstage lived in, so things were split up. At some point we moved things around so there's a tiny bootblock (doing only flash mapping and maybe deciding which romstage to load), and the romstage doing raminit until the ramstage can be loaded as usual.
Many boards are converted to that new style. As it requires chipset modifications (essentially splitting out the flash mapping code), some boards were not. At some point I hope we'll have all boards follow the new style.
It might not be necessary for ARM, but I'd propose you also stick to the general layout: - bootblock does flash mapping (if necessary) and decides which romstage to load - romstage does raminit - ramstage does businit - payload does whatever is necessary next.
Patrick
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Hamo -
Marc Jones -
Patrick Georgi