[commit] r6229 - in trunk: . src/cpu/amd/model_10xxx src/vendorcode src/vendorcode/amd src/vendorcode/amd/cimx src/vendorcode/amd/cimx/lib src/vendorcode/amd/cimx/sb800
Author: uwe Date: Sat Jan 1 18:44:07 2011 New Revision: 6229 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6229
Log: Add AMD SB800 southbridge CIMx code.
The main CIMx code is in a src/vendorcode directory and should not be changed with regard to coding style etc. in order to remain easily syncable with the "upstream" AMD code.
Signed-off-by: Kerry She Kerry.she@amd.com Acked-by: Stefan Reinauer stepan@coreboot.org
Added: trunk/src/vendorcode/ trunk/src/vendorcode/Makefile.inc trunk/src/vendorcode/amd/ trunk/src/vendorcode/amd/cimx/ trunk/src/vendorcode/amd/cimx/lib/ trunk/src/vendorcode/amd/cimx/lib/Makefile.inc trunk/src/vendorcode/amd/cimx/lib/amdlib32.c trunk/src/vendorcode/amd/cimx/lib/amdlib32.h trunk/src/vendorcode/amd/cimx/sb800/ trunk/src/vendorcode/amd/cimx/sb800/ACPILIB.c trunk/src/vendorcode/amd/cimx/sb800/ACPILIB.h trunk/src/vendorcode/amd/cimx/sb800/AMDLIB.c trunk/src/vendorcode/amd/cimx/sb800/AMDSBLIB.c trunk/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h trunk/src/vendorcode/amd/cimx/sb800/AZALIA.c trunk/src/vendorcode/amd/cimx/sb800/DISPATCHER.c trunk/src/vendorcode/amd/cimx/sb800/EC.c trunk/src/vendorcode/amd/cimx/sb800/ECLIB.c trunk/src/vendorcode/amd/cimx/sb800/ECfan.h trunk/src/vendorcode/amd/cimx/sb800/ECfanLIB.c trunk/src/vendorcode/amd/cimx/sb800/ECfanc.c trunk/src/vendorcode/amd/cimx/sb800/GEC.c trunk/src/vendorcode/amd/cimx/sb800/Gpp.c trunk/src/vendorcode/amd/cimx/sb800/IOLIB.c trunk/src/vendorcode/amd/cimx/sb800/LEGACY.c trunk/src/vendorcode/amd/cimx/sb800/MEMLIB.c trunk/src/vendorcode/amd/cimx/sb800/Makefile.inc trunk/src/vendorcode/amd/cimx/sb800/OEM.h trunk/src/vendorcode/amd/cimx/sb800/PCILIB.c trunk/src/vendorcode/amd/cimx/sb800/PMIO2LIB.c trunk/src/vendorcode/amd/cimx/sb800/PMIOLIB.c trunk/src/vendorcode/amd/cimx/sb800/SATA.c trunk/src/vendorcode/amd/cimx/sb800/SB800.h trunk/src/vendorcode/amd/cimx/sb800/SBCMN.c trunk/src/vendorcode/amd/cimx/sb800/SBDEF.h trunk/src/vendorcode/amd/cimx/sb800/SBMAIN.c trunk/src/vendorcode/amd/cimx/sb800/SBPELIB.c trunk/src/vendorcode/amd/cimx/sb800/SBPOR.c trunk/src/vendorcode/amd/cimx/sb800/SBSUBFUN.h trunk/src/vendorcode/amd/cimx/sb800/SBTYPE.h trunk/src/vendorcode/amd/cimx/sb800/SMM.c trunk/src/vendorcode/amd/cimx/sb800/SbModInf.c trunk/src/vendorcode/amd/cimx/sb800/USB.c Modified: trunk/Makefile trunk/src/cpu/amd/model_10xxx/init_cpus.c
Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Fri Dec 31 20:20:23 2010 (r6228) +++ trunk/Makefile Sat Jan 1 18:44:07 2011 (r6229) @@ -126,6 +126,7 @@ BUILD-y := src/lib src/boot src/console src/devices src/southbridge src/northbridge src/superio src/drivers BUILD-y += util/cbfstool util/sconfig BUILD-$(CONFIG_ARCH_X86) += src/pc80 +BUILD-y += src/vendorcode
ifneq ($(CONFIG_LOCALVERSION),"") COREBOOT_EXTRA_VERSION := -$(call strip_quotes,$(CONFIG_LOCALVERSION))
Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/init_cpus.c Fri Dec 31 20:20:23 2010 (r6228) +++ trunk/src/cpu/amd/model_10xxx/init_cpus.c Sat Jan 1 18:44:07 2011 (r6229) @@ -27,6 +27,7 @@
#include <cpu/x86/mtrr/earlymtrr.c> #include <northbridge/amd/amdfam10/raminit_amdmct.c> +#include <reset.h>
static void prep_fid_change(void); static void init_fidvid_stage2(u32 apicid, u32 nodeid);
Added: trunk/src/vendorcode/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/Makefile.inc Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1 @@ +subdirs-y += amd
Added: trunk/src/vendorcode/amd/cimx/lib/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/lib/Makefile.inc Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,3 @@ + +romstage-y += amdlib32.c +ramstage-y += amdlib32.c
Added: trunk/src/vendorcode/amd/cimx/lib/amdlib32.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/lib/amdlib32.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,84 @@ +#include "amdlib32.h" + +UINT8 ReadIo8 (IN UINT16 port) +{ + UINT8 value; + __asm__ __volatile__ ("inb %w1, %b0" : "=a"(value) : "Nd" (port)); + return value; +} + +UINT16 ReadIo16 (IN UINT16 port) +{ + UINT16 value; + __asm__ __volatile__ ("inw %w1, %w0" : "=a"(value) : "Nd" (port)); + return value; +} + +UINT32 ReadIo32 (IN UINT16 port) +{ + UINT32 value; + __asm__ __volatile__ ("inl %w1, %0" : "=a"(value) : "Nd" (port)); + return value; +} + +VOID WriteIo8 (IN UINT16 port, IN UINT8 value) +{ + __asm__ __volatile__ ("outb %b0, %w1" : : "a" (value), "Nd" (port)); +} + +VOID WriteIo16 (IN UINT16 port, IN UINT16 value) +{ + __asm__ __volatile__ ("outw %w0, %w1" : : "a" (value), "Nd" (port)); +} + +VOID WriteIo32 (IN UINT16 port, IN UINT32 value) +{ + __asm__ __volatile__ ("outl %0, %w1" : : "a" (value), "Nd" (port)); +} + +UINT64 ReadTSC(VOID) +{ + struct tsc_struct { + unsigned lo; + unsigned hi; + } res; + UINT64 ret; + + __asm__ __volatile__ ( + "rdtsc" + : "=a" (res.lo), "=d"(res.hi) /* outputs */ + ); + ret = res.hi; + ret <<= 32; + ret |= res.lo; + return ret; +} + +VOID CpuidRead(IN UINT32 op, IN OUT SB_CPUID_DATA* Data) +{ + asm volatile( + "cpuid" + : "=a" (Data->EAX_Reg), + "=b" (Data->EBX_Reg), + "=c" (Data->ECX_Reg), + "=d" (Data->EDX_Reg) + : "0" (op)); +} + +static inline unsigned int cpuid_ecx(unsigned int op) +{ + unsigned int eax, ecx; + + __asm__("cpuid" + : "=a" (eax), "=c" (ecx) + : "0" (op) + : "ebx", "edx" ); + return ecx; +} + +//static inline unsigned get_core_num(void) +UINT8 ReadNumberOfCpuCores(VOID) +{ + return (cpuid_ecx(0x80000008) & 0xff); +} +
Added: trunk/src/vendorcode/amd/cimx/lib/amdlib32.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/lib/amdlib32.h Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,16 @@ +#ifndef _AMDLIB32_H_ +#define _AMDLIB32_H_ + +#include "cbtypes.h" +#include "Amd.h" + +UINT8 ReadIo8 (IN UINT16 port); +UINT16 ReadIo16 (IN UINT16 port); +UINT32 ReadIo32 (IN UINT16 port); +VOID WriteIo8 (IN UINT16 port, IN UINT8 value); +VOID WriteIo16 (IN UINT16 port, IN UINT16 value); +VOID WriteIo32 (IN UINT16 port, IN UINT32 value); +UINT64 ReadTSC(VOID); +VOID CpuidRead(IN UINT32 op, IN OUT SB_CPUID_DATA* Data); +UINT8 ReadNumberOfCpuCores(VOID); +#endif //_AMDLIB32_H_
Added: trunk/src/vendorcode/amd/cimx/sb800/ACPILIB.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/ACPILIB.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,158 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" + +// +// +// Routine Description: +// +// Locate ACPI table +// +// Arguments: +// +// Signature - table signature +// +//Returns: +// +// pointer to ACPI table +// +// +VOID* +ACPI_LocateTable ( + IN UINT32 Signature + ) +{ + UINT32 i; + UINT32* RsdPtr; + UINT32* Rsdt; + UINTN tableOffset; + DESCRIPTION_HEADER* CurrentTable; + + RsdPtr = (UINT32*) (UINTN)0xe0000; + Rsdt = NULL; + do { + //if ( *RsdPtr == ' DSR' && *(RsdPtr + 1) == ' RTP' ) { //gcc multi-character character constant warning + if ( *RsdPtr == 0x20445352 && *(RsdPtr + 1) == 0x20525450) { + + Rsdt = (UINT32*) (UINTN) ((RSDP*)RsdPtr)->RsdtAddress; + break; + } + RsdPtr += 4; + } while ( RsdPtr <= (UINT32*) (UINTN)0xffff0 ); + if ( Rsdt != NULL && ACPI_GetTableChecksum (Rsdt) == 0 ) { + for ( i = 0; i < (((DESCRIPTION_HEADER*)Rsdt)->Length - sizeof (DESCRIPTION_HEADER)) / 4; i++ ) { + tableOffset = *(UINTN*) ((UINT8*)Rsdt + sizeof (DESCRIPTION_HEADER) + i * 4); + CurrentTable = (DESCRIPTION_HEADER*)tableOffset; + if ( CurrentTable->Signature == Signature ) { + return CurrentTable; + } + } + } + return NULL; +} + +// +// +// Routine Description: +// +// Update table checksum +// +// Arguments: +// +// TablePtr - table pointer +// +// Returns: +// +// none +// +// +VOID +ACPI_SetTableChecksum ( + IN VOID* TablePtr + ) +{ + UINT8 Checksum; + Checksum = 0; + ((DESCRIPTION_HEADER*)TablePtr)->Checksum = 0; + Checksum = ACPI_GetTableChecksum (TablePtr); + ((DESCRIPTION_HEADER*)TablePtr)->Checksum = (UINT8)(0x100 - Checksum); +} + +// +// +// Routine Description: +// +// Get table checksum +// +// Arguments: +// +// TablePtr - table pointer +// +// Returns: +// +// none +// +// +UINT8 +ACPI_GetTableChecksum ( + IN VOID* TablePtr + ) +{ + return GetByteSum (TablePtr, ((DESCRIPTION_HEADER*)TablePtr)->Length); +} + + +UINT8 +GetByteSum ( + IN VOID* pData, + IN UINT32 Length + ) +{ + UINT32 i; + UINT8 Checksum; + Checksum = 0; + for ( i = 0; i < Length; i++ ) { + Checksum = Checksum + (*((UINT8*)pData + i)); + } + return Checksum; +} +VOID +GetSbAcpiMmioBase ( + OUT UINT32* AcpiMmioBase + ) +{ + UINT32 Value16; + + ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint16, &Value16); + *AcpiMmioBase = Value16 << 16; +} + +VOID +GetSbAcpiPmBase ( + OUT UINT16* AcpiPmBase + ) +{ + ReadPMIO (SB_PMIOA_REG60, AccWidthUint16, AcpiPmBase); +} +
Added: trunk/src/vendorcode/amd/cimx/sb800/ACPILIB.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/ACPILIB.h Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,60 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +/** + * RSDP - ACPI 2.0 table RSDP + */ +typedef struct _RSDP +{ + UINT64 Signature; /* RSDP signature "RSD PTR" */ + UINT8 Checksum; /* checksum of the first 20 bytes */ + UINT8 OEMID[6]; /* OEM ID, "LXBIOS" */ + UINT8 Revision; /* 0 for APCI 1.0, 2 for ACPI 2.0 */ + UINT32 RsdtAddress; /* physical address of RSDT */ + UINT32 Length; /* total length of RSDP (including extended part) */ + UINT64 XsdtAddress; /* physical address of XSDT */ + UINT8 ExtendedChecksum; /* chechsum of whole table */ + UINT8 Reserved[3]; +} RSDP; + + +/** + * DESCRIPTION_HEADER - ACPI common table header + */ +typedef struct _DESCRIPTION_HEADER +{ + UINT32 Signature; /* ACPI signature (4 ASCII characters) */ + UINT32 Length; /* Length of table, in bytes, including header */ + UINT8 Revision; /* ACPI Specification minor version # */ + UINT8 Checksum; /* To make sum of entire table == 0 */ + UINT8 OEMID[6]; /* OEM identification */ + UINT8 OEMTableID[8]; /* OEM table identification */ + UINT32 OEMRevision; /* OEM revision number */ + UINT32 CreatorID; /* ASL compiler vendor ID */ + UINT32 CreatorRevision; /* ASL compiler revision number */ +} DESCRIPTION_HEADER; + +VOID* ACPI_LocateTable (IN UINT32 Signature); +VOID ACPI_SetTableChecksum (IN VOID* TablePtr); +UINT8 ACPI_GetTableChecksum (IN VOID* TablePtr); +UINT8 GetByteSum (IN VOID* pData, IN UINT32 Length);
Added: trunk/src/vendorcode/amd/cimx/sb800/AMDLIB.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/AMDLIB.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,82 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" + +UINT8 +getNumberOfCpuCores ( + OUT VOID + ) +{ + UINT8 Result; + Result = 1; + Result = ReadNumberOfCpuCores (); + return Result; +} + +UINT32 +readAlink ( + IN UINT32 Index + ) +{ + UINT32 Data; + WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32, &Index); + ReadIO (ALINK_ACCESS_DATA, AccWidthUint32, &Data); + //Clear Index + Index = 0; + WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32, &Index); + return Data; +} + +VOID +writeAlink ( + IN UINT32 Index, + IN UINT32 Data + ) +{ + WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &Index); + WriteIO (ALINK_ACCESS_DATA, AccWidthUint32 | S3_SAVE, &Data); + //Clear Index + Index = 0; + WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &Index); +} + +VOID +rwAlink ( + IN UINT32 Index, + IN UINT32 AndMask, + IN UINT32 OrMask + ) +{ + UINT32 AccesType; + AccesType = Index & 0xE0000000; + if (AccesType == (AXINDC << 29)) { + writeAlink ((SB_AX_INDXC_REG30 | AccesType), Index & 0x1FFFFFFF); + Index = (SB_AX_DATAC_REG34 | AccesType); + } else if (AccesType == (AXINDP << 29)) { + writeAlink ((SB_AX_INDXP_REG38 | AccesType), Index & 0x1FFFFFFF); + Index = (SB_AX_DATAP_REG3C | AccesType); + } + writeAlink (Index, (readAlink (Index) & AndMask) | OrMask ); +} +
Added: trunk/src/vendorcode/amd/cimx/sb800/AMDSBLIB.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/AMDSBLIB.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,142 @@ +/** + * @file + * + * Southbridge IO access common routine + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: CIMx-SB + * @e sub-project: + * @e $Revision:$ @e $Date:$ + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" + +/*----------------------------------------------------------------------------------------*/ +/** + * SbStall - Delay routine + * + * + * + * @param[in] uSec + * + */ +VOID +SbStall ( + IN UINT32 uSec + ) +{ + UINT16 timerAddr; + UINT32 startTime; + UINT32 elapsedTime; + + ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG64, AccWidthUint16, &timerAddr); + if ( timerAddr == 0 ) { + uSec = uSec / 2; + while ( uSec != 0 ) { + ReadIO (0x80, AccWidthUint8, (UINT8 *) (&startTime)); + uSec--; + } + } else { + ReadIO (timerAddr, AccWidthUint32, &startTime); + for ( ;; ) { + ReadIO (timerAddr, AccWidthUint32, &elapsedTime); + if ( elapsedTime < startTime ) { + elapsedTime = elapsedTime + 0xFFFFFFFF - startTime; + } else { + elapsedTime = elapsedTime - startTime; + } + if ( (elapsedTime * 28 / 100) > uSec ) { + break; + } + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * SbReset - Generate a reset command + * + * + * + * @param[in] OpFlag - Dummy + * + */ +VOID +SbReset ( + IN UINT8 OpFlag + ) +{ + UINT8 Temp; + Temp = OpFlag; + RWIO (0xcf9, AccWidthUint8, 0x0, 0x06); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * outPort80 - Send data to PORT 80 (debug port) + * + * + * + * @param[in] pcode - debug code (32 bits) + * + */ +VOID +outPort80 ( + IN UINT32 pcode + ) +{ + WriteIO (0x80, AccWidthUint8, &pcode); + return; +} + +/** + * AmdSbCopyMem - Memory copy + * + * @param[in] pDest - Destance address point + * @param[in] pSource - Source Address point + * @param[in] Length - Data length + * + */ +VOID +AmdSbCopyMem ( + IN VOID* pDest, + IN VOID* pSource, + IN UINTN Length + ) +{ + UINTN i; + UINT8 *Ptr; + UINT8 *Source; + Ptr = (UINT8*)pDest; + Source = (UINT8*)pSource; + for (i = 0; i < Length; i++) { + *Ptr = *Source; + Source++; + Ptr++; + } +}
Added: trunk/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,97 @@ +/** + * @file + * + * Southbridge IO access common routine define file + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: CIMx-SB + * @e sub-project: + * @e $Revision:$ @e $Date:$ + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + + +//AMDSBLIB Routines + +/** + * SbStall - Delay routine + * + * + * + * @param[in] uSec + * + */ +VOID SbStall (IN UINT32 uSec); + +/** + * SbReset - Generate a reset command + * + * + * + * @param[in] OpFlag - Dummy + * + */ +VOID SbReset (IN UINT8 OpFlag); + +/** + * outPort80 - Send data to PORT 80 (debug port) + * + * + * + * @param[in] pcode - debug code (32 bits) + * + */ +VOID outPort80 (IN UINT32 pcode); + +/** + * getEfuseStatue - Get Efuse status + * + * + * @param[in] Value - Return Chip strap status + * + */ +VOID getEfuseStatus (IN VOID* Value); + +/** + * AmdSbDispatcher - Dispatch Southbridge function + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +AGESA_STATUS AmdSbDispatcher (IN VOID *pConfig); + +/** + * AmdSbCopyMem - Memory copy + * + * @param[in] pDest - Destance address point + * @param[in] pSource - Source Address point + * @param[in] Length - Data length + * + */ +VOID AmdSbCopyMem (IN VOID* pDest, IN VOID* pSource, IN UINTN Length);
Added: trunk/src/vendorcode/amd/cimx/sb800/AZALIA.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/AZALIA.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,502 @@ +/** + * @file + * + * Config Southbridge HD Audio Controller + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: CIMx-SB + * @e sub-project: + * @e $Revision:$ @e $Date:$ + * + */ + +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + + +#include "SBPLATFORM.h" + +// +// Declaration of local functions +// + +VOID configureAzaliaPinCmd (IN AMDSBCFG* pConfig, IN UINT32 ddBAR0, IN UINT8 dbChannelNum); +VOID configureAzaliaSetConfigD4Dword (IN CODECENTRY* tempAzaliaCodecEntryPtr, IN UINT32 ddChannelNum, IN UINT32 ddBAR0); + +/** + * Pin Config for ALC880, ALC882 and ALC883. + * + * + * + */ +CODECENTRY AzaliaCodecAlc882Table[] = +{ + {0x14, 0x01014010}, + {0x15, 0x01011012}, + {0x16, 0x01016011}, + {0x17, 0x01012014}, + {0x18, 0x01A19030}, + {0x19, 0x411111F0}, + {0x1a, 0x01813080}, + {0x1b, 0x411111F0}, + {0x1C, 0x411111F0}, + {0x1d, 0x411111F0}, + {0x1e, 0x01441150}, + {0x1f, 0x01C46160}, + {0xff, 0xffffffff} +}; + +/** + * Pin Config for ALC0262. + * + * + * + */ +CODECENTRY AzaliaCodecAlc262Table[] = +{ + {0x14, 0x01014010}, + {0x15, 0x411111F0}, + {0x16, 0x411111F0}, + {0x18, 0x01A19830}, + {0x19, 0x02A19C40}, + {0x1a, 0x01813031}, + {0x1b, 0x02014C20}, + {0x1c, 0x411111F0}, + {0x1d, 0x411111F0}, + {0x1e, 0x0144111E}, + {0x1f, 0x01C46150}, + {0xff, 0xffffffff} +}; + +/** + * Pin Config for ALC0269. + * + * + * + */ +CODECENTRY AzaliaCodecAlc269Table[] = +{ + {0x12, 0x99A30960}, + {0x14, 0x99130110}, + {0x15, 0x0221401F}, + {0x16, 0x99130120}, + {0x18, 0x01A19850}, + {0x19, 0x02A15951}, + {0x1a, 0x01813052}, + {0x1b, 0x0181405F}, + {0x1d, 0x40134601}, + {0x1e, 0x01441130}, + {0x11, 0x18567140}, + {0x20, 0x0030FFFF}, + {0xff, 0xffffffff} +}; + +/** + * Pin Config for ALC0861. + * + * + * + */ +CODECENTRY AzaliaCodecAlc861Table[] = +{ + {0x01, 0x8086C601}, + {0x0B, 0x01014110}, + {0x0C, 0x01813140}, + {0x0D, 0x01A19941}, + {0x0E, 0x411111F0}, + {0x0F, 0x02214420}, + {0x10, 0x02A1994E}, + {0x11, 0x99330142}, + {0x12, 0x01451130}, + {0x1F, 0x411111F0}, + {0x20, 0x411111F0}, + {0x23, 0x411111F0}, + {0xff, 0xffffffff} +}; + +/** + * Pin Config for ALC0889. + * + * + * + */ +CODECENTRY AzaliaCodecAlc889Table[] = +{ + {0x11, 0x411111F0}, + {0x14, 0x01014010}, + {0x15, 0x01011012}, + {0x16, 0x01016011}, + {0x17, 0x01013014}, + {0x18, 0x01A19030}, + {0x19, 0x411111F0}, + {0x1a, 0x411111F0}, + {0x1b, 0x411111F0}, + {0x1C, 0x411111F0}, + {0x1d, 0x411111F0}, + {0x1e, 0x01442150}, + {0x1f, 0x01C42160}, + {0xff, 0xffffffff} +}; + +/** + * Pin Config for ADI1984. + * + * + * + */ +CODECENTRY AzaliaCodecAd1984Table[] = +{ + {0x11, 0x0221401F}, + {0x12, 0x90170110}, + {0x13, 0x511301F0}, + {0x14, 0x02A15020}, + {0x15, 0x50A301F0}, + {0x16, 0x593301F0}, + {0x17, 0x55A601F0}, + {0x18, 0x55A601F0}, + {0x1A, 0x91F311F0}, + {0x1B, 0x014511A0}, + {0x1C, 0x599301F0}, + {0xff, 0xffffffff} +}; + +/** + * FrontPanel Config table list + * + * + * + */ +CODECENTRY FrontPanelAzaliaCodecTableList[] = +{ + {0x19, 0x02A19040}, + {0x1b, 0x02214020}, + {0xff, 0xffffffff} +}; + +/** + * Current HD Audio support codec list + * + * + * + */ +CODECTBLLIST azaliaCodecTableList[] = +{ + {0x010ec0880, &AzaliaCodecAlc882Table[0]}, + {0x010ec0882, &AzaliaCodecAlc882Table[0]}, + {0x010ec0883, &AzaliaCodecAlc882Table[0]}, + {0x010ec0885, &AzaliaCodecAlc882Table[0]}, + {0x010ec0889, &AzaliaCodecAlc889Table[0]}, + {0x010ec0262, &AzaliaCodecAlc262Table[0]}, + {0x010ec0269, &AzaliaCodecAlc269Table[0]}, + {0x010ec0861, &AzaliaCodecAlc861Table[0]}, + {0x011d41984, &AzaliaCodecAd1984Table[0]}, + { (UINT32) 0x0FFFFFFFF, (CODECENTRY*) (UINTN)0x0FFFFFFFF} +}; + +/** + * azaliaInitBeforePciEnum - Config HD Audio Before PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +azaliaInitBeforePciEnum ( + IN AMDSBCFG* pConfig + ) +{ + if ( pConfig->AzaliaController == 1 ) { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, 0); + } else { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, BIT0); + if ( pConfig->BuildParameters.HdAudioMsi) { + RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG44, AccWidthUint32 | S3_SAVE, ~BIT8, BIT8); + RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG60, AccWidthUint32 | S3_SAVE, ~BIT16, BIT16); + } + } +} + +/** + * azaliaInitAfterPciEnum - Config HD Audio after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +azaliaInitAfterPciEnum ( + IN AMDSBCFG* pConfig + ) +{ + UINT8 Data; + UINT8 i; + UINT8 dbEnableAzalia; + UINT8 dbPinRouting; + UINT8 dbChannelNum; + UINT8 dbTempVariable; + UINT16 dwTempVariable; + UINT32 ddBAR0; + UINT32 ddTempVariable; + dbEnableAzalia = 0; + dbChannelNum = 0; + dbTempVariable = 0; + dwTempVariable = 0; + ddBAR0 = 0; + ddTempVariable = 0; + + if ( pConfig->AzaliaController == 1 ) { + return; + } + + if ( pConfig->AzaliaController != 1 ) { + RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint8 | S3_SAVE, ~BIT1, BIT1); + if ( pConfig->BuildParameters.AzaliaSsid != NULL ) { + RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.AzaliaSsid); + } + ReadPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG10, AccWidthUint32, &ddBAR0); + if ( ddBAR0 != 0 ) { + if ( ddBAR0 != 0xFFFFFFFF ) { + ddBAR0 &= ~(0x03FFF); + dbEnableAzalia = 1; + } + } + } + + if ( dbEnableAzalia ) { + // Get SDIN Configuration + if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin0 == 2 ) { + RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x3E); + RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x00); + } else { + RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x0); + RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x01); + } + if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin1 == 2 ) { + RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x3E); + RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x00); + } else { + RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x0); + RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x01); + } + if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin2 == 2 ) { + RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x3E); + RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x00); + } else { + RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x0); + RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x01); + } + if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin3 == 2 ) { + RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x3E); + RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x00); + } else { + RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x0); + RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x01); + } + // INT#A Azalia resource + Data = 0x93; // Azalia APIC index + WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &Data); + Data = 0x10; // IRQ16 (INTA#) + WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &Data); + + i = 11; + do { + ReadMEM ( ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); + dbTempVariable |= BIT0; + WriteMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); + SbStall (1000); + ReadMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); + i--; + } while ((! (dbTempVariable & BIT0)) && (i > 0) ); + + if ( i == 0 ) { + return; + } + + SbStall (1000); + ReadMEM ( ddBAR0 + SB_AZ_BAR_REG0E, AccWidthUint16, &dwTempVariable); + if ( dwTempVariable & 0x0F ) { + + //atleast one azalia codec found + // ?? E0 is not real register what we expect. we have change to GPIO/and program GPIO Mux + //ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGE0, AccWidthUint8, &dbPinRouting); + dbPinRouting = pConfig->AZALIACONFIG.AzaliaSdinPin; + do { + if ( ( ! (dbPinRouting & BIT0) ) && (dbPinRouting & BIT1) ) { +// dbChannelNum = 3; + configureAzaliaPinCmd (pConfig, ddBAR0, dbChannelNum); + } + dbPinRouting >>= 2; + dbChannelNum++; + } while ( dbChannelNum != 4 ); + } else { + //No Azalia codec found + if ( pConfig->AzaliaController != 2 ) { + dbEnableAzalia = 0; //set flag to disable Azalia + } + } + } + + if ( dbEnableAzalia ) { + //redo clear reset + do { + dwTempVariable = 0; + WriteMEM ( ddBAR0 + SB_AZ_BAR_REG0C, AccWidthUint16 | S3_SAVE, &dwTempVariable); + ReadMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); + dbTempVariable &= ~(BIT0); + WriteMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); + ReadMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); + } while ( dbTempVariable & BIT0 ); + + if ( pConfig->AzaliaSnoop == 1 ) { + RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG42, AccWidthUint8 | S3_SAVE, 0xFF, BIT1 + BIT0); + } + } else { + //disable Azalia controller + RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint16 | S3_SAVE, 0, 0); + // RWPMIO (SB_PMIO_REG59, AccWidthUint8 | S3_SAVE, ~BIT3, 0); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, 0); + // RWPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGFC, AccWidthUint8 | S3_SAVE, 0, 0x55); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, 0); + } +} + +/** + * configureAzaliaPinCmd - Configuration HD Audio PIN Command + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * @param[in] ddBAR0 HD Audio BAR0 base address. + * @param[in] dbChannelNum Channel Number. + * + */ +VOID +configureAzaliaPinCmd ( + IN AMDSBCFG* pConfig, + IN UINT32 ddBAR0, + IN UINT8 dbChannelNum + ) +{ + UINT32 ddTempVariable; + UINT32 ddChannelNum; + CODECTBLLIST* ptempAzaliaOemCodecTablePtr; + CODECENTRY* tempAzaliaCodecEntryPtr; + + if ( (pConfig->AzaliaPinCfg) != 1 ) { + return; + } + + ddChannelNum = dbChannelNum << 28; + ddTempVariable = 0xF0000; + ddTempVariable |= ddChannelNum; + + WriteMEM (ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddTempVariable); + SbStall (600); + ReadMEM (ddBAR0 + SB_AZ_BAR_REG64, AccWidthUint32 | S3_SAVE, &ddTempVariable); + + if ( ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) (UINTN)0xFFFFFFFF))) { + ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) FIXUP_PTR (&azaliaCodecTableList[0]); + } else { + ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr; + } + + while ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF ) { + if ( ptempAzaliaOemCodecTablePtr->CodecID == ddTempVariable ) { + break; + } else { + ++ptempAzaliaOemCodecTablePtr; + } + } + + if ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF ) { + tempAzaliaCodecEntryPtr = (CODECENTRY*) ptempAzaliaOemCodecTablePtr->CodecTablePtr; + + if ( ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) (UINTN)0xFFFFFFFF)) ) { + tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR (tempAzaliaCodecEntryPtr); + } + configureAzaliaSetConfigD4Dword (tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0); + if ( pConfig->AzaliaFrontPanel != 1 ) { + if ( (pConfig->AzaliaFrontPanel == 2) || (pConfig->FrontPanelDetected == 1) ) { + if ( ((pConfig->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr) == NULL) || ((pConfig->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr) == (VOID*) (UINTN)0xFFFFFFFF) ) { + tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR (&FrontPanelAzaliaCodecTableList[0]); + } else { + tempAzaliaCodecEntryPtr = (CODECENTRY*) pConfig->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr; + } + configureAzaliaSetConfigD4Dword (tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0); + } + } + } +} + +/** + * configureAzaliaSetConfigD4Dword - Configuration HD Audio Codec table + * + * + * @param[in] tempAzaliaCodecEntryPtr HD Audio Codec table structure pointer. + * @param[in] ddChannelNum HD Audio Channel Number. + * @param[in] ddBAR0 HD Audio BAR0 base address. + * + */ +VOID +configureAzaliaSetConfigD4Dword ( + IN CODECENTRY* tempAzaliaCodecEntryPtr, + IN UINT32 ddChannelNum, + IN UINT32 ddBAR0 + ) +{ + UINT8 dbtemp1; + UINT8 dbtemp2; + UINT8 i; + UINT32 ddtemp; + UINT32 ddtemp2; + ddtemp = 0; + ddtemp2 = 0; + while ( (tempAzaliaCodecEntryPtr->Nid) != 0xFF ) { + dbtemp1 = 0x20; + if ( (tempAzaliaCodecEntryPtr->Nid) == 0x1 ) { + dbtemp1 = 0x24; + } + + ddtemp = tempAzaliaCodecEntryPtr->Nid; + ddtemp &= 0xff; + ddtemp <<= 20; + ddtemp |= ddChannelNum; + + ddtemp |= (0x700 << 8); + for ( i = 4; i > 0; i-- ) { + do { + ReadMEM (ddBAR0 + SB_AZ_BAR_REG68, AccWidthUint32, &ddtemp2); + } while ( ddtemp2 & BIT0 ); + + dbtemp2 = (UINT8) (( (tempAzaliaCodecEntryPtr->Byte40) >> ((4 - i) * 8 ) ) & 0xff); + ddtemp = (ddtemp & 0xFFFF0000) + ((dbtemp1 - i) << 8) + dbtemp2; + WriteMEM (ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddtemp); + SbStall (60); + } + ++tempAzaliaCodecEntryPtr; + } +} +
Added: trunk/src/vendorcode/amd/cimx/sb800/DISPATCHER.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/DISPATCHER.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,247 @@ +/** + * @file + * + * Function dispatcher. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: CIMx-SB + * @e sub-project: + * @e $Revision:$ @e $Date:$ + * + */ + +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "SBPLATFORM.h" + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- +*/ + + +// +// Declaration of local functions +// + +VOID saveConfigPointer (IN AMDSBCFG* pConfig); +VOID* VerifyImage (IN UINT64 Signature, IN VOID* ImagePtr); +VOID* LocateImage (IN UINT64 Signature); + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/** + * AmdSbDispatcher - Dispatch Southbridge function + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +AGESA_STATUS +AmdSbDispatcher ( + IN VOID *pConfig + ) +{ + AGESA_STATUS Status; + +#ifdef B1_IMAGE + VOID *pAltImagePtr; + CIM_IMAGE_ENTRY AltImageEntry; +#endif + + UINT64 tdValue; + tdValue = 0x32314130384253ULL; + +#ifdef B1_IMAGE + pAltImagePtr = NULL; +#endif + Status = AGESA_UNSUPPORTED; + +#ifdef B1_IMAGE + if ((UINT32) (UINTN) (((AMD_CONFIG_PARAMS*)pConfig)->AltImageBasePtr) != 0xffffffff ) { + if ( ((AMD_CONFIG_PARAMS*)pConfig)->AltImageBasePtr ) { + pAltImagePtr = VerifyImage ( tdValue, (VOID*) (UINTN) ((AMD_CONFIG_PARAMS*)pConfig)->AltImageBasePtr); + } + if ( pAltImagePtr == NULL ) { + pAltImagePtr = LocateImage ( tdValue ); + } + if ( pAltImagePtr != NULL ) { + ((AMD_CONFIG_PARAMS*)pConfig)->ImageBasePtr = (UINT32) (UINTN) pAltImagePtr; + AltImageEntry = (CIM_IMAGE_ENTRY) (UINTN) ((UINT32) (UINTN) pAltImagePtr + (UINT32) (((AMD_IMAGE_HEADER*) (UINTN) pAltImagePtr)->EntryPointAddress)); + (*AltImageEntry) (pConfig); + return Status; + } + } +#endif + saveConfigPointer (pConfig); + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_POWERON_INIT ) { + sbPowerOnInit ((AMDSBCFG*) pConfig); + } + +#ifndef B1_IMAGE + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_INIT ) { + sbBeforePciInit ((AMDSBCFG*)pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_INIT ) { + sbAfterPciInit ((AMDSBCFG*)pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_MID_POST_INIT ) { + sbMidPostInit ((AMDSBCFG*)pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_LATE_POST_INIT ) { + sbLatePost ((AMDSBCFG*)pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_RESTORE_INIT ) { + sbBeforePciRestoreInit ((AMDSBCFG*)pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_RESTORE_INIT ) { + sbAfterPciRestoreInit ((AMDSBCFG*)pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_SERVICE ) { + sbSmmService ((AMDSBCFG*)pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_ACPION ) { + sbSmmAcpiOn ((AMDSBCFG*)pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_EC_FANCONTROL ) { + sbECfancontrolservice((AMDSBCFG*)pConfig);; + } +#endif + return Status; +} + +/** + * LocateImage - Locate Southbridge CIMx module + * + * + * + * @param[in] Signature Southbridge CIMx image signature. + * + */ +VOID* +LocateImage ( + IN UINT64 Signature + ) +{ + VOID *Result; + UINT32 ImagePtr; + ImagePtr = 0xffffffff - (IMAGE_ALIGN - 1); + + while ( ImagePtr >= (0xfffffff - (NUM_IMAGE_LOCATION * IMAGE_ALIGN - 1)) ) { +#ifdef x64 + 12346789 +#else + Result = VerifyImage (Signature, (VOID*) ImagePtr); +#endif + if ( Result != NULL ) { + return Result; + } + ImagePtr -= IMAGE_ALIGN; + } + return NULL; +} + +/** + * VerifyImage - Verify Southbridge CIMx module + * + * + * @param[in] Signature Southbridge CIMx image signature. + * @param[in] ImagePtr Southbridge CIMx image address. + * + */ +VOID* +VerifyImage ( + IN UINT64 Signature, + IN VOID* ImagePtr + ) +{ + UINT16 *TempImagePtr; + UINT16 Sum; + UINT32 i; + Sum = 0; + //if ( (*((UINT32*)ImagePtr) == 'DMA$' && ((CIMFILEHEADER*)ImagePtr)->CreatorID == Signature) ) { //gcc multi-character character constant warning + if ( (*((UINT32*)ImagePtr) == 0x444d4124 && ((CIMFILEHEADER*)ImagePtr)->CreatorID == Signature) ) {//'DMA$' + //GetImage Image size + TempImagePtr = (UINT16*)ImagePtr; + for ( i = 0; i < (((CIMFILEHEADER*)ImagePtr)->ImageSize); i += 2 ) { + Sum = Sum + *TempImagePtr; + TempImagePtr++; + } + if ( Sum == 0 ) { + return ImagePtr; + } + } + return NULL; +} + +/** + * saveConfigPointer - Verify Southbridge CIMx module + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +saveConfigPointer ( + IN AMDSBCFG* pConfig + ) +{ + UINT8 dbReg; + UINT8 i; + UINT32 ddValue; + + ddValue = (UINT32) (UINTN)pConfig; + dbReg = SB_ECMOS_REG08; + + for ( i = 0; i <= 3; i++ ) { + WriteIO (SB_IOMAP_REG72, AccWidthUint8, &dbReg); + WriteIO (SB_IOMAP_REG73, AccWidthUint8, (UINT8*)&ddValue); + ddValue = (ddValue >> 8); + dbReg++; + } +}
Added: trunk/src/vendorcode/amd/cimx/sb800/EC.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/EC.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,121 @@ + +/** + * @file + * + * Config Southbridge EC Controller + * + * Init EC features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: CIMx-SB + * @e sub-project: + * @e $Revision:$ @e $Date:$ + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" + +#ifndef NO_EC_SUPPORT + +/** + * Config EC controller during power-on + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +ecPowerOnInit ( + IN AMDSBCFG* pConfig + ) +{ + //Enable config mode + EnterEcConfig (); + + //Do settings for mailbox - logical device 0x09 + RWEC8 (0x07, 0x00, 0x09); //switch to device 9 (Mailbox) + RWEC8 (0x60, 0x00, (MailBoxPort >> 8)); //set MSB of Mailbox port + RWEC8 (0x61, 0x00, (MailBoxPort & 0xFF)); //set LSB of Mailbox port + RWEC8 (0x30, 0x00, 0x01); //;Enable Mailbox Registers Interface, bit0=1 + + if ( pConfig->BuildParameters.EcKbd == ENABLED) { + //Enable KBRST#, IRQ1 & IRQ12, GateA20 Function signal from IMC + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD6, AccWidthUint8, ~BIT8, BIT0 + BIT1 + BIT2 + BIT3); + + //Disable LPC Decoding of port 60/64 + RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG47), AccWidthUint8 | S3_SAVE, ~BIT5, 0); + + //Enable logical device 0x07 (Keyboard controller) + RWEC8 (0x07, 0x00, 0x07); + RWEC8 (0x30, 0x00, 0x01); + } + + if ( pConfig->BuildParameters.EcChannel0 == ENABLED) { + //Logical device 0x03 + RWEC8 (0x07, 0x00, 0x03); + RWEC8 (0x60, 0x00, 0x00); + RWEC8 (0x61, 0x00, 0x62); + RWEC8 (0x30, 0x00, 0x01); //;Enable Device 8 + } + + //Enable EC (IMC) to generate SMI to BIOS + RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGB3, AccWidthUint8, ~BIT6, BIT6); + ExitEcConfig (); +} + +/** + * Config EC controller before PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +ecInitBeforePciEnum ( + IN AMDSBCFG* pConfig + ) +{ + AMDSBCFG* pTmp; // dummy code + pTmp = pConfig; +} + +/** + * Prepare EC controller to boot to OS. + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +ecInitLatePost ( + IN AMDSBCFG* pConfig + ) +{ + AMDSBCFG* pTmp; // dummy code + pTmp = pConfig; +} +#endif
Added: trunk/src/vendorcode/amd/cimx/sb800/ECLIB.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/ECLIB.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,146 @@ +/** + * @file + * + * Southbridge EC IO access common routine + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" + +// #ifndef NO_EC_SUPPORT + +/*----------------------------------------------------------------------------------------*/ +/** + * EnterEcConfig - Force EC into Config mode + * + * + * + * + */ +VOID +EnterEcConfig ( + ) +{ + UINT16 dwEcIndexPort; + + ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort); + dwEcIndexPort &= ~(BIT0); + RWIO (dwEcIndexPort, AccWidthUint8, 0x00, 0x5A); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * ExitEcConfig - Force EC exit Config mode + * + * + * + * + */ +VOID +ExitEcConfig ( + ) +{ + UINT16 dwEcIndexPort; + + ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort); + dwEcIndexPort &= ~(BIT0); + RWIO (dwEcIndexPort, AccWidthUint8, 0x00, 0xA5); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * ReadEC8 - Read EC register data + * + * + * + * @param[in] Address - EC Register Offset Value + * @param[in] Value - Read Data Buffer + * + */ +VOID +ReadEC8 ( + IN UINT8 Address, + IN UINT8* Value + ) +{ + UINT16 dwEcIndexPort; + + ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort); + dwEcIndexPort &= ~(BIT0); + WriteIO (dwEcIndexPort, AccWidthUint8, &Address); + ReadIO (dwEcIndexPort + 1, AccWidthUint8, Value); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * WriteEC8 - Write date into EC register + * + * + * + * @param[in] Address - EC Register Offset Value + * @param[in] Value - Write Data Buffer + * + */ +VOID +WriteEC8 ( + IN UINT8 Address, + IN UINT8* Value + ) +{ + UINT16 dwEcIndexPort; + + ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort); + dwEcIndexPort &= ~(BIT0); + + WriteIO (dwEcIndexPort, AccWidthUint8, &Address); + WriteIO (dwEcIndexPort + 1, AccWidthUint8, Value); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * RWEC8 - Read/Write EC register + * + * + * + * @param[in] Address - EC Register Offset Value + * @param[in] AndMask - Data And Mask 8 bits + * @param[in] OrMask - Data OR Mask 8 bits + * + */ +VOID +RWEC8 ( + IN UINT8 Address, + IN UINT8 AndMask, + IN UINT8 OrMask + ) +{ + UINT8 Result; + ReadEC8 (Address, &Result); + Result = (Result & AndMask) | OrMask; + WriteEC8 (Address, &Result); +} + +// #endif +
Added: trunk/src/vendorcode/amd/cimx/sb800/ECfan.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/ECfan.h Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,60 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + + +VOID WriteECmsg (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value); +VOID WaitForEcLDN9MailboxCmdAck (VOID); +VOID ReadECmsg (IN UINT8 Address, IN UINT8 OpFlag, OUT VOID* Value); + +// IMC Message Register Software Interface +#define CPU_MISC_BUS_DEV_FUN ((0x18 << 3) + 3) + +#define MSG_SYS_TO_IMC 0x80 +#define Fun_80 0x80 +#define Fun_81 0x81 +#define Fun_82 0x82 +#define Fun_83 0x83 +#define Fun_84 0x84 +#define Fun_85 0x85 +#define Fun_86 0x86 +#define Fun_87 0x87 +#define Fun_88 0x88 +#define Fun_89 0x89 +#define Fun_90 0x90 +#define MSG_IMC_TO_SYS 0x81 +#define MSG_REG0 0x82 +#define MSG_REG1 0x83 +#define MSG_REG2 0x84 +#define MSG_REG3 0x85 +#define MSG_REG4 0x86 +#define MSG_REG5 0x87 +#define MSG_REG6 0x88 +#define MSG_REG7 0x89 +#define MSG_REG8 0x8A +#define MSG_REG9 0x8B +#define MSG_REGA 0x8C +#define MSG_REGB 0x8D +#define MSG_REGC 0x8E +#define MSG_REGD 0x8F + +
Added: trunk/src/vendorcode/amd/cimx/sb800/ECfanLIB.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/ECfanLIB.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,87 @@ +/** + * @file + * + * Southbridge EC IO access common routine + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" +#include "ECfan.h" + +VOID +ReadECmsg ( + IN UINT8 Address, + IN UINT8 OpFlag, + OUT VOID* Value + ) +{ + UINT8 i; + + OpFlag = OpFlag & 0x7f; + if (OpFlag == 0x02) OpFlag = 0x03; + for (i = 0; i <= OpFlag; i++) { + WriteIO(MailBoxPort, AccWidthUint8, &Address); // EC_LDN9_MAILBOX_BASE_ADDRESS + Address++; + ReadIO(MailBoxPort + 1, AccWidthUint8, (UINT8 *)Value+i); // EC_LDN9_MAILBOX_BASE_ADDRESS + } +} + + +VOID +WriteECmsg ( + IN UINT8 Address, + IN UINT8 OpFlag, + IN VOID* Value + ) +{ + UINT8 i; + + OpFlag = OpFlag & 0x7f; + if (OpFlag == 0x02) OpFlag = 0x03; + for (i = 0; i <= OpFlag; i++) { + WriteIO(MailBoxPort, AccWidthUint8, &Address); // EC_LDN9_MAILBOX_BASE_ADDRESS + Address++; + WriteIO(MailBoxPort + 1, AccWidthUint8, (UINT8 *)Value+i); // EC_LDN9_MAILBOX_BASE_ADDRESS + } +} + +VOID +WaitForEcLDN9MailboxCmdAck ( + VOID + ) +{ + UINT8 Msgdata; + UINT16 Delaytime; + Msgdata = 0; + for (Delaytime = 0; Delaytime <= 500; Delaytime++) { + ReadECmsg (MSG_REG0, AccWidthUint8, &Msgdata); + if ( Msgdata == 0xfa) { + break; + } + SbStall (1000); // Wait for 1ms + } +} + +
Added: trunk/src/vendorcode/amd/cimx/sb800/ECfanc.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/ECfanc.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,195 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + + +#include "SBPLATFORM.h" +#include "ECfan.h" +/** + * Table for Function Number + * + * + * + * + */ +UINT8 FunctionNumber[] = +{ + Fun_81, + Fun_83, + Fun_85, + Fun_89, +}; + +/** + * Table for Max Thermal Zone + * + * + * + * + */ +UINT8 MaxZone[] = +{ + 4, + 4, + 4, + 4, +}; + +/** + * Table for Max Register + * + * + * + * + */ +UINT8 MaxRegister[] = +{ + MSG_REG9, + MSG_REGB, + MSG_REG9, + MSG_REGA, +}; + +/*------------------------------------------------------------------------------- +;Procedure: IsZoneFuncEnable +; +;Description: This routine will check every zone support function with BitMap from user define +; +; +;Exit: None +; +;Modified: None +; +;----------------------------------------------------------------------------- +*/ +BOOLEAN +IsZoneFuncEnable ( + UINT16 Flag, + UINT8 func, + UINT8 Zone +) +{ + return (BOOLEAN)(((Flag >> (func *4)) & 0xF) & ((UINT8 )1 << Zone)); +} + +/*------------------------------------------------------------------------------- +;Procedure: sbECfancontrolservice +; +;Description: This routine service EC fan policy +; +; +;Exit: None +; +;Modified: None +; +;----------------------------------------------------------------------------- +*/ +VOID +sbECfancontrolservice ( + IN AMDSBCFG* pConfig + ) +{ + UINT8 ZoneNum; + UINT8 FunNum; + UINT8 RegNum; + UINT8 * CurPoint; + UINT8 FunIndex; + BOOLEAN IsSendEcMsg; + + CurPoint = &pConfig->Pecstruct.MSGFun81zone0MSGREG0 + MaxZone[0] * (MaxRegister[0] - MSG_REG0 + 1); + for ( FunIndex = 1; FunIndex <= 3; FunIndex++ ) { + FunNum = FunctionNumber[FunIndex]; + for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) { + IsSendEcMsg = IsZoneFuncEnable (pConfig->Pecstruct.IMCFUNSupportBitMap, FunIndex, ZoneNum); + for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) { + if (IsSendEcMsg) { + WriteECmsg (RegNum, AccWidthUint8, CurPoint); // + } + CurPoint += 1; + } + if (IsSendEcMsg) { + WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &FunNum); // function number + WaitForEcLDN9MailboxCmdAck (); + } + } + } + CurPoint = &pConfig->Pecstruct.MSGFun81zone0MSGREG0; + for ( FunIndex = 0; FunIndex <= 0; FunIndex++ ) { + FunNum = FunctionNumber[FunIndex]; + for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) { + IsSendEcMsg = IsZoneFuncEnable (pConfig->Pecstruct.IMCFUNSupportBitMap, FunIndex, ZoneNum); + for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) { + if (IsSendEcMsg) { + WriteECmsg (RegNum, AccWidthUint8, CurPoint); // + } + CurPoint += 1; + } + if (IsSendEcMsg) { + WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &FunNum); // function number + WaitForEcLDN9MailboxCmdAck (); + } + } + } +} + +/*------------------------------------------------------------------------------- +;Procedure: SBIMCFanInitializeS3 +; +;Description: This routine initialize IMC fan when S3 resume +; +; +;Exit: None +; +;Modified: None +; +;----------------------------------------------------------------------------- +*/ +VOID +SBIMCFanInitializeS3 (VOID) +{ + UINT8 dbPortStatus,Value80,Value82,Value83,Value84; + + getChipSysMode (&dbPortStatus); + if ((dbPortStatus & ChipSysEcEnable) != 0) { + Value80 = 0x98; + Value82 = 0x00; + Value83 = 0x02; + Value84 = 0x00; + + // Clear MSG_REG0 to receive acknowledge byte + WriteECmsg (MSG_REG0, AccWidthUint8, &Value82); + + // Set MSG_REG1 + // 0x02 - Notify IMC that the system is waken from any sleep state + WriteECmsg (MSG_REG1, AccWidthUint8, &Value83); + + // Set timeout counter value to 00 which disables watchdog timer + WriteECmsg (MSG_REG2, AccWidthUint8, &Value84); + + // Write mailbox function number to kick off the command + // 0x98 - IMC System Sleep and Wake Services + WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &Value80); + + // Read acknowledge byte to make sure function is executed properly + WaitForEcLDN9MailboxCmdAck (); + } +}
Added: trunk/src/vendorcode/amd/cimx/sb800/GEC.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/GEC.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,135 @@ +/** + * @file + * + * Config Southbridge GEC controller + * + * Init GEC features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: CIMx-SB + * @e sub-project: + * @e $Revision:$ @e $Date:$ + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" + +/** + * gecInitBeforePciEnum - Config GEC controller before PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +gecInitBeforePciEnum ( + IN AMDSBCFG* pConfig + ) +{ + UINT8 cimSBGecDebugBus; + UINT8 cimSBGecPwr; + + cimSBGecDebugBus = (UINT8) pConfig->SBGecDebugBus; + cimSBGecPwr = (UINT8) pConfig->SBGecPwr; +#if SB_CIMx_PARAMETER == 0 + cimSBGecDebugBus = cimSBGecDebugBusDefault; + cimSBGecPwr = cimSBGecPwrDefault; +#endif + if ( pConfig->GecConfig == 0) { + // GEC Enabled + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT0, 0x00); + RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GEVENT_REG11, AccWidthUint8, 0, 0x00); + RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GEVENT_REG21, AccWidthUint8, 0, 0x01); + RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG166, AccWidthUint8, 0, 0x01); + //RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG181, AccWidthUint8, 0, 0x01); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF8, AccWidthUint8, ~(BIT5 + BIT6), (UINT8) ((cimSBGecPwr) << 5)); + } else { + // GEC Disabled + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT0, BIT0); + return; //return if GEC controller is disabled. + } + if ( cimSBGecDebugBus == 1) { + // GEC Debug Bus Enabled + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT3, BIT3); + } else { + // GEC Debug Bus Disabled + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT3, 0x00); + } +} + +/** + * gecInitAfterPciEnum - Config GEC controller after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +gecInitAfterPciEnum ( + IN AMDSBCFG* pConfig + ) +{ + VOID* GecRomAddress; + VOID* GecShadowRomAddress; + UINT32 ddTemp; + UINT8 dbVar; + UINT8 dbTemp; + if ( pConfig->GecConfig == 0) { + dbVar = 0; + ReadPCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG04, AccWidthUint8, &dbVar); + dbTemp = 0x07; + WritePCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG04, AccWidthUint8, &dbTemp); + if ( !pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr == NULL ) { + GecRomAddress = pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr; + GecShadowRomAddress = (VOID*) (UINTN) pConfig->BuildParameters.GecShadowRomBase; + AmdSbCopyMem (GecShadowRomAddress, GecRomAddress, 0x100); + ReadPCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG10, AccWidthUint32, &ddTemp); + ddTemp = ddTemp & 0xFFFFFFF0; + RWMEM (ddTemp + 0x6804, AccWidthUint32, 0, BIT0 + BIT29); + } + WritePCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG04, AccWidthUint8, &dbVar); + } +} + +/** + * gecInitLatePost - Prepare GEC controller to boot to OS. + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +gecInitLatePost ( + IN AMDSBCFG* pConfig + ) +{ + if ( !pConfig->GecConfig == 0) { + return; //return if GEC controller is disabled. + } +} + +
Added: trunk/src/vendorcode/amd/cimx/sb800/Gpp.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/Gpp.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,887 @@ + +/** + * @file + * + * Config Southbridge GPP controller + * + * Init GPP features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: CIMx-SB + * @e sub-project + * @e $Revision:$ @e $Date:$ + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" + +/** + * PCIE_CAP_ID - PCIe Cap ID + * + */ +#define PCIE_CAP_ID 0x10 + +// +// Declaration of local functions +// + +/** + * PreInitGppLink - Enable GPP link training. + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ + VOID PreInitGppLink (IN AMDSBCFG* pConfig); + UINT8 CheckGppLinkStatus (IN AMDSBCFG* pConfig); + VOID AfterGppLinkInit (IN AMDSBCFG* pConfig); + VOID sbGppForceGen2 (IN UINT32 portId ); + VOID sbGppForceGen1 (IN UINT32 portId ); + VOID sbGppDisableUnusedPadMap (IN AMDSBCFG* pConfig ); + VOID sbGppSetAspm (IN UINT32 pciAddress, IN UINT8 LxState); + UINT8 sbFindPciCap (IN UINT32 pciAddress, IN UINT8 targetCapId); + +// +// Declaration of external functions +// + +// +//----------------------------------------------------------------------------------- +// Early SB800 GPP initialization sequence: +// +// 1) Set port enable bit fields by current GPP link configuration mode +// 2) Deassert GPP reset and pull EP out of reset - Clear GPP_RESET (abcfg:0xC0[8] = 0) +// 3) Loop polling for the link status of all ports +// 4) Misc operations after link training: +// - (optional) Detect GFX device +// - Hide empty GPP configuration spaces (Disable empty GPP ports) +// - (optional) Power down unused GPP ports +// - (optional) Configure PCIE_P2P_Int_Map (abcfg:0xC4[7:0]) +// 5) GPP init completed +// +// +// *) Gen2 vs Gen1 +// Gen2 mode Gen1 mode +// --------------------------------------------------------------- +// STRAP_PHY_PLL_CLKF[6:0] 7'h32 7'h19 +// STRAP_BIF_GEN2_EN 1 0 +// +// PCIE_PHY_PLL clock locks @ 5GHz +// +// + +/** + * GPP early programming and link training. On exit all populated EPs should be fully operational. + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +sbPcieGppEarlyInit ( + IN AMDSBCFG* pConfig + ) +{ + UINT8 TogglePort; + UINT8 portNum; + UINT32 reg32Value; + UINT8 retryCount; + UINT8 cimGppMemWrImprove; + UINT8 cimGppLaneReversal; + UINT8 cimAlinkPhyPllPowerDown; + + cimGppMemWrImprove = pConfig->GppMemWrImprove; + cimGppLaneReversal = (UINT8) pConfig->GppLaneReversal; + cimAlinkPhyPllPowerDown = (UINT8) pConfig->AlinkPhyPllPowerDown; +#if SB_CIMx_PARAMETER == 0 + cimGppMemWrImprove = cimGppMemWrImproveDefault; + cimGppLaneReversal = cimGppLaneReversalDefault; + cimAlinkPhyPllPowerDown = cimAlinkPhyPllPowerDownDefault; +#endif + +// +// Configure NB-SB link PCIE PHY PLL power down for L1 +// + if ( cimAlinkPhyPllPowerDown == TRUE ) { + UINT32 abValue; + // Set PCIE_P_CNTL in Alink PCIEIND space + writeAlink (SB_AX_INDXC_REG30 | (UINT32) (AXINDC << 29), 0x40); + abValue = readAlink (SB_AX_DATAC_REG34 | (UINT32) (AXINDC << 29)); + abValue |= BIT12 + BIT3 + BIT0; + abValue &= ~(BIT9 + BIT4); + writeAlink (SB_AX_DATAC_REG34 | (UINT32) (AXINDC << 29), abValue); + rwAlink (SB_AX_INDXC_REG02 | (UINT32) (AXINDC << 29), ~BIT8, (BIT8)); + } + +// +// Set ABCFG 0x031C[0] = 1 enable the lane reversal support. +// + reg32Value = readAlink (SB_ABCFG_REG31C | (UINT32) (ABCFG << 29)); + if ( cimGppLaneReversal ) { + writeAlink (SB_ABCFG_REG31C | (UINT32) (ABCFG << 29), reg32Value | BIT0); + } else { + writeAlink (SB_ABCFG_REG31C | (UINT32) (ABCFG << 29), reg32Value | 0x00); + } +// +// Set abcfg:0x90[20] = 1 to enable GPP bridge multi-function +// + reg32Value = readAlink (SB_ABCFG_REG90 | (UINT32) (ABCFG << 29)); + writeAlink (SB_ABCFG_REG90 | (UINT32) (ABCFG << 29), reg32Value | BIT20); + + +// +// Initialize and configure GPP +// + if (pConfig->GppFunctionEnable) { + // PreInit - Enable GPP link training + PreInitGppLink (pConfig); + +// +// GPP Upstream Memory Write Arbitration Enhancement ABCFG 0x54[26] = 1 +// GPP Memory Write Max Payload Improvement RCINDC_Reg 0x10[12:10] = 0x4 +// + if ( cimGppMemWrImprove == TRUE ) { + rwAlink (SB_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~BIT26, (BIT26)); + rwAlink (SB_RCINDXC_REG10 | (UINT32) (RCINDXC << 29), ~(BIT12 + BIT11 + BIT10), (BIT12)); + } + + if ( pConfig->S3Resume ) { + for ( portNum = 0; portNum < MAX_GPP_PORTS; portNum++ ) { + reg32Value = readAlink ((SB_ABCFG_REG340 + portNum * 4) | (UINT32) (ABCFG << 29)); + writeAlink ((SB_ABCFG_REG340 + portNum * 4) | (UINT32) (ABCFG << 29), reg32Value & ~BIT21); + } + } + // + // a) Loop polling regA5 -> LcState (timeout ~100ms); + // b) if (LcState[5:0] == 0x10), training successful, go to g); + // c) if any of (LcState[13:8], [21:16], [29:24]) == 0x29 or 0x2A: + // d) Clear De-emphasis bit for relevant ports; + // e) Toggle GPP reset signal (via OEM callback); + // f) go back to a); + // g) exit; + // + for (retryCount = 0; retryCount < MAX_GPP_RESETS; retryCount++) { + // Polling each GPP port for link status + TogglePort = CheckGppLinkStatus (pConfig); + + if (TogglePort == 0) { + break; + } else { + // Check failure port and clear STRAP_BIF_DE_EMPHASIS_SEL_x_GPP bit (abcfg:0x34[0, 4, 8, C][21]=0) + for ( portNum = 0; portNum < MAX_GPP_PORTS; portNum++ ) { + if (TogglePort & (1 << portNum)) { + reg32Value = readAlink ((SB_ABCFG_REG340 + portNum * 4) | (UINT32) (ABCFG << 29)); + writeAlink ((SB_ABCFG_REG340 + portNum * 4) | (UINT32) (ABCFG << 29), reg32Value & ~BIT21); + } + sbGppForceGen1 (portNum); + } + + // Toggle GPP reset (Note this affects all SB800 GPP ports) + CallBackToOEM (CB_SBGPP_RESET_ASSERT, (UINT32)TogglePort, pConfig); + SbStall (500); + CallBackToOEM (CB_SBGPP_RESET_DEASSERT, (UINT32)TogglePort, pConfig); + } + }; + + // Misc operations after link training + AfterGppLinkInit (pConfig); + } else { + +// RPR 5.11 Power Saving With GPP Disable +// ABCFG 0xC0[8] = 0x0 +// ABCFG 0xC0[15:12] = 0xF +// Enable "Power Saving Feature for A-Link Express Lanes" +// Enable "Power Saving Feature for GPP Lanes" +// ABCFG 0x90[19] = 1 +// ABCFG 0x90[6] = 1 +// RCINDC_Reg 0x65 [27:0] = 0xFFFFFFF +// ABCFG 0xC0[7:4] = 0x0 + + rwAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), ~BIT8, (BIT4 + BIT5 + BIT6 + BIT7)); + rwAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, (BIT12 + BIT13 + BIT14 + BIT15)); + rwAlink (SB_AX_INDXC_REG40, ~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12)); + rwAlink (RC_INDXC_REG40, ~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12)); + rwAlink ((SB_ABCFG_REG90 | (UINT32) (ABCFG << 29)), 0xFFFFFFFF, (BIT6 + BIT19)); + rwAlink (RC_INDXC_REG65, 0xFFFFFFFF, 0x0fffffff); + rwAlink ((SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29)), ~(BIT4 + BIT5 + BIT6 + BIT7), 0); + } + sbGppDisableUnusedPadMap ( pConfig ); +} + +/** + * PreInitGppLink - Enable GPP link training. + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +PreInitGppLink ( + IN AMDSBCFG* pConfig + ) +{ + UINT8 portMask[5] = {0x01, + 0x00, + 0x03, + 0x07, + 0x0F + }; + UINT8 cfgMode; + UINT8 portId; + UINT32 reg32Value; + UINT16 tmp16Value; + +// PCIE_GPP_ENABLE (abcfg:0xC0): +// +// GPP_LINK_CONFIG ([3:0]) PortA PortB PortC PortD Description +// ---------------------------------------------------------------------------------- +// 0000 0-3 x4 Config +// 0001 N/A +// 0010 0-1 2-3 0 2:2 Config +// 0011 0-1 2 3 2:1:1 Config +// 0100 0 1 2 3 1:1:1:1 Config +// +// For A12 and above: +// ABCFG:0xC0[12] - Port A hold training (default 1) +// ABCFG:0xC0[13] - Port B hold training (default 1) +// ABCFG:0xC0[14] - Port C hold training (default 1) +// ABCFG:0xC0[15] - Port D hold training (default 1) +// +// + // + // Set port enable bit fields based on current GPP link configuration mode + // + cfgMode = (UINT8) pConfig->GppLinkConfig; + if ( cfgMode > GPP_CFGMODE_X1111 || cfgMode == 1 ) { + cfgMode = GPP_CFGMODE_X4000; + pConfig->GppLinkConfig = GPP_CFGMODE_X4000; + } + reg32Value = (UINT32) portMask[cfgMode]; + + // Mask out non-applicable ports according to the target link configuration mode + for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) { + pConfig->PORTCONFIG[portId].PortCfg.PortPresent &= (reg32Value >> portId) & BIT0; + } + + // + // Deassert GPP reset and pull EP out of reset - Clear GPP_RESET (abcfg:0xC0[8] = 0) + // + tmp16Value = (UINT16) (~reg32Value << 12); + reg32Value = (UINT32) (tmp16Value + (reg32Value << 4) + cfgMode); + writeAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), reg32Value); + + reg32Value = readAlink (0xC0 | (UINT32) (RCINDXC << 29)); + writeAlink (0xC0 | (UINT32) (RCINDXC << 29), reg32Value | 0x400); // Set STRAP_F0_MSI_EN + + // A-Link L1 Entry Delay Shortening + // AXINDP_Reg 0xA0[7:4] = 0x3 + rwAlink (SB_AX_INDXP_REGA0, 0xFFFFFF0F, 0x30); + rwAlink (SB_AX_INDXP_REGB1, 0xFFFFFFFF, BIT19); + rwAlink (SB_AX_INDXP_REGB1, 0xFFFFFFFF, BIT28); + + // RPR5.22 GPP L1 Entry Delay Shortening + // RCINDP_Reg 0xA0[7:4] = 0x1 Enter L1 sooner after ACK'ing PM request. + // This is done to reduce number of NAK received with L1 enabled. + for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) { + rwAlink (SB_RCINDXP_REGA0 | portId << 24, 0xFFFFFF0F, 0x10); + } +} + +/** + * CheckGppLinkStatus - loop polling the link status for each GPP port + * + * + * Return: ToggleStatus[3:0] = Port bitmap for those need to clear De-emphasis + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +UINT8 +CheckGppLinkStatus ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 retryCounter; + UINT32 portId; + UINT32 abIndex; + UINT32 Data32; + UINT8 portScanMap; + UINT8 portScanMap2; + UINT8 ToggleStatus; + UINT16 i; + SBGPPPORTCONFIG *portCfg; + + + portScanMap = 0; + retryCounter = MAX_TRAINING_RETRY; + ToggleStatus = 0; + + // Obtain a list of ports to be checked + for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) { + portCfg = &pConfig->PORTCONFIG[portId].PortCfg; + if ( portCfg->PortPresent == TRUE && portCfg->PortDetected == FALSE ) { + portScanMap |= 1 << portId; + } + } + portScanMap2 = portScanMap; + + // + // After training is enabled, Check LCSTATE for each port, if LCSTATE<= 4, then keep + // polling for up to 40ms. If LCSTATE still <= 4, then assume the port to be empty. + // + i = 400; + while ( --i && portScanMap2) { + for (portId = 0; portId < MAX_GPP_PORTS; portId++) { + portCfg = &pConfig->PORTCONFIG[portId].PortCfg; + if (((portCfg->PortHotPlug == FALSE) || ((portCfg->PortHotPlug == TRUE) && (pConfig->S3Resume == FALSE)) ) && (portScanMap2 & (1 << portId))) { + // + // Get port link state (reading LC_CURRENT_STATE of PCIEIND_P) + // + abIndex = SB_RCINDXP_REGA5 | (UINT32) (RCINDXP << 29) | (portId << 24); + Data32 = readAlink (abIndex) & 0x3F; + if ((UINT8) (Data32) > 4) { + portScanMap2 &= ~(1 << portId); // This port is not empty + break; + } + SbStall (100); // Delay 100us + } + } + } + portScanMap &= ~portScanMap2; // Mark remaining ports as empty + + + while ( --retryCounter && portScanMap ) { + for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) { + portCfg = &pConfig->PORTCONFIG[portId].PortCfg; + if (( portCfg->PortHotPlug == TRUE ) && ( pConfig->S3Resume )) { + continue; + } + if ( portCfg->PortPresent == TRUE && portCfg->PortDetected == FALSE ) { + // + // Get port link state (reading LC_CURRENT_STATE of PCIEIND_P) + // + SbStall (1000); // Delay 400us + abIndex = SB_RCINDXP_REGA5 | (UINT32) (RCINDXP << 29) | (portId << 24); + Data32 = readAlink (abIndex) & 0x3F3F3F3F; + + if ( (UINT8) (Data32) == 0x10 ) { + portCfg->PortDetected = TRUE; + portScanMap &= ~(1 << portId); + } else { + for (i = 0; i < 4; i++) { + // + // Compliance mode (0x7), downgrade from Gen2 to Gen1 (*A12) + // + if ((UINT8) (Data32) == 0x29 || (UINT8) (Data32) == 0x2A || (UINT8) (Data32) == 0x7 ) { + ToggleStatus |= (1 << portId); // A11 only: need to toggle GPP reset + portScanMap &= ~(1 << portId); + } + Data32 >>= 8; + } + } + } + } + } + return ToggleStatus; +} + + +/** + * AfterGppLinkInit + * - Search for display device behind each GPP port + * - If the port is empty AND not hotplug-capable: + * * Turn off link training + * * (optional) Power down the port + * * Hide the configuration space (Turn off the port) + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +AfterGppLinkInit ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 portId; + SBGPPPORTCONFIG *portCfg; + UINT32 regBusNumber; + UINT32 abValue; + UINT32 abIndex; + UINT32 i; + UINT32 Data32; + UINT8 bValue; + UINT8 cimGppGen2; + + cimGppGen2 = pConfig->GppGen2; +#if SB_CIMx_PARAMETER == 0 + cimGppGen2 = cimGppGen2Default; +#endif + + bValue = GPP_EFUSE_LOCATION; + getEfuseStatus (&bValue); + if ( (bValue & GPP_GEN2_EFUSE_BIT) != 0 ) { + cimGppGen2 = FALSE; + } else { + pConfig->CoreGen2Enable = TRUE; // Output for platform use + } + +//GPP Gen2 Speed Change +// if ((GPP Gen2 == enabled) and (RCINDP_Reg 0xA4[0] == 0x1)) { +// PCIe_Cfg 0x88[3:0] = 0x2 +// RCINDP_Reg 0xA2[13] = 0x0 +// RCINDP_Reg 0xC0[15] = 0x0 +// RCINDP_Reg 0xA4[29] = 0x1 +// } else { +// PCIe_Cfg 0x88[3:0] = 0x1 +// RCINDP_Reg 0xA4[0] = 0x0 +// RCINDP_Reg 0xA2[13] = 0x1 +// RCINDP_Reg 0xC0[15] = 0x0 +// RCINDP_Reg 0xA4[29] = 0x1 +// } + for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) { + portCfg = &pConfig->PORTCONFIG[portId].PortCfg; + abValue = readAlink (SB_RCINDXP_REGA4 | portId << 24) & BIT0; + if (( cimGppGen2 == TRUE ) && (abValue == BIT0) && (portCfg->PortDetected == TRUE)) { + portCfg->PortIsGen2 = TRUE; // Output for platform use + sbGppForceGen2 (portId); + //_asm {jmp $}; + SbStall (400); // Delay 400us + i = 500; + Data32 = 0; + while ( --i ) { + abIndex = SB_RCINDXP_REGA5 | (UINT32) (RCINDXP << 29) | (portId << 24); + Data32 = readAlink (abIndex) & 0x3F; + if ((UINT8) (Data32) == 0x10) { + break; + } + SbStall (400); // Delay 100us + } + if (!( (UINT8) (Data32) == 0x10 )) { + if (pConfig->GppCompliance == FALSE) { + portCfg->PortIsGen2 = FALSE; // Revert to default; output for platform use + sbGppForceGen1 (portId); + } + } + } else { + if (pConfig->GppCompliance == FALSE) { + sbGppForceGen1 (portId); + } + } +//RPR 5.9 Link Bandwidth Notification Capability Enable +//RCINDC 0xC1[0] = 1 +//PCIe Cfg 0x68[10] = 0 +//PCIe Cfg 0x68[11] = 0 + + rwAlink (SB_RCINDXC_REGC1, 0xFFFFFFFF, BIT0); + RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x68), AccWidthUint16, ~(BIT10 + BIT11), 0); + } + +// Status = AGESA_SUCCESS; + pConfig->GppFoundGfxDev = 0; + abValue = readAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29)); + + for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) { + portCfg = &pConfig->PORTCONFIG[portId].PortCfg; + // Check if there is GFX device behind each GPP port + if ( portCfg->PortDetected == TRUE ) { + regBusNumber = (SBTEMP_BUS << 16) + (SBTEMP_BUS << 8); + WritePCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x18), AccWidthUint32, ®BusNumber); + // *** Stall (); + ReadPCI (PCI_ADDRESS (SBTEMP_BUS, 0, 0, 0x0B), AccWidthUint8, &bValue); + if ( bValue == 3 ) { + pConfig->GppFoundGfxDev |= (1 << portId); + } + regBusNumber = 0; + WritePCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x18), AccWidthUint32, ®BusNumber); + } + + // Mask off non-applicable ports + else if ( portCfg->PortPresent == FALSE ) { + abValue &= ~(1 << (portId + 4)); + } + // Mask off empty port if the port is not hotplug-capable + else if ( portCfg->PortHotPlug == FALSE ) { + abValue &= ~(1 << (portId + 4)); + } + // Clear STRAP_BIF_DE_EMPHASIS_SEL_x_GPP bit (abcfg:0x34[0, 4, 8, C][21]=0) to make hotplug working + if ( portCfg->PortHotPlug == TRUE ) { + rwAlink ((SB_ABCFG_REG340 + portId * 4) | (UINT32) (ABCFG << 29), ~BIT21, 0); + +// RPR5.12 Hot Plug: PCIe Native Support +// RCINDP_Reg 0x10[3] = 0x1 +// PCIe_Cfg 0x5A[8] = 0x1 +// PCIe_Cfg 0x6C[6] = 0x1 +// RCINDP_Reg 0x20[19] = 0x0 + + rwAlink ((SB_RCINDXP_REG10 | (UINT32) (RCINDXP << 29) | (portId << 24)), 0xFFFFFFFF, BIT3); + RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x5b), AccWidthUint8, 0xff, BIT0); + RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x6c), AccWidthUint8, 0xff, BIT6); + rwAlink ((SB_RCINDXP_REG20 | (UINT32) (RCINDXP << 29) | (portId << 24)), ~BIT19, 0); + } + } + if ( pConfig->GppUnhidePorts == FALSE ) { + if ((abValue & 0xF0) == 0) { + abValue = BIT8; // if all ports are empty set GPP_RESET + } else if ((abValue & 0xE0) != 0 && (abValue & 0x10) == 0) { + abValue |= BIT4; // PortA should always be visible whenever other ports are exist + } + + // Update GPP_Portx_Enable (abcfg:0xC0[7:5]) + writeAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), abValue); + } + + // + // Common initialization for open GPP ports + // + for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) { + ReadPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x80), AccWidthUint8, &bValue); + if (bValue != 0xff) { + // Set pciCfg:PCIE_DEVICE_CNTL2[3:0] = 4'h6 (0x80[3:0]) + bValue &= 0xf0; + bValue |= 0x06; + WritePCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x80), AccWidthUint8, &bValue); + + // Set PCIEIND_P:PCIE_RX_CNTL[RX_RCB_CPL_TIMEOUT_MODE] (0x70:[19]) = 1 + abIndex = SB_RCINDXP_REG70 | (UINT32) (RCINDXP << 29) | (portId << 24); + abValue = readAlink (abIndex) | BIT19; + writeAlink (abIndex, abValue); + + // Set PCIEIND_P:PCIE_TX_CNTL[TX_FLUSH_TLP_DIS] (0x20:[19]) = 0 + abIndex = SB_RCINDXP_REG20 | (UINT32) (RCINDXP << 29) | (portId << 24); + abValue = readAlink (abIndex) & ~BIT19; + writeAlink (abIndex, abValue); + + } + } +} + + +/** + * sbPcieGppLateInit - Late PCIE initialization for SB800 GPP component + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +sbPcieGppLateInit ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 reg32Value; + UINT8 portId; + UINT8 busNum; + UINT8 aspmValue; + UINT8 reg8Value; + UINT8 cimGppPhyPllPowerDown; + + reg8Value = 0x01; +// +// Configure ASPM +// +// writeAlink (0xC0 | (UINT32) (RCINDXC << 29), 0x400); // Set STRAP_F0_MSI_EN + aspmValue = (UINT8)pConfig->GppPortAspm; + cimGppPhyPllPowerDown = (UINT8) pConfig->GppPhyPllPowerDown; +#if SB_CIMx_PARAMETER == 0 + aspmValue = cimGppPortAspmDefault; + cimGppPhyPllPowerDown = cimGppPhyPllPowerDownDefault; +#endif + + for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) { + // write pci_reg3d with 0x01 to fix yellow mark for GPP bridge under Vista + // when native PCIE is enabled but MSI is not available + // SB02029: SB800 BIF/GPP allowing strap STRAP_BIF_INTERRUPT_PIN_SB controlled by AB reg + WritePCI (PCI_ADDRESS (0, 21, portId, 0x3d), AccWidthUint8, ®8Value); + ReadPCI (PCI_ADDRESS (0, 21, portId, 0x19), AccWidthUint8, &busNum); + if (busNum != 0xFF) { + ReadPCI (PCI_ADDRESS (busNum, 0, 0, 0x00), AccWidthUint32, ®32Value); + if (reg32Value != 0xffffffff) { + // Set ASPM on EP side + sbGppSetAspm (PCI_ADDRESS (busNum, 0, 0, 0), aspmValue & 0x3); + // Set ASPM on port side + sbGppSetAspm (PCI_ADDRESS (0, 21, portId, 0), aspmValue & 0x3); + } + } + aspmValue = aspmValue >> 2; + } + +// +// Configure Lock HWInit registers +// + reg32Value = readAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29)); + if (reg32Value & 0xF0) { + reg32Value = readAlink (SB_RCINDXC_REG10 | (UINT32) (RCINDXC << 29)); + writeAlink (SB_RCINDXC_REG10 | (UINT32) (RCINDXC << 29), reg32Value | BIT0); // Set HWINIT_WR_LOCK + + if ( cimGppPhyPllPowerDown == TRUE ) { +// +// RPR 5.4 Power Saving Feature for GPP Lanes +// + UINT32 abValue; + // Set PCIE_P_CNTL in Alink PCIEIND space + abValue = readAlink (RC_INDXC_REG40 | (UINT32) (RCINDXC << 29)); + abValue |= BIT12 + BIT3 + BIT0; + abValue &= ~(BIT9 + BIT4); + writeAlink (RC_INDXC_REG40 | (UINT32) (RCINDXC << 29), abValue); + } + } + +// +// Configure Lock HWInit registers +// + reg32Value = readAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29)); +// +// Disable hidden register decode and serial number capability +// + reg32Value = readAlink (SB_ABCFG_REG330 | (UINT32) (ABCFG << 29)); + writeAlink (SB_ABCFG_REG330 | (UINT32) (ABCFG << 29), reg32Value & ~(BIT26 + BIT10)); +} + +/** + * sbGppSetAspm - Set SPP ASPM + * + * + * @param[in] pciAddress PCI Address. + * @param[in] LxState Lane State. + * + */ +VOID +sbGppSetAspm ( + IN UINT32 pciAddress, + IN UINT8 LxState + ) +{ + UINT8 pcieCapOffset; + UINT8 value8; + UINT8 maxFuncs; + UINT32 devBDF; + + maxFuncs = 1; + ReadPCI (pciAddress + 0x0E, AccWidthUint8, &value8); + + if (value8 & BIT7) { + maxFuncs = 8; // multi-function device + } + while (maxFuncs != 0) { + devBDF = pciAddress + (UINT32) ((maxFuncs - 1) << 16); + pcieCapOffset = sbFindPciCap (devBDF, PCIE_CAP_ID); + if (pcieCapOffset) { + // Read link capabilities register (0x0C[11:10] - ASPM support) + ReadPCI (devBDF + pcieCapOffset + 0x0D, AccWidthUint8, &value8); + if (value8 & BIT2) { + value8 = (value8 >> 2) & (BIT1 + BIT0); + // Set ASPM state in link control register + RWPCI (devBDF + pcieCapOffset + 0x10, AccWidthUint8, 0xffffffff, LxState & value8); + } + } + maxFuncs--; + } +} + +/** + * sbFindPciCap - Find PCI Cap + * + * + * @param[in] pciAddress PCI Address. + * @param[in] targetCapId Target Cap ID. + * + */ +UINT8 +sbFindPciCap ( + IN UINT32 pciAddress, + IN UINT8 targetCapId + ) +{ + UINT8 NextCapPtr; + UINT8 CapId; + + NextCapPtr = 0x34; + while (NextCapPtr != 0) { + ReadPCI (pciAddress + NextCapPtr, AccWidthUint8, &NextCapPtr); + if (NextCapPtr == 0xff) { + return 0; + } + if (NextCapPtr != 0) { + ReadPCI (pciAddress + NextCapPtr, AccWidthUint8, &CapId); + if (CapId == targetCapId) { + break; + } else { + NextCapPtr++; + } + } + } + return NextCapPtr; +} + +/** + * sbGppForceGen2 - Set SPP to GENII + * + * + * @param[in] portId + * + */ +VOID +sbGppForceGen2 ( + IN UINT32 portId + ) +{ + RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x88), AccWidthUint8, 0xf0, 0x02); + rwAlink (SB_RCINDXP_REGA2 | portId << 24, ~BIT13, 0); + rwAlink (SB_RCINDXP_REGC0 | portId << 24, ~BIT15, 0); + rwAlink (SB_RCINDXP_REGA4 | portId << 24, 0xFFFFFFFF, BIT29); +} + +/** + * sbGppForceGen1 - Set SPP to GENI + * + * + * @param[in] portId + * + */ +VOID +sbGppForceGen1 ( + IN UINT32 portId + ) +{ + RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x88), AccWidthUint8, 0xf0, 0x01); + rwAlink (SB_RCINDXP_REGA4 | portId << 24, ~BIT0, 0); + rwAlink (SB_RCINDXP_REGA2 | portId << 24, 0xFFFFFFFF, BIT13); + rwAlink (SB_RCINDXP_REGC0 | portId << 24, ~BIT15, 0); + rwAlink (SB_RCINDXP_REGA4 | portId << 24, 0xFFFFFFFF, BIT29); +} + +/** + * sbGppDisableUnusedPadMap - Return GPP Pad Map + * + * + * @param[in] pConfig + * + */ +VOID +sbGppDisableUnusedPadMap ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 Data32; + UINT32 HoldData32; + SBGPPPORTCONFIG *portCfg; + UINT8 cimGppLaneReversal; + UINT8 cimAlinkPhyPllPowerDown; + UINT8 cimGppPhyPllPowerDown; + + cimAlinkPhyPllPowerDown = (UINT8) pConfig->AlinkPhyPllPowerDown; + cimGppLaneReversal = (UINT8) pConfig->GppLaneReversal; + cimGppPhyPllPowerDown = (UINT8) pConfig->GppPhyPllPowerDown; +#if SB_CIMx_PARAMETER == 0 + cimGppLaneReversal = cimGppLaneReversalDefault; + cimAlinkPhyPllPowerDown = cimAlinkPhyPllPowerDownDefault; + cimGppPhyPllPowerDown = cimGppPhyPllPowerDownDefault; +#endif + + Data32 = 0; + HoldData32 = 0; + switch ( pConfig->GppLinkConfig ) { + case GPP_CFGMODE_X4000: + portCfg = &pConfig->PORTCONFIG[0].PortCfg; + if ( portCfg->PortDetected == FALSE ) { + Data32 |= 0x0f0f; + HoldData32 |= 0x1000; + } + break; + case GPP_CFGMODE_X2200: + portCfg = &pConfig->PORTCONFIG[0].PortCfg; + if ( portCfg->PortDetected == FALSE ) { + Data32 |= ( cimGppLaneReversal )? 0x0c0c:0x0303; + HoldData32 |= 0x1000; + } + portCfg = &pConfig->PORTCONFIG[1].PortCfg; + if ( portCfg->PortDetected == FALSE ) { + Data32 |= ( cimGppLaneReversal )? 0x0303:0x0c0c; + HoldData32 |= 0x2000; + } + break; + case GPP_CFGMODE_X2110: + portCfg = &pConfig->PORTCONFIG[0].PortCfg; + if ( portCfg->PortDetected == FALSE ) { + Data32 |= ( cimGppLaneReversal )? 0x0c0c:0x0303; + HoldData32 |= 0x1000; + } + portCfg = &pConfig->PORTCONFIG[1].PortCfg; + if ( portCfg->PortDetected == FALSE ) { + Data32 |= ( cimGppLaneReversal )? 0x0202:0x0404; + HoldData32 |= 0x2000; + } + portCfg = &pConfig->PORTCONFIG[2].PortCfg; + if ( portCfg->PortDetected == FALSE ) { + Data32 |= ( cimGppLaneReversal )? 0x0101:0x0808; + HoldData32 |= 0x4000; + } + break; + case GPP_CFGMODE_X1111: + portCfg = &pConfig->PORTCONFIG[0].PortCfg; + if ( portCfg->PortDetected == FALSE ) { + Data32 |= ( cimGppLaneReversal )? 0x0808:0x0101; + HoldData32 |= 0x1000; + } + portCfg = &pConfig->PORTCONFIG[1].PortCfg; + if ( portCfg->PortDetected == FALSE ) { + Data32 |= ( cimGppLaneReversal )? 0x0404:0x0202; + HoldData32 |= 0x2000; + } + portCfg = &pConfig->PORTCONFIG[2].PortCfg; + if ( portCfg->PortDetected == FALSE ) { + Data32 |= ( cimGppLaneReversal )? 0x0202:0x0404; + HoldData32 |= 0x4000; + } + portCfg = &pConfig->PORTCONFIG[3].PortCfg; + if ( portCfg->PortDetected == FALSE ) { + Data32 |= ( cimGppLaneReversal )? 0x0101:0x0808; + HoldData32 |= 0x8000; + } + break; + default: + break; + } + +// RPR 5.11 Power Saving With GPP Disable +// ABCFG 0xC0[8] = 0x0 +// ABCFG 0xC0[15:12] = 0xF +// Enable "Power Saving Feature for A-Link Express Lanes" +// Enable "Power Saving Feature for GPP Lanes" +// ABCFG 0x90[19] = 1 +// ABCFG 0x90[6] = 1 +// RCINDC_Reg 0x65 [27:0] = 0xFFFFFFF +// ABCFG 0xC0[7:4] = 0x0 + if ( (Data32 & 0xf) == 0xf ) Data32 |= 0x0cff0000; + if ( cimAlinkPhyPllPowerDown && cimGppPhyPllPowerDown ) { + rwAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), ~BIT8, 0); + rwAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, HoldData32); + rwAlink (SB_AX_INDXC_REG40, ~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12)); + rwAlink (RC_INDXC_REG40, ~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12)); + rwAlink ((SB_ABCFG_REG90 | (UINT32) (ABCFG << 29)), 0xFFFFFFFF, (BIT6 + BIT19)); + rwAlink (RC_INDXC_REG65, 0xFFFFFFFF, Data32); + } +}
Added: trunk/src/vendorcode/amd/cimx/sb800/IOLIB.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/IOLIB.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,81 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" + + +VOID +ReadIO ( + IN UINT16 Address, + IN UINT8 OpFlag, + IN VOID* Value + ) +{ + OpFlag = OpFlag & 0x7f; + switch ( OpFlag ) { + case AccWidthUint8: + *(UINT8*)Value = ReadIo8 (Address); + break; + case AccWidthUint16: + *(UINT16*)Value = ReadIo16 (Address); + break; + case AccWidthUint32: + *(UINT32*)Value = ReadIo32 (Address); + break; + } +} + +VOID +WriteIO ( + IN UINT16 Address, + IN UINT8 OpFlag, + IN VOID* Value + ) +{ + OpFlag = OpFlag & 0x7f; + switch ( OpFlag ) { + case AccWidthUint8: + WriteIo8 (Address, *(UINT8*)Value); + break; + case AccWidthUint16: + WriteIo16 (Address, *(UINT16*)Value); + break; + case AccWidthUint32: + WriteIo32 (Address, *(UINT32*)Value); + break; + } +} + +VOID +RWIO ( + IN UINT16 Address, + IN UINT8 OpFlag, + IN UINT32 Mask, + IN UINT32 Data + ) +{ + UINT32 Result; + ReadIO (Address, OpFlag, &Result); + Result = (Result & Mask) | Data; + WriteIO (Address, OpFlag, &Result); +}
Added: trunk/src/vendorcode/amd/cimx/sb800/LEGACY.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/LEGACY.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,37 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" + +UINT32 +GetFixUp ( + OUT VOID + ) +{ + AMD_CONFIG_PARAMS* Result; + Result = (AMD_CONFIG_PARAMS*) getConfigPointer (); + if ( Result->ImageBasePtr > 0x100000 && Result->ImageBasePtr < 0xFF000000 ) { + return 0; + } + return Result->ImageBasePtr; +}
Added: trunk/src/vendorcode/amd/cimx/sb800/MEMLIB.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/MEMLIB.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,86 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" + +VOID +ReadMEM ( + IN UINT32 Address, + IN UINT8 OpFlag, + IN VOID* Value + ) +{ + OpFlag = OpFlag & 0x7f; + switch ( OpFlag ) { + case AccWidthUint8: + *((UINT8*)Value) = *((UINT8*) ((UINTN)Address)); + break; + case AccWidthUint16: + //*((UINT16*)Value) = *((UINT16*) ((UINTN)Address)); //gcc break strict-aliasing rules + *((UINT8*)Value) = *((UINT8*) ((UINTN)Address)); + *((UINT8*)Value + 1) = *((UINT8*)((UINTN)Address) + 1); + break; + case AccWidthUint32: + *((UINT32*)Value) = *((UINT32*) ((UINTN)Address)); + break; + } +} + +VOID +WriteMEM ( + IN UINT32 Address, + IN UINT8 OpFlag, + IN VOID* Value + ) +{ + OpFlag = OpFlag & 0x7f; + switch ( OpFlag ) { + case AccWidthUint8 : + *((UINT8*) ((UINTN)Address)) = *((UINT8*)Value); + break; + case AccWidthUint16: + //*((UINT16*) ((UINTN)Address)) = *((UINT16*)Value); //gcc break strict-aliasing rules + *((UINT8*)((UINTN)Address)) = *((UINT8*)Value); + *((UINT8*)((UINTN)Address) + 1) = *((UINT8*)Value + 1); + break; + case AccWidthUint32: + *((UINT32*) ((UINTN)Address)) = *((UINT32*)Value); + break; + } +} + +VOID +RWMEM ( + IN UINT32 Address, + IN UINT8 OpFlag, + IN UINT32 Mask, + IN UINT32 Data + ) +{ + UINT32 Result; + ReadMEM (Address, OpFlag, &Result); + Result = (Result & Mask) | Data; + WriteMEM (Address, OpFlag, &Result); +} + +
Added: trunk/src/vendorcode/amd/cimx/sb800/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/Makefile.inc Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,75 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2010 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +# CIMX Root directory +CIMX_ROOT = src/vendorcode/amd/cimx + +CIMX_INC = -I$(src)/mainboard/$(MAINBOARDDIR) +CIMX_INC += -I$(src)/southbridge/amd/cimx_wrapper/sb800 +CIMX_INC += -I$(CIMX_ROOT)/sb800 +#TODO merge withagesa lib functions +CIMX_INC += -I$(CIMX_ROOT)/lib + +# CIMX LIB files +romstage-y += MEMLIB.c +romstage-y += PCILIB.c +romstage-y += IOLIB.c +romstage-y += PMIOLIB.c +romstage-y += AMDLIB.c +romstage-y += SBPELIB.c +romstage-y += AMDSBLIB.c +romstage-y += SBPOR.c +romstage-y += ECLIB.c +romstage-y += EC.c +ramstage-y += DISPATCHER.c + +ramstage-y += ACPILIB.c +ramstage-y += AZALIA.c +ramstage-y += DISPATCHER.c +ramstage-y += ECfanc.c +ramstage-y += ECfanLIB.c +ramstage-y += GEC.c +ramstage-y += Gpp.c +ramstage-y += PMIO2LIB.c +ramstage-y += SATA.c +ramstage-y += SBCMN.c +ramstage-y += SBMAIN.c +ramstage-y += SBPOR.c +ramstage-y += MEMLIB.c +ramstage-y += PCILIB.c +ramstage-y += IOLIB.c +ramstage-y += PMIOLIB.c +ramstage-y += AMDLIB.c +ramstage-y += SBPELIB.c +ramstage-y += AMDSBLIB.c +ramstage-y += ECLIB.c +ramstage-y += EC.c +ramstage-y += SMM.c +ramstage-y += USB.c +#ramstage-y += LEGACY.c +#ramstage-y += SbModInf.c + +CIMX_CFLAGS = +export CIMX_ROOT +export CIMX_INC +export CIMX_CFLAGS +CC := $(CC) $(CIMX_INC) + +####################################################################### +
Added: trunk/src/vendorcode/amd/cimx/sb800/OEM.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/OEM.h Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,274 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#define BIOS_SIZE 0x04 //04 - 1MB +#define LEGACY_FREE 0x00 +#define ACPI_SLEEP_TRAP 0x01 +//#define SPREAD_SPECTRUM_EPROM_LOAD 0x01 + +/** + * Module Specific Defines for platform BIOS + * + */ + +/** + * PCIEX_BASE_ADDRESS - Define PCIE base address + * + * @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000 + */ +#ifdef MOVE_PCIEBAR_TO_F0000000 + #define PCIEX_BASE_ADDRESS 0xF7000000 +#else + #define PCIEX_BASE_ADDRESS 0xE0000000 +#endif + +/** + * SMBUS0_BASE_ADDRESS - Smbus base address + * + */ +#ifndef SMBUS0_BASE_ADDRESS + #define SMBUS0_BASE_ADDRESS 0xB00 +#endif + +/** + * SMBUS1_BASE_ADDRESS - Smbus1 (ASF) base address + * + */ +#ifndef SMBUS1_BASE_ADDRESS + #define SMBUS1_BASE_ADDRESS 0xB20 +#endif + +/** + * GEC_BASE_ADDRESS - Gec Shadow ROM base address + * + */ +#ifndef GEC_BASE_ADDRESS + #define GEC_BASE_ADDRESS 0xFED61000 +#endif + + +/** + * SIO_PME_BASE_ADDRESS - Super IO PME base address + * + */ +#ifndef SIO_PME_BASE_ADDRESS + #define SIO_PME_BASE_ADDRESS 0xE00 +#endif + +/** + * SPI_BASE_ADDRESS - SPI controller (ROM) base address + * + */ +#ifndef SPI_BASE_ADDRESS + #define SPI_BASE_ADDRESS 0xFEC10000 +#endif + +/** + * WATCHDOG_TIMER_BASE_ADDRESS - WATCHDOG timer base address + * + */ +#ifndef WATCHDOG_TIMER_BASE_ADDRESS + #define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 // Watchdog Timer Base Address +#endif + +/** + * HPET_BASE_ADDRESS - HPET base address + * + */ +#ifndef HPET_BASE_ADDRESS + #define HPET_BASE_ADDRESS 0xFED00000 // HPET Base address +#endif + +/** + * ALT_ADDR_400 - For some BIOS codebases which use 0x400 as ACPI base address + * + */ +#ifdef ALT_ADDR_400 + #define ACPI_BLK_BASE 0x400 +#else + #define ACPI_BLK_BASE 0x800 +#endif + +#define PM1_STATUS_OFFSET 0x00 +#define PM1_ENABLE_OFFSET 0x02 +#define PM1_CONTROL_OFFSET 0x04 +#define PM_TIMER_OFFSET 0x08 +#define CPU_CONTROL_OFFSET 0x10 +#define EVENT_STATUS_OFFSET 0x20 +#define EVENT_ENABLE_OFFSET 0x24 + +/** + * PM1_EVT_BLK_ADDRESS - ACPI power management Event Block base address + * + */ +#define PM1_EVT_BLK_ADDRESS ACPI_BLK_BASE + PM1_STATUS_OFFSET // AcpiPm1EvtBlkAddr + +/** + * PM1_CNT_BLK_ADDRESS - ACPI power management Control block base address + * + */ +#define PM1_CNT_BLK_ADDRESS ACPI_BLK_BASE + PM1_CONTROL_OFFSET // AcpiPm1CntBlkAddr + +/** + * PM1_TMR_BLK_ADDRESS - ACPI power management Timer block base address + * + */ +#define PM1_TMR_BLK_ADDRESS ACPI_BLK_BASE + PM_TIMER_OFFSET // AcpiPmTmrBlkAddr + +/** + * CPU_CNT_BLK_ADDRESS - ACPI power management CPU Control block base address + * + */ +#define CPU_CNT_BLK_ADDRESS ACPI_BLK_BASE + CPU_CONTROL_OFFSET // CpuControlBlkAddr + +/** + * GPE0_BLK_ADDRESS - ACPI power management General Purpose Event block base address + * + */ +#define GPE0_BLK_ADDRESS ACPI_BLK_BASE + EVENT_STATUS_OFFSET // AcpiGpe0BlkAddr + +/** + * SMI_CMD_PORT - ACPI SMI Command block base address + * + */ +#define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr + +/** + * ACPI_PMA_CNT_BLK_ADDRESS - ACPI power management additional control block base address + * + */ +#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr + +/** + * SATA_IDE_MODE_SSID - Sata controller IDE mode SSID. + * Define value for SSID while SATA controller set to IDE mode. + */ +#ifndef SATA_IDE_MODE_SSID + #define SATA_IDE_MODE_SSID 0x43901002 +#endif + +/** + * SATA_RAID_MODE_SSID - Sata controller RAID mode SSID. + * Define value for SSID while SATA controller set to RAID mode. + */ +#ifndef SATA_RAID_MODE_SSID + #define SATA_RAID_MODE_SSID 0x43921002 +#endif + +/** + * SATA_RAID5_MODE_SSID - Sata controller RAID5 mode SSID. + * Define value for SSID while SATA controller set to RAID5 mode. + */ +#ifndef SATA_RAID5_MODE_SSID + #define SATA_RAID5_MODE_SSID 0x43931002 +#endif + +/** + * SATA_AHCI_MODE_SSID - Sata controller AHCI mode SSID. + * Define value for SSID while SATA controller set to AHCI mode. + */ +#ifndef SATA_AHCI_SSID + #define SATA_AHCI_SSID 0x43911002 +#endif + +/** + * OHCI_SSID - All SB OHCI controllers SSID value. + * + */ +#ifndef OHCI_SSID + #define OHCI_SSID 0x43971002 +#endif + +/** + * EHCI_SSID - All SB EHCI controllers SSID value. + * + */ +#ifndef EHCI_SSID + #define EHCI_SSID 0x43961002 +#endif + +/** + * OHCI4_SSID - OHCI (USB 1.1 mode *HW force) controllers SSID value. + * + */ +#ifndef OHCI4_SSID + #define OHCI4_SSID 0x43991002 +#endif + +/** + * SMBUS_SSID - Smbus controller (South Bridge device 0x14 function 0) SSID value. + * + */ +#ifndef SMBUS_SSID + #define SMBUS_SSID 0x43851002 +#endif + +/** + * IDE_SSID - SATA IDE controller (South Bridge device 0x14 function 1) SSID value. + * + */ +#ifndef IDE_SSID + #define IDE_SSID 0x439C1002 +#endif + +/** + * AZALIA_SSID - AZALIA controller (South Bridge device 0x14 function 2) SSID value. + * + */ +#ifndef AZALIA_SSID + #define AZALIA_SSID 0x43831002 +#endif + +/** + * LPC_SSID - LPC controller (South Bridge device 0x14 function 3) SSID value. + * + */ +#ifndef LPC_SSID + #define LPC_SSID 0x439D1002 +#endif + +/** + * PCIB_SSID - PCIB controller (South Bridge device 0x14 function 4) SSID value. + * + */ +#ifndef PCIB_SSID + #define PCIB_SSID 0x43841002 +#endif + +/** + * USB_PLL_Voltage - CG2 Clock voltage setting. + * + */ +#ifndef USB_PLL_Voltage + #define USB_PLL_Voltage 0x10 +#endif + +/** + * Spread_Spectrum_Type + * + * - 0 : Normal platform + * - 1 : Ontario platform + */ +#ifndef Spread_Spectrum_Type + #define Spread_Spectrum_Type 0x00 +#endif
Added: trunk/src/vendorcode/amd/cimx/sb800/PCILIB.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/PCILIB.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,76 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + + +#include "SBPLATFORM.h" + +VOID +ReadPCI ( + IN UINT32 Address, + IN UINT8 OpFlag, + IN VOID* Value + ) +{ + OpFlag = OpFlag & 0x7f; + + if ( (UINT16)Address < 0xff ) { + //Normal Config Access + UINT32 AddrCf8; + AddrCf8 = (1 << 31) + ((Address >> 8) & 0x0FFFF00) + (Address & 0xFC); + WriteIO (0xCf8, AccWidthUint32, &AddrCf8); + ReadIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value); + } +} + +VOID +WritePCI ( + IN UINT32 Address, + IN UINT8 OpFlag, + IN VOID* Value + ) +{ + OpFlag = OpFlag & 0x7f; + if ( (UINT16)Address < 0xff ) { + //Normal Config Access + UINT32 AddrCf8; + AddrCf8 = (1 << 31) + ((Address >> 8)&0x0FFFF00) + (Address & 0xFC); + WriteIO (0xCf8, AccWidthUint32, &AddrCf8); + WriteIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value); + } +} + +VOID +RWPCI ( + IN UINT32 Address, + IN UINT8 OpFlag, + IN UINT32 Mask, + IN UINT32 Data + ) +{ + UINT32 Result; + Result = 0; + OpFlag = OpFlag & 0x7f; + ReadPCI (Address, OpFlag, &Result); + Result = (Result & Mask) | Data; + WritePCI (Address, OpFlag, &Result); +}
Added: trunk/src/vendorcode/amd/cimx/sb800/PMIO2LIB.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/PMIO2LIB.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,120 @@ +/** + * @file + * + * Southbridge PMIO2 access common routine + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" + + +/*----------------------------------------------------------------------------------------*/ +/** + * Read PMIO2 + * + * + * + * @param[in] Address - PMIO2 Offset value + * @param[in] OpFlag - Access sizes + * @param[in] Value - Read Data Buffer + * + */ +VOID +ReadPMIO2 ( + IN UINT8 Address, + IN UINT8 OpFlag, + IN VOID* Value + ) +{ + UINT8 i; + OpFlag = OpFlag & 0x7f; + + if ( OpFlag == 0x02 ) { + OpFlag = 0x03; + } + for ( i = 0; i <= OpFlag; i++ ) { + WriteIO (0xCD0, AccWidthUint8, &Address); // SB_IOMAP_REGCD0 + Address++; + ReadIO (0xCD1, AccWidthUint8, (UINT8 *) Value + i); // SB_IOMAP_REGCD1 + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Write PMIO 2 + * + * + * + * @param[in] Address - PMIO2 Offset value + * @param[in] OpFlag - Access sizes + * @param[in] Value - Write Data Buffer + * + */ +VOID +WritePMIO2 ( + IN UINT8 Address, + IN UINT8 OpFlag, + IN VOID* Value + ) +{ + UINT8 i; + OpFlag = OpFlag & 0x7f; + + if ( OpFlag == 0x02 ) { + OpFlag = 0x03; + } + for ( i = 0; i <= OpFlag; i++ ) { + WriteIO (0xCD0, AccWidthUint8, &Address); // SB_IOMAP_REGCD0 + Address++; + WriteIO (0xCD1, AccWidthUint8, (UINT8 *)Value + i); // SB_IOMAP_REGCD1 + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * RWPMIO2 - Read/Write PMIO2 + * + * + * + * @param[in] Address - PMIO2 Offset value + * @param[in] OpFlag - Access sizes + * @param[in] AndMask - Data And Mask 32 bits + * @param[in] OrMask - Data OR Mask 32 bits + * + */ +VOID +RWPMIO2 ( + IN UINT8 Address, + IN UINT8 OpFlag, + IN UINT32 AndMask, + IN UINT32 OrMask + ) +{ + UINT32 Result; + OpFlag = OpFlag & 0x7f; + ReadPMIO2 (Address, OpFlag, &Result); + Result = (Result & AndMask) | OrMask; + WritePMIO2 (Address, OpFlag, &Result); +}
Added: trunk/src/vendorcode/amd/cimx/sb800/PMIOLIB.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/PMIOLIB.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,119 @@ +/** + * @file + * + * Southbridge PMIO access common routine + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" + +/*----------------------------------------------------------------------------------------*/ +/** + * Read PMIO + * + * + * + * @param[in] Address - PMIO Offset value + * @param[in] OpFlag - Access sizes + * @param[in] Value - Read Data Buffer + * + */ +VOID +ReadPMIO ( + IN UINT8 Address, + IN UINT8 OpFlag, + IN VOID* Value + ) +{ + UINT8 i; + OpFlag = OpFlag & 0x7f; + + if ( OpFlag == 0x02 ) { + OpFlag = 0x03; + } + for ( i = 0; i <= OpFlag; i++ ) { + WriteIO (0xCD6, AccWidthUint8, &Address); // SB_IOMAP_REGCD6 + Address++; + ReadIO (0xCD7, AccWidthUint8, (UINT8 *)Value + i); // SB_IOMAP_REGCD7 + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Write PMIO + * + * + * + * @param[in] Address - PMIO Offset value + * @param[in] OpFlag - Access sizes + * @param[in] Value - Write Data Buffer + * + */ +VOID +WritePMIO ( + IN UINT8 Address, + IN UINT8 OpFlag, + IN VOID* Value + ) +{ + UINT8 i; + OpFlag = OpFlag & 0x7f; + + if ( OpFlag == 0x02 ) { + OpFlag = 0x03; + } + for ( i = 0; i <= OpFlag; i++ ) { + WriteIO (0xCD6, AccWidthUint8, &Address); // SB_IOMAP_REGCD6 + Address++; + WriteIO (0xCD7, AccWidthUint8, (UINT8 *)Value + i); // SB_IOMAP_REGCD7 + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * RWPMIO - Read/Write PMIO + * + * + * + * @param[in] Address - PMIO Offset value + * @param[in] OpFlag - Access sizes + * @param[in] AndMask - Data And Mask 32 bits + * @param[in] OrMask - Data OR Mask 32 bits + * + */ +VOID +RWPMIO ( + IN UINT8 Address, + IN UINT8 OpFlag, + IN UINT32 AndMask, + IN UINT32 OrMask + ) +{ + UINT32 Result; + OpFlag = OpFlag & 0x7f; + ReadPMIO (Address, OpFlag, &Result); + Result = (Result & AndMask) | OrMask; + WritePMIO (Address, OpFlag, &Result); +}
Added: trunk/src/vendorcode/amd/cimx/sb800/SATA.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/SATA.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,665 @@ + +/** + * @file + * + * Config Southbridge SATA controller + * + * Init SATA features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: CIMx-SB + * @e sub-project: + * @e $Revision:$ @e $Date:$ + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" + +// +// Declaration of local functions +// +VOID sataSetIrqIntResource (IN AMDSBCFG* pConfig); +VOID sataBar5setting (IN AMDSBCFG* pConfig, IN UINT32 *pBar5); +VOID shutdownUnconnectedSataPortClock (IN AMDSBCFG* pConfig, IN UINT32 ddBar5); +VOID sataDriveDetection (IN AMDSBCFG* pConfig, IN UINT32 *pBar5); + +/** + * sataSetIrqIntResource - Config SATA IRQ/INT# resource + * + * + * - Private function + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +sataSetIrqIntResource ( + IN AMDSBCFG* pConfig + ) +{ + UINT8 dbValue; + // IRQ14/IRQ15 come from IDE or SATA + dbValue = 0x08; + WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &dbValue); + ReadIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue); + dbValue = dbValue & 0x0F; + if (pConfig->SataClass == 3) { + dbValue = dbValue | 0x50; + } else { + if (pConfig->SataIdeMode == 1) { + // Both IDE & SATA set to Native mode + dbValue = dbValue | 0xF0; + } + } + WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue); +} + +/** + * sataBar5setting - Config SATA BAR5 + * + * - Private function + * + * @param[in] pConfig - Southbridge configuration structure pointer. + * @param[in] *pBar5 - SATA BAR5 buffer. + * + */ +VOID +sataBar5setting ( + IN AMDSBCFG* pConfig, + IN UINT32 *pBar5 + ) +{ + //Get BAR5 value + ReadPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, pBar5); + //Assign temporary BAR if is not already assigned + if ( (*pBar5 == 0) || (*pBar5 == - 1) ) { + //assign temporary BAR5 + if ( (pConfig->TempMMIO == 0) || (pConfig->TempMMIO == - 1) ) { + *pBar5 = 0xFEC01000; + } else { + *pBar5 = pConfig->TempMMIO; + } + WritePCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, pBar5); + } + //Clear Bits 9:0 + *pBar5 = *pBar5 & 0xFFFFFC00; +} +/** + * shutdownUnconnectedSataPortClock - Shutdown unconnected Sata port clock + * + * - Private function + * + * @param[in] pConfig Southbridge configuration structure pointer. + * @param[in] ddBar5 Sata BAR5 base address. + * + */ +VOID +shutdownUnconnectedSataPortClock ( + IN AMDSBCFG* pConfig, + IN UINT32 ddBar5 + ) +{ + UINT8 dbPortNum; + UINT8 dbPortSataStatus; + UINT8 NumOfPorts; + UINT8 cimSataClkAutoOff; + + cimSataClkAutoOff = (UINT8) pConfig->SataClkAutoOff; +#if SB_CIMx_PARAMETER == 0 + cimSataClkAutoOff = cimSataClkAutoOffDefault; +#endif + NumOfPorts = 0; + if ( cimSataClkAutoOff == TRUE ) { + for ( dbPortNum = 0; dbPortNum < 6; dbPortNum++ ) { + ReadMEM (ddBar5 + SB_SATA_BAR5_REG128 + (dbPortNum * 0x80), AccWidthUint8, &dbPortSataStatus); + // Shutdown the clock for the port and do the necessary port reporting changes. + // ?? Error port status should be 1 not 3 + if ( ((dbPortSataStatus & 0x0F) != 0x03) && (! ((pConfig->SataEspPort) & (1 << dbPortNum))) ) { + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, (1 << dbPortNum)); + RWMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, ~(1 << dbPortNum), 00); + } + } //end of for (dbPortNum=0;dbPortNum<6;dbPortNum++) + ReadMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, &dbPortSataStatus); + //if all ports are in disabled state, report atleast one port + if ( (dbPortSataStatus & 0x3F) == 0) { + RWMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, (UINT32) ~(0x3F), 01); + } + ReadMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, &dbPortSataStatus); + for (dbPortNum = 0; dbPortNum < 6; dbPortNum ++) { + if (dbPortSataStatus & (1 << dbPortNum)) { + NumOfPorts++; + } + } + if ( NumOfPorts == 0) { + NumOfPorts = 0x01; + } + RWMEM (ddBar5 + SB_SATA_BAR5_REG00, AccWidthUint8, 0xE0, NumOfPorts - 1); + } //end of SataClkAuto Off option +} + +/** + * Table for class code of SATA Controller in different modes + * + * + * + * + */ +UINT32 sataIfCodeTable[] = +{ + 0x01018F40, //sata class ID of IDE + 0x01040040, //sata class ID of RAID + 0x01060140, //sata class ID of AHCI + 0x01018A40, //sata class ID of Legacy IDE + 0x01018F40, //sata class ID of IDE to AHCI mode +}; + +/** + * Table for device id of SATA Controller in different modes + * + * + * + * + */ +UINT16 sataDeviceIDTable[] = +{ + 0x4390, //sata device ID of IDE + 0x4392, //sata device ID of RAID + 0x4391, //sata class ID of AHCI + 0x4390, //sata device ID of Legacy IDE + 0x4390, //sata device ID of IDE->AHCI mode +}; + +/** + * Table for Sata Phy Fine Setting + * + * + * + * + */ +SATAPHYSETTING sataPhyTable[] = +{ + {0x3006, 0x0056A607}, + {0x2006, 0x00061400}, + {0x1006, 0x00061302}, + + {0x3206, 0x0056A607}, + {0x2206, 0x00061400}, + {0x1206, 0x00061302}, + + {0x3406, 0x0056A607}, + {0x2406, 0x00061402}, + {0x1406, 0x00064300}, + + {0x3606, 0x0056A607}, + {0x2606, 0x00061402}, + {0x1606, 0x00064300}, + + {0x3806, 0x0056A700}, + {0x2806, 0x00061502}, + {0x1806, 0x00064302}, + + {0x3A06, 0x0056A700}, + {0x2A06, 0x00061502}, + {0x1A06, 0x00064302} +}; + +/** + * sataInitBeforePciEnum - Config SATA controller before PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +sataInitBeforePciEnum ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 ddTempVar; + UINT32 ddValue; + UINT32 *tempptr; + UINT16 *pDeviceIdptr; + UINT32 dwDeviceId; + UINT8 dbValue; + UINT8 pValue; + UINT16 i; + SATAPHYSETTING *pPhyTable; + + ddTempVar = NULL; + // BIT0 Enable write access to PCI header (reg 08h-0Bh) by setting SATA PCI register 40h + // BIT4: Disable fast boot + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0 + BIT2 + BIT4); + // BIT0 Enable write access to PCI header (reg 08h-0Bh) by setting IDE PCI register 40h + RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0); + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8 | S3_SAVE, 0, pConfig->SataPortPower); + dbValue = (UINT8)pConfig->SataClass; + if (dbValue == AHCI_MODE_4394) { + dbValue = AHCI_MODE; + } + if (dbValue == IDE_TO_AHCI_MODE_4394) { + dbValue = IDE_TO_AHCI_MODE; + } + // Disable PATA MSI + RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG34), AccWidthUint8 | S3_SAVE, 0x00, 0x00); + RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG06), AccWidthUint8 | S3_SAVE, 0xEF, 0x00); + + // Get the appropriate class code from the table and write it to PCI register 08h-0Bh + // Set the appropriate SATA class based on the input parameters + // SATA IDE Controller Class ID & SSID + tempptr = (UINT32 *) FIXUP_PTR (&sataIfCodeTable[0]); + if ( (pConfig->SataIdeMode == 1) && (pConfig->SataClass != 3) ) { + ddValue = tempptr[0]; + // Write the class code to IDE PCI register 08h-0Bh + RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG08), AccWidthUint32 | S3_SAVE, 0, ddValue); + } + ddValue = tempptr[dbValue]; + // Write the class code to SATA PCI register 08h-0Bh + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG08), AccWidthUint32 | S3_SAVE, 0, ddValue); + if ( pConfig->SataClass == LEGACY_IDE_MODE ) { + //Set PATA controller to native mode + RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG09), AccWidthUint8 | S3_SAVE, 0x00, 0x08F); + } + if (pConfig->BuildParameters.IdeSsid != NULL ) { + RWPCI ((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.IdeSsid); + } + // SATA Controller Class ID & SSID + pDeviceIdptr = (UINT16 *) FIXUP_PTR (&sataDeviceIDTable[0]); + if ( pConfig->BuildParameters.SataIDESsid != NULL ) { + ddTempVar = pConfig->BuildParameters.SataIDESsid; + } + dwDeviceId = pDeviceIdptr[dbValue]; + if ( pConfig->SataClass == RAID_MODE) { + if ( pConfig->BuildParameters.SataRAID5Ssid != NULL ) { + ddTempVar = pConfig->BuildParameters.SataRAID5Ssid; + } + dwDeviceId = V_SB_SATA_RAID5_DID; + pValue = SATA_EFUSE_LOCATION; + getEfuseStatus (&pValue); + if (( pValue & SATA_EFUSE_BIT ) || ( pConfig->SataForceRaid == 1 )) { + dwDeviceId = V_SB_SATA_RAID_DID; + if ( pConfig->BuildParameters.SataRAIDSsid != NULL ) { + ddTempVar = pConfig->BuildParameters.SataRAIDSsid; + } + } + } + if ( ((pConfig->SataClass) == AHCI_MODE) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE) || + ((pConfig->SataClass) == AHCI_MODE_4394) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE_4394) ) { + if ( pConfig->BuildParameters.SataAHCISsid != NULL ) { + ddTempVar = pConfig->BuildParameters.SataAHCISsid; + } + } + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, dwDeviceId); + if ( ddTempVar != NULL ) { + RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG2C, AccWidthUint32 | S3_SAVE, 0x00, ddTempVar); + } + // SATA IRQ Resource + sataSetIrqIntResource (pConfig); + + // 8.4 SATA PHY Programming Sequence + pPhyTable = (SATAPHYSETTING*)FIXUP_PTR (&sataPhyTable[0]); + for (i = 0; i < (sizeof (sataPhyTable) / sizeof (SATAPHYSETTING)); i++) { + RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG84, AccWidthUint16 | S3_SAVE, ~(BIT1 + BIT2 + BIT9 + BIT10 + BIT11 + BIT12 + BIT13 + BIT14), pPhyTable->wPhyCoreControl); + RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG94, AccWidthUint32 | S3_SAVE, 0x00, pPhyTable->dwPhyFineTune); + ++pPhyTable; + } + +// CallBackToOEM (SATA_PHY_PROGRAMMING, NULL, pConfig); + + RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0); + // Disable write access to PCI header + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0); +} + +/** + * sataInitAfterPciEnum - Config SATA controller after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +sataInitAfterPciEnum ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 ddAndMask; + UINT32 ddOrMask; + UINT32 ddBar5; + UINT8 dbVar; + UINT8 dbPortNum; + UINT8 dbEfuse; + UINT8 dbPortMode; + UINT16 SataPortMode; + UINT8 cimSataAggrLinkPmCap; + UINT8 cimSataPortMultCap; + UINT8 cimSataPscCap; + UINT8 cimSataSscCap; + UINT8 cimSataFisBasedSwitching; + UINT8 cimSataCccSupport; + + cimSataAggrLinkPmCap = (UINT8) pConfig->SataAggrLinkPmCap; + cimSataPortMultCap = (UINT8) pConfig->SataPortMultCap; + cimSataPscCap = (UINT8) pConfig->SataPscCap; + cimSataSscCap = (UINT8) pConfig->SataSscCap; + cimSataFisBasedSwitching = (UINT8) pConfig->SataFisBasedSwitching; + cimSataCccSupport = (UINT8) pConfig->SataCccSupport; + +#if SB_CIMx_PARAMETER == 0 + cimSataAggrLinkPmCap = cimSataAggrLinkPmCapDefault; + cimSataPortMultCap = cimSataPortMultCapDefault; + cimSataPscCap = cimSataPscCapDefault; + cimSataSscCap = cimSataSscCapDefault; + cimSataFisBasedSwitching = cimSataFisBasedSwitchingDefault; + cimSataCccSupport = cimSataCccSupportDefault; +#endif + + ddAndMask = 0; + ddOrMask = 0; + ddBar5 = 0; + if ( pConfig->SATAMODE.SataMode.SataController == 0 ) { + return; //return if SATA controller is disabled. + } + + //Enable write access to pci header, pm capabilities + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xFF, BIT0); + //Disable AHCI Prefetch function + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8 | S3_SAVE, 0x7F, BIT7); + + sataBar5setting (pConfig, &ddBar5); + + ReadPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar); + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8,0xFF, 0x03); //memory and io access enable + dbEfuse = SATA_FIS_BASE_EFUSE_LOC; + getEfuseStatus (&dbEfuse); + + if ( !cimSataPortMultCap ) { + ddAndMask |= BIT12; + } + if ( cimSataAggrLinkPmCap ) { + ddOrMask |= BIT11; + } else { + ddAndMask |= BIT11; + } + if ( cimSataPscCap ) { + ddOrMask |= BIT1; + } + if ( cimSataSscCap ) { + ddOrMask |= BIT26; + } + if ( cimSataFisBasedSwitching ) { + if (dbEfuse & BIT1) { + ddAndMask |= BIT10; + } else { + ddOrMask |= BIT10; + } + } else { + ddAndMask |= BIT10; + } + // RPR 8.10 Disabling CCC (Command Completion Coalescing) support. + if ( cimSataCccSupport ) { + ddOrMask |= BIT19; + } else { + ddAndMask |= BIT19; + } + RWMEM ((ddBar5 + SB_SATA_BAR5_REGFC), AccWidthUint32 | S3_SAVE, ~ddAndMask, ddOrMask); + + + // SATA ESP port setting + // These config bits are set for SATA driver to identify which ports are external SATA ports and need to + // support hotplug. If a port is set as an external SATA port and need to support hotplug, then driver will + // not enable power management (HIPM & DIPM) for these ports. + if ( pConfig->SataEspPort != 0 ) { + RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(pConfig->SataEspPort), 0); + RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(BIT12 + BIT13 + BIT14 + BIT15 + BIT16 + BIT17 + BIT5 + BIT4 + BIT3 + BIT2 + BIT1 + BIT0), (pConfig->SataEspPort << 12)); + // RPR 8.7 External SATA Port Indication Registers + // If any of the ports was programmed as an external port, HCAP.SXS should also be set + RWMEM ((ddBar5 + SB_SATA_BAR5_REGFC), AccWidthUint32 | S3_SAVE, ~(BIT20), BIT20); + } else { + // RPR 8.7 External SATA Port Indication Registers + // If any of the ports was programmed as an external port, HCAP.SXS should also be set (Clear for no ESP port) + RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(BIT5 + BIT4 + BIT3 + BIT2 + BIT1 + BIT0), 0x00); + RWMEM ((ddBar5 + SB_SATA_BAR5_REGFC), AccWidthUint32 | S3_SAVE, ~(BIT20), 0x00); + } + if ( cimSataFisBasedSwitching ) { + if (dbEfuse & BIT1) { + RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(BIT22 + BIT23 + BIT24 + BIT25 + BIT26 + BIT27), 0x00); + } else { + RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(BIT22 + BIT23 + BIT24 + BIT25 + BIT26 + BIT27), (BIT22 + BIT23 + BIT24 + BIT25 + BIT26 + BIT27)); + } + } else { + RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(BIT22 + BIT23 + BIT24 + BIT25 + BIT26 + BIT27), 0x00); + } + + // Disabled SATA MSI and D3 Power State capability + // RPR 8.13 SATA MSI and D3 Power State Capability + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG34), AccWidthUint8 | S3_SAVE, 0, 0x70); + + if (((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE)) { + // RIAD or AHCI + if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == DISABLED) { + RWMEM ((ddBar5 + SB_SATA_BAR5_REG00), AccWidthUint8 | S3_SAVE, ~(BIT2 + BIT1 + BIT0), BIT2 + BIT0); + RWMEM ((ddBar5 + SB_SATA_BAR5_REG0C), AccWidthUint8 | S3_SAVE, 0xC0, 0x3F); + // RPR 8.10 Disabling CCC (Command Completion Coalescing) support. + // 8 messages + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50 + 2), AccWidthUint8, ~(BIT3 + BIT2 + BIT1), BIT2 + BIT1); + } else { + // RPR 8.10 Disabling CCC (Command Completion Coalescing) support. + if ( pConfig->SataCccSupport ) { + // 8 messages + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50 + 2), AccWidthUint8, ~(BIT3 + BIT2 + BIT1), BIT2 + BIT1); + } else { + // 4 messages + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50 + 2), AccWidthUint8, ~(BIT3 + BIT2 + BIT1), BIT2); + } + } + } + + if ( pConfig->BIOSOSHandoff == 1 ) { + RWMEM ((ddBar5 + SB_SATA_BAR5_REG24), AccWidthUint8 | S3_SAVE, ~BIT0, BIT0); + } else { + RWMEM ((ddBar5 + SB_SATA_BAR5_REG24), AccWidthUint8 | S3_SAVE, ~BIT0, 0x00); + } + + SataPortMode = (UINT16)pConfig->SataPortMode; + dbPortNum = 0; + while ( dbPortNum < 6 ) { + dbPortMode = (UINT8) (SataPortMode & 3); + if ( (dbPortMode == BIT0) || (dbPortMode == BIT1) ) { + if ( dbPortMode == BIT0 ) { + // set GEN 1 + RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0x0F, 0x10); + } + if ( dbPortMode == BIT1 ) { + // set GEN2 (default is GEN3) + RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0x0F, 0x20); + } + RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFF, 0x01); + } + SataPortMode >>= 2; + dbPortNum ++; + } + SbStall (1000); + SataPortMode = (UINT16)pConfig->SataPortMode; + dbPortNum = 0; + while ( dbPortNum < 6 ) { + dbPortMode = (UINT8) (SataPortMode & 3); + if ( (dbPortMode == BIT0) || (dbPortMode == BIT1) ) { + RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFE, 0x00); + } + dbPortNum ++; + SataPortMode >>= 2; + } + WritePCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar); + //Disable write access to pci header, pm capabilities + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0); +} + + +/** + * sataInitMidPost - Config SATA controller in Middle POST. + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +sataInitMidPost ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 ddBar5; + sataBar5setting (pConfig, &ddBar5); + //If this is not S3 resume and also if SATA set to one of IDE mode, them implement drive detection workaround. + if ( ! (pConfig->S3Resume) && ( ((pConfig->SataClass) != AHCI_MODE) && ((pConfig->SataClass) != RAID_MODE) ) ) { + sataDriveDetection (pConfig, &ddBar5); + } +} + +/** + * sataDriveDetection - Sata drive detection + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * @param[in] *pBar5 Sata BAR5 base address. + * + */ +VOID +sataDriveDetection ( + IN AMDSBCFG* pConfig, + IN UINT32 *pBar5 + ) +{ + UINT32 ddVar0; + UINT8 dbPortNum; + UINT8 dbVar0; + UINT16 dwIoBase; + UINT16 dwVar0; + if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) ) { + for ( dbPortNum = 0; dbPortNum < 4; dbPortNum++ ) { + ReadMEM (*pBar5 + SB_SATA_BAR5_REG128 + dbPortNum * 0x80, AccWidthUint32, &ddVar0); + if ( ( ddVar0 & 0x0F ) == 0x03 ) { + if ( dbPortNum & BIT0 ) { + //this port belongs to secondary channel + ReadPCI (((UINT32) (SATA_BUS_DEV_FUN << 16) + SB_SATA_REG18), AccWidthUint16, &dwIoBase); + } else { + //this port belongs to primary channel + ReadPCI (((UINT32) (SATA_BUS_DEV_FUN << 16) + SB_SATA_REG10), AccWidthUint16, &dwIoBase); + } + //if legacy ide mode, then the bar registers don't contain the correct values. So we need to hardcode them + if ( pConfig->SataClass == LEGACY_IDE_MODE ) { + dwIoBase = ( (0x170) | ((UINT16) ( (~((UINT8) (dbPortNum & BIT0) << 7)) & 0x80 )) ); + } + if ( dbPortNum & BIT1 ) { + //this port is slave + dbVar0 = 0xB0; + } else { + //this port is master + dbVar0 = 0xA0; + } + dwIoBase &= 0xFFF8; + WriteIO (dwIoBase + 6, AccWidthUint8, &dbVar0); + //Wait in loop for 30s for the drive to become ready + for ( dwVar0 = 0; dwVar0 < 300000; dwVar0++ ) { + ReadIO (dwIoBase + 7, AccWidthUint8, &dbVar0); + if ( (dbVar0 & 0x88) == 0 ) { + break; + } + SbStall (100); + } + } //end of if ( ( ddVar0 & 0x0F ) == 0x03) + } //for (dbPortNum = 0; dbPortNum < 4; dbPortNum++) + } //if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE)) +} + +/** + * sataInitLatePost - Prepare SATA controller to boot to OS. + * + * - Set class ID to AHCI (if set to AHCI * Mode) + * - Enable AHCI interrupt + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +sataInitLatePost ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 ddBar5; + UINT8 dbVar; + UINT8 dbPortNum; + + //Return immediately is sata controller is not enabled + if ( pConfig->SATAMODE.SataMode.SataController == 0 ) { + return; + } + //Enable write access to pci header, pm capabilities + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0); + +// if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == DISABLED) { + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 1), AccWidthUint8 | S3_SAVE, ~BIT7, BIT7); +// } + sataBar5setting (pConfig, &ddBar5); + + ReadPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar); + //Enable memory and io access + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, 0xFF, 0x03); + + shutdownUnconnectedSataPortClock (pConfig, ddBar5); + + if (( pConfig->SataClass == IDE_TO_AHCI_MODE) || ( pConfig->SataClass == IDE_TO_AHCI_MODE_4394 )) { + //program the AHCI class code + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG08), AccWidthUint32 | S3_SAVE, 0, 0x01060100); + //Set interrupt enable bit + RWMEM ((ddBar5 + 0x04), AccWidthUint8, (UINT32)~0, BIT1); + //program the correct device id for AHCI mode + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, 0x4391); + } + + if (( pConfig->SataClass == AHCI_MODE_4394 ) || ( pConfig->SataClass == IDE_TO_AHCI_MODE_4394 )) { + //program the correct device id for AHCI 4394 mode + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, 0x4394); + } + + //Clear error status ?? only 4 port + RWMEM ((ddBar5 + SB_SATA_BAR5_REG130), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF); + RWMEM ((ddBar5 + SB_SATA_BAR5_REG1B0), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF); + RWMEM ((ddBar5 + SB_SATA_BAR5_REG230), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF); + RWMEM ((ddBar5 + SB_SATA_BAR5_REG2B0), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF); + RWMEM ((ddBar5 + SB_SATA_BAR5_REG330), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF); + RWMEM ((ddBar5 + SB_SATA_BAR5_REG3B0), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF); + //Restore memory and io access bits + WritePCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar ); + //Disable write access to pci header and pm capabilities + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0); + for ( dbPortNum = 0; dbPortNum < 6; dbPortNum++ ) { + RWMEM ((ddBar5 + 0x110 + (dbPortNum * 0x80)), AccWidthUint32, 0xFFFFFFFF, 0x00); + } +} + +
Added: trunk/src/vendorcode/amd/cimx/sb800/SB800.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/SB800.h Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,1893 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#pragma pack (push, 1) + +#define CIMX_SB_REVISION "1.1.0.6" +#define CIMX_SB_ID "SB80A13" +#ifndef SBCIMx_Version + #define SBCIMx_Version 0x1106 +#endif //CIMx_Version + + +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page SB_POWERON_INIT_Page SB_POWERON_INIT + * @section SB_POWERON_INIT Interface Call + * Initialize structure referenced by AMDSBCFG to default recommended value. + * @subsection SB_POWERON_INIT_CallIn Call Prototype + * @par + * sbPowerOnInit ((AMDSBCFG*) pConfig) (Followed PH Interface) + * @subsection SB_BEFORE_PCI_INIT_CallID Service ID + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> SB_POWERON_INIT --> 0x00010001 </TD></TR> + * </TABLE> + * @subsection SB_POWERON_INIT_CallOut Prepare for Callout + * @par + * Not Applicable (Not necessary for the current implementation) + * @subsection SB_POWERON_INIT_Config Prepare for Configuration Data. + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> BUILDPARAM::BiosSize </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::LegacyFree </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::EcKbd </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::Smbus0BaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::Smbus1BaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::SioPmeBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::WatchDogTimerBase </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::GecShadowRomBase </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::SpiRomBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::AcpiPm1EvtBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::AcpiPm1CntBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::AcpiPmTmrBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::CpuControlBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::AcpiGpe0BlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::SmiCmdPortAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::AcpiPmaCntBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * </TABLE> + * + */ +#define SB_POWERON_INIT 0x00010001 +#define OUTDEBUG_PORT 0x00010002 +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page SB_BEFORE_PCI_INIT_Page SB_BEFORE_PCI_INIT + * @section SB_BEFORE_PCI_INIT Interface Call + * Initialize structure referenced by AMDSBCFG to default recommended value. + * @subsection SB_BEFORE_PCI_INIT_CallIn Call Prototype + * @par + * sbBeforePciInit ((AMDSBCFG*)pConfig) (Followed PH Interface) + * @subsection SB_BEFORE_PCI_INIT_CallID Service ID + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> SB_BEFORE_PCI_INIT --> 0x00010010 </TD></TR> + * </TABLE> + * @subsection SB_BEFORE_PCI_INIT_CallOut Prepare for Callout + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> @ref CB_SBGPP_RESET_ASSERT_Page "CB_SBGPP_RESET_ASSERT"</TD></TR> + * <TR><TD class="indexkey" width=380> @ref CB_SBGPP_RESET_DEASSERT_Page "CB_SBGPP_RESET_DEASSERT"</TD></TR> + * </TABLE> + * @subsection SB_BEFORE_PCI_INIT_Config Prepare for Configuration Data. + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> AMDSBCFG::SataIdeMode </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> AMDSBCFG::USBDeviceConfig </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> AMDSBCFG::GecConfig </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaController </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> AMDSBCFG::PciClks </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::SataIDESsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::SataRAID5Ssid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::SataRAIDSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::SataAHCISsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::SmbusSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::LpcSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::PCIBSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> + * </TABLE> + * + */ +#define SB_BEFORE_PCI_INIT 0x00010010 +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page SB_AFTER_PCI_INIT_Page SB_AFTER_PCI_INIT + * @section SB_AFTER_PCI_INIT Interface Call + * Initialize structure referenced by AMDSBCFG to default recommended value. + * @subsection SB_AFTER_PCI_INIT_CallIn Call Prototype + * @par + * sbAfterPciInit ((AMDSBCFG*)pConfig) (Followed PH Interface) + * @subsection SB_AFTER_PCI_INIT_CallID Service ID + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> SB_AFTER_PCI_INIT --> 0x00010020 </TD></TR> + * </TABLE> + * @subsection SB_AFTER_PCI_INIT_CallOut Prepare for Callout + * @par + * Not Applicable (Not necessary for the current implementation) + * @subsection SB_AFTER_PCI_INIT_Config Prepare for Configuration Data. + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> AMDSBCFG::SataEspPort </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaController </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaPinCfg </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaSdinPin </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::OhciSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::Ohci4Ssid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::EhciSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::AzaliaSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> + * </TABLE> + * + */ +#define SB_AFTER_PCI_INIT 0x00010020 +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page SB_MID_POST_INIT_Page SB_MID_POST_INIT + * @section SB_MID_POST_INIT Interface Call + * Initialize structure referenced by AMDSBCFG to default recommended value. + * @subsection SB_MID_POST_INIT_CallIn Call Prototype + * @par + * sbMidPostInit ((AMDSBCFG*)pConfig) (Followed PH Interface) + * @subsection SB_MID_POST_INIT_CallID Service ID + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> SB_MID_POST_INIT --> 0x00010021 </TD></TR> + * </TABLE> + * @subsection SB_MID_POST_INIT_CallOut Prepare for Callout + * @par + * Not Applicable (Not necessary for the current implementation) + * @subsection SB_MID_POST_INIT_Config Prepare for Configuration Data. + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * </TABLE> + * + */ +#define SB_MID_POST_INIT 0x00010021 +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page SB_LATE_POST_INIT_Page SB_LATE_POST_INIT + * @section SB_LATE_POST_INIT Interface Call + * Initialize structure referenced by AMDSBCFG to default recommended value. + * @subsection SB_LATE_POST_INIT_CallIn Call Prototype + * @par + * sbLatePost ((AMDSBCFG*)pConfig) (Followed PH Interface) + * @subsection SB_LATE_POST_INIT_CallID Service ID + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> SB_LATE_POST_INIT --> 0x00010030 </TD></TR> + * </TABLE> + * @subsection SB_LATE_POST_INIT_CallOut Prepare for Callout + * @par + * Not Applicable (Not necessary for the current implementation) + * @subsection SB_LATE_POST_INIT_Config Prepare for Configuration Data. + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * </TABLE> + * + */ +#define SB_LATE_POST_INIT 0x00010030 +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page SB_BEFORE_PCI_RESTORE_INIT_Page SB_BEFORE_PCI_RESTORE_INIT + * @section SB_BEFORE_PCI_RESTORE_INIT Interface Call + * Initialize structure referenced by AMDSBCFG to default recommended value. + * @subsection SB_BEFORE_PCI_RESTORE_INIT_CallIn Call Prototype + * @par + * sbBeforePciRestoreInit ((AMDSBCFG*)pConfig) (Followed PH Interface) + * @subsection SB_BEFORE_PCI_RESTORE_INIT_CallID Service ID + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> SB_BEFORE_PCI_RESTORE_INIT --> 0x00010040 </TD></TR> + * </TABLE> + * @subsection SB_BEFORE_PCI_RESTORE_INIT_CallOut Prepare for Callout + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> @ref CB_SBGPP_RESET_ASSERT_Page "CB_SBGPP_RESET_ASSERT"</TD></TR> + * <TR><TD class="indexkey" width=380> @ref CB_SBGPP_RESET_DEASSERT_Page "CB_SBGPP_RESET_DEASSERT"</TD></TR> + * </TABLE> + * @subsection SB_BEFORE_PCI_RESTORE_INIT_Config Prepare for Configuration Data. + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> AMDSBCFG::SataIdeMode </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> AMDSBCFG::USBDeviceConfig </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> AMDSBCFG::GecConfig </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaController </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> AMDSBCFG::PciClks </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::SataIDESsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::SataRAID5Ssid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::SataRAIDSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::SataAHCISsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::SmbusSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::LpcSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::PCIBSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> + * </TABLE> + * + */ +#define SB_BEFORE_PCI_RESTORE_INIT 0x00010040 +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page SB_AFTER_PCI_RESTORE_INIT_Page SB_AFTER_PCI_RESTORE_INIT + * @section SB_AFTER_PCI_RESTORE_INIT Interface Call + * Initialize structure referenced by AMDSBCFG to default recommended value. + * @subsection SB_AFTER_PCI_RESTORE_INIT_CallIn Call Prototype + * @par + * sbAfterPciRestoreInit ((AMDSBCFG*)pConfig) (Followed PH Interface) + * @subsection SB_AFTER_PCI_RESTORE_INIT_CallID Service ID + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> SB_AFTER_PCI_RESTORE_INIT --> 0x00010050 </TD></TR> + * </TABLE> + * @subsection SB_AFTER_PCI_RESTORE_INIT_CallOut Prepare for Callout + * @par + * Not Applicable (Not necessary for the current implementation) + * @subsection SB_AFTER_PCI_RESTORE_INIT_Config Prepare for Configuration Data. + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> AMDSBCFG::SataEspPort </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaController </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaPinCfg </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaSdinPin </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::OhciSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::Ohci4Ssid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::EhciSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILDPARAM::AzaliaSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> + * </TABLE> + * + */ +#define SB_AFTER_PCI_RESTORE_INIT 0x00010050 +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page SB_SMM_SERVICE_Page SB_SMM_SERVICE + * @section SB_SMM_SERVICE Interface Call + * Initialize structure referenced by AMDSBCFG to default recommended value. + * @subsection SB_SMM_SERVICE_CallIn Call Prototype + * @par + * sbSmmService ((AMDSBCFG*)pConfig) (Followed PH Interface) + * @subsection SB_SMM_SERVICE_CallID Service ID + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> SB_SMM_SERVICE --> 0x00010060 </TD></TR> + * </TABLE> + * @subsection SB_SMM_SERVICE_CallOut Prepare for Callout + * @par + * Not Applicable (Not necessary for the current implementation) + * @subsection SB_SMM_SERVICE_Config Prepare for Configuration Data. + * @par + * Not necessary on current implementation + * + */ +#define SB_SMM_SERVICE 0x00010060 +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page SB_SMM_ACPION_Page SB_SMM_ACPION + * @section SB_SMM_ACPION Interface Call + * Initialize structure referenced by AMDSBCFG to default recommended value. + * @subsection SB_SMM_ACPION_CallIn Call Prototype + * @par + * sbSmmAcpiOn ((AMDSBCFG*)pConfig) (Followed PH Interface) + * @subsection SB_SMM_ACPION_CallID Service ID + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> SB_SMM_ACPION --> 0x00010061 </TD></TR> + * </TABLE> + * @subsection SB_SMM_ACPION_CallOut Prepare for Callout + * @par + * Not Applicable (Not necessary for the current implementation) + * @subsection SB_SMM_ACPION_Config Prepare for Configuration Data. + * @par + * Not necessary on current implementation + * + */ +#define SB_SMM_ACPION 0x00010061 +#define SB_EC_FANCONTROL 0x00010070 + +#ifndef OEM_CALLBACK_BASE + #define OEM_CALLBACK_BASE 0x00010100 +#endif + +//0x00 - 0x0F callback functions are reserved for bootblock +#define SATA_PHY_PROGRAMMING OEM_CALLBACK_BASE + 0x10 +#define PULL_UP_PULL_DOWN_SETTINGS OEM_CALLBACK_BASE + 0x20 +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page CB_SBGPP_RESET_ASSERT_Page CB_SBGPP_RESET_ASSERT + * @section CB_SBGPP_RESET_ASSERT Interface Call + * Initialize structure referenced by AMDSBCFG to default recommended value. + * @subsection CB_SBGPP_RESET_ASSERT_CallID Service ID + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> CB_SBGPP_RESET_ASSERT --> 0x00010130 </TD></TR> + * </TABLE> + * @subsection CB_SBGPP_RESET_ASSERT_Config Prepare for Configuration Data. + * @par + * Not necessary on current implementation + * + */ +#define CB_SBGPP_RESET_ASSERT OEM_CALLBACK_BASE + 0x30 +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page CB_SBGPP_RESET_DEASSERT_Page CB_SBGPP_RESET_DEASSERT + * @section CB_SBGPP_RESET_DEASSERT Interface Call + * Initialize structure referenced by AMDSBCFG to default recommended value. + * @subsection CB_SBGPP_RESET_DEASSERT _CallID Service ID + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> CB_SBGPP_RESET_DEASSERT --> 0x00010131 </TD></TR> + * </TABLE> + * @subsection CB_SBGPP_RESET_DEASSERT _Config Prepare for Configuration Data. + * @par + * Not necessary on current implementation + * + */ +#define CB_SBGPP_RESET_DEASSERT OEM_CALLBACK_BASE + 0x31 + +#define IMC_FIRMWARE_FAIL OEM_CALLBACK_BASE + 0x40 + +#define CFG_ADDR_PORT 0xCF8 +#define CFG_DATA_PORT 0xCFC + +#define ALINK_ACCESS_INDEX 0x0CD8 +#define ALINK_ACCESS_DATA ALINK_ACCESS_INDEX + 4 + +/*------------------------------------------------------------------ +; I/O Base Address - Should be set by host BIOS +;------------------------------------------------------------------ */ +#define DELAY_PORT 0x0E0 + +/*------------------------------------------------------------------ +; Fuse ID and minor ID of efuse bits +;------------------------------------------------------------------ */ +#define FUSE_ID_EFUSE_LOC 0x1F // efuse bits 248-255 +#define MINOR_ID_EFUSE_LOC 0x1E // efuse bits 240-247 +#define M1_D1_FUSE_ID 0x70 +#define M1_MINOR_ID 0x02 + +/*------------------------------------------------------------------ +; DEBUG_PORT = 8-bit I/O Port Address for POST Code Display +;------------------------------------------------------------------ */ +// ASIC VendorID and DeviceIDs +#define AMD_SB_VID 0x1002 +#define SB_DEVICE_ID 0x4385 /* AMD ER SB800 */ +#define V_SB_SATA_VID AMD_SB_VID // dev 17 Func 0 +#define V_SB_SATA_DID 0x4390 +#define V_SB_SATA_AHCI_DID 0x4391 +#define V_SB_SATA_RAID_DID 0x4392 +#define V_SB_SATA_RAID5_DID 0x4393 +#define V_SB_USB_OHCI_VID AMD_SB_VID // dev 18 Func 0, dev 19 Func 0, dev 22 Func 0 +#define V_SB_USB_OHCI_DID 0x4397 +#define V_SB_USB_EHCI_VID AMD_SB_VID // dev 18 Func 2, dev 19 Func 2, dev 22 Func 2 +#define V_SB_USB_EHCI_DID 0x4396 +#define V_SB_SMBUS_VID AMD_SB_VID // dev 20 Func 0 +#define V_SB_SMBUS_DID 0x4385 +#define V_SB_IDE_VID AMD_SB_VID // dev 20 Func 1 +#define V_SB_IDE_DID 0x439C +#define V_SB_AZALIA_VID AMD_SB_VID // dev 20 Func 2 +#define V_SB_AZALIA_DID 0x4383 +#define V_SB_LPC_VID AMD_SB_VID // dev 20 Func 3 +#define V_SB_LPC_DID 0x439D +#define V_SB_PCIB_VID AMD_SB_VID // dev 20 Func 4 +#define V_SB_PCIB_DID 0x4384 +#define V_SB_USB_OHCIF_VID AMD_SB_VID // dev 20 Func 5 +#define V_SB_USB_OHCIF_DID 0x4399 +#define V_SB_NIC_VID 0x14E4 // dev 20 Func 6 +#define V_SB_NIC_DID 0x1699 + +//Misc +#define ACPI_SMI_CMD_PORT 0xB0 +#define ACPI_SMI_DATA_PORT 0xB1 +#define R_SB_ACPI_PM1_STATUS 0x00 +#define R_SB_ACPI_PM1_ENABLE 0x02 +#define R_SB_ACPI_PM_CONTROL 0x04 +#define R_SB_ACPI_EVENT_STATUS 0x20 +#define R_SB_ACPI_EVENT_ENABLE 0x24 +#define R_SB_PM_ACPI_PMA_CNT_BLK_LO 0x2C + +#define SATA_BUS_DEV_FUN ((0x11 << 3) + 0) +#define SB_SATA1_BUS 0 +#define SB_SATA1_DEV 17 +#define SB_SATA1_FUNC 0 + +#define FC_BUS_DEV_FUN ((0x11 << 3) + 1) +#define USB1_OHCI_BUS_DEV_FUN ((0x12 << 3) + 0) // PORT 0-4 +#define SB_OHCI1_BUS 0 +#define SB_OHCI1_DEV 18 +#define SB_OHCI1_FUNC 0 +#define USB2_OHCI_BUS_DEV_FUN ((0x13 << 3) + 0) // PORT 5-9 +#define SB_OHCI2_BUS 0 +#define SB_OHCI2_DEV 19 +#define SB_OHCI2_FUNC 0 +#define USB3_OHCI_BUS_DEV_FUN ((0x16 << 3) + 0) // PORT 10-13 +#define SB_OHCI3_BUS 0 +#define SB_OHCI3_DEV 22 +#define SB_OHCI3_FUNC 0 +#define USB1_EHCI_BUS_DEV_FUN ((0x12 << 3) + 2) // PORT 0-4 +#define SB_EHCI1_BUS 0 +#define SB_EHCI1_DEV 18 +#define SB_EHCI1_FUNC 2 +#define USB2_EHCI_BUS_DEV_FUN ((0x13 << 3) + 2) // PORT 5-9 +#define SB_EHCI2_BUS 0 +#define SB_EHCI2_DEV 19 +#define SB_EHCI2_FUNC 2 +#define USB3_EHCI_BUS_DEV_FUN ((0x16 << 3) + 2) // PORT 10-13 +#define SB_EHCI3_BUS 0 +#define SB_EHCI3_DEV 22 +#define SB_EHCI3_FUNC 2 + +#define SMBUS_BUS_DEV_FUN ((0x14 << 3) + 0) +#define SB_ISA_BUS 0 +#define SB_ISA_DEV 20 +#define SB_ISA_FUNC 0 +#define IDE_BUS_DEV_FUN ((0x14 << 3) + 1) +#define SB_IDE_BUS 0 +#define SB_IDE_DEV 20 +#define SB_IDE_FUNC 1 +#define AZALIA_BUS_DEV_FUN ((0x14 << 3) + 2) +#define SB_AZALIA_BUS 0 +#define SB_AZALIA_DEV 20 +#define SB_AZALIA_FUNC 2 +#define LPC_BUS_DEV_FUN ((0x14 << 3) + 3) +#define SB_LPC_BUS 0 +#define SB_LPC_DEV 20 +#define SB_LPC_FUNC 3 +#define PCIB_BUS_DEV_FUN ((0x14 << 3) + 4) // P2P in SB700 +#define SB_PCI_BUS 0 +#define SB_PCI_DEV 20 +#define SB_PCI_FUNC 4 +#define USB4_OHCI_BUS_DEV_FUN ((0x14 << 3) + 5) // PORT FL0 - FL1 +#define SB_OHCI4_BUS 0 +#define SB_OHCI4_DEV 20 +#define SB_OHCI4_FUNC 5 +//Gigabyte Ethernet Controller +#define GEC_BUS_DEV_FUN ((0x14 << 3) + 6) +#define SB_GBEC_BUS 0 +#define SB_GBEC_DEV 20 +#define SB_GBEC_FUNC 6 + +#define SB_GPP_BUS 0 +#define SB_GPP_DEV 21 +#define SB_GPP_FUNC 0 +#define GPP0_BUS_DEV_FUN ((0x15 << 3) + 0) // GPP P2P bridge PORT0 +#define GPP1_BUS_DEV_FUN ((0x15 << 3) + 1) // GPP P2P bridge PORT1 +#define GPP2_BUS_DEV_FUN ((0x15 << 3) + 2) // GPP P2P bridge PORT2 +#define GPP3_BUS_DEV_FUN ((0x15 << 3) + 3) // GPP P2P bridge PORT3 + +#define ACPI_MMIO_BASE 0xFED80000 +#define SB_CFG_BASE 0x000 // DWORD +#define GPIO_BASE 0x100 // BYTE +#define SMI_BASE 0x200 // DWORD +#define PMIO_BASE 0x300 // DWORD +#define PMIO2_BASE 0x400 // BYTE +#define BIOS_RAM_BASE 0x500 // BYTE +#define CMOS_RAM_BASE 0x600 // BYTE +#define CMOS_BASE 0x700 // BYTE +#define ASF_BASE 0x900 // DWORD +#define SMBUS_BASE 0xA00 // DWORD +#define WATCHDOG_BASE 0xB00 // ?? +#define HPET_BASE 0xC00 // DWORD +#define IOMUX_BASE 0xD00 // BYTE +#define MISC_BASE 0xE00 + +#define GPP_EFUSE_LOCATION 0x14 // bit 160 +#define GPP_GEN2_EFUSE_BIT BIT0 + +// RegSpace field (AB_INDEX[31:29] +#define AXINDC 0 // AXINDC +#define AXINDP 2 // AXINDP +#define ABCFG 6 // ABCFG +#define AXCFG 4 // AXCFG +#define RCINDXC 1 // PCIEIND +#define RCINDXP 3 // PCIEIND_P + +#define SBTEMP_BUS 8 +#define GPP_DEV_NUM 21 //?? Code style different +#define MAX_GPP_PORTS 4 +#ifndef TRUE + #define TRUE 1 +#endif +#ifndef FALSE + #define FALSE 0 +#endif +// +// ABCFG Registers +// +#define SB_ABCFG_REG00 0x00 // VENDOR ID +#define SB_ABCFG_REG08 0x08 // REVISION ID +#define SB_ABCFG_REG40 0x40 // BL_EVENTCNT0LO +#define SB_ABCFG_REG44 0x44 // BL_EVENTCNT1LO +#define SB_ABCFG_REG48 0x48 // BL_EVENTCNTSEL +#define SB_ABCFG_REG4A 0x4A // BL_EVENTCNT0HI +#define SB_ABCFG_REG4B 0x4B // BL_EVENTCNT1HI +#define SB_ABCFG_REG4C 0x4C // BL_EVENTCNTCTL +#define SB_ABCFG_REG50 0x50 // MISCCTL_50 +#define SB_ABCFG_REG54 0x54 // MISCCTL_54 +#define SB_ABCFG_REG58 0x58 // BL RAB CONTROL + +#define SB_ABCFG_REG60 0x60 // LINKWIDTH_CTL +#define SB_ABCFG_REG64 0x64 // LINKWIDTH_UP_INTERVAL +#define SB_ABCFG_REG68 0x68 // LINKWIDTH_DN_INVERVAL +#define SB_ABCFG_REG6C 0x6C // LINKWIDTH_UPSTREAM_DWORDS +#define SB_ABCFG_REG70 0x70 // LINKWIDTH_DOWNSTREAM_DWORDS +#define SB_ABCFG_REG74 0x74 // LINKWIDTH_THRESHOLD_INCREASE +#define SB_ABCFG_REG78 0x78 // LINKWIDTH_THRESHOLD_DECREASE + +#define SB_ABCFG_REG80 0x80 // BL DMA PREFETCH CONTROL +#define SB_ABCFG_REG88 0x88 // +#define SB_ABCFG_REG90 0x90 // BIF CONTROL 0 +#define SB_ABCFG_REG94 0x94 // MSI CONTROL +#define SB_ABCFG_REG98 0x98 // BIF CONTROL 1 +#define SB_ABCFG_REG9C 0x9C // MISCCTL_9C +#define SB_ABCFG_REGA0 0xA0 // BIF PHY CONTROL ENABLE +#define SB_ABCFG_REGA4 0xA4 // BIF PHY CONTROL A4 +#define SB_ABCFG_REGA8 0xA8 // BIF PHY CONTROL A8 +#define SB_ABCFG_REGB0 0xB0 // HYPERFLASH-PCIE PORT MAPPING +#define SB_ABCFG_REGC0 0xC0 // PCIE_GPP_ENABLE +#define SB_ABCFG_REGC4 0xC4 // PCIE_P2P_INT_MAP +#define SB_ABCFG_REGD0 0xD0 // MCTP_VDM_TX_FIFO_DATA +#define SB_ABCFG_REGD4 0xD4 // MCTP_VMD_TX_CONTROL +#define SB_ABCFG_REGE0 0xE0 // MCTP_VDM_RX_FIFO_DATA +#define SB_ABCFG_REGE4 0xE4 // MCTP_VDM_RX_FIFO_STATUS +#define SB_ABCFG_REGEC 0xEC // MCTP_VDM_CONTROL +#define SB_ABCFG_REGF0 0xF0 // GPP_UPSTREAM_CONTROL +#define SB_ABCFG_REGFC 0xFC // SB_TRAP_CONTROL +#define SB_ABCFG_REG100 0x100 // SB_TRAP0_ADDRL +#define SB_ABCFG_REG104 0x104 // SB_TRAP0_ADDRH +#define SB_ABCFG_REG108 0x108 // SB_TRAP0_CMD +#define SB_ABCFG_REG10C 0x10C // SB_TRAP1_DATA +#define SB_ABCFG_REG110 0x110 // SB_TRAP1_ADDRL +#define SB_ABCFG_REG114 0x114 // SB_TRAP1_ADDRH +#define SB_ABCFG_REG118 0x118 // SB_TRAP1_CMD +#define SB_ABCFG_REG11C 0x11C // SB_TRAP1_DATA +#define SB_ABCFG_REG120 0x120 // SB_TRAP2_ADDRL +#define SB_ABCFG_REG124 0x124 // SB_TRAP2_ADDRH +#define SB_ABCFG_REG128 0x128 // SB_TRAP2_CMD +#define SB_ABCFG_REG12C 0x12C // SB_TRAP2_DATA +#define SB_ABCFG_REG130 0x130 // SB_TRAP3_ADDRL +#define SB_ABCFG_REG134 0x134 // SB_TRAP3_ADDRH +#define SB_ABCFG_REG138 0x138 // SB_TRAP3_CMD +#define SB_ABCFG_REG13C 0x13C // SB_TRAP3_DATA +#define SB_ABCFG_REG300 0x300 // MCTP_VDM_RX_SMI_CONTROL +#define SB_ABCFG_REG310 0x310 // BIF_GPP_STRAP_SYSTEM_0 +#define SB_ABCFG_REG314 0x314 // BIF_GPP_STRAP_SYSTEM_1 +#define SB_ABCFG_REG31C 0x31C // BIF_GPP_STRAP_LINK_CONTROL_0 +#define SB_ABCFG_REG320 0x320 // BIF_GPP_STRAP_LINK_CONTROL_LANE_A +#define SB_ABCFG_REG324 0x324 // BIF_GPP_STRAP_LINK_CONTROL_LANE_B +#define SB_ABCFG_REG328 0x328 // BIF_GPP_STRAP_LINK_CONTROL_LANE_C +#define SB_ABCFG_REG32C 0x32C // BIF_GPP_STRAP_LINK_CONTROL_LANE_D +#define SB_ABCFG_REG330 0x330 // BIF_GPP_STRAP_BIF_0 +#define SB_ABCFG_REG334 0x334 // BIF_GPP_STRAP_BIF_1 +#define SB_ABCFG_REG338 0x338 // BIF_GPP_STRAP_BIF_2 +#define SB_ABCFG_REG340 0x340 // BIF_GPP_STRAP_BIF_LANE_A +#define SB_ABCFG_REG344 0x344 // BIF_GPP_STRAP_BIF_LANE_B +#define SB_ABCFG_REG348 0x348 // BIF_GPP_STRAP_BIF_LANE_C +#define SB_ABCFG_REG34C 0x34C // BIF_GPP_STRAP_BIF_LANE_D +#define SB_ABCFG_REG350 0x350 // BIF_GPP_STRAP_PHY_LOGICAL _0 +#define SB_ABCFG_REG354 0x354 // BIF_GPP_STRAP_PHY_LOGICAL _1 +#define SB_ABCFG_REG404 0x404 // GPP0_SHADOW_COMMAND +#define SB_ABCFG_REG418 0x418 // GPP0_SHADOW_BUS_NUMBER +#define SB_ABCFG_REG41C 0x41C // GPP0_SHADOW_IO_LIMIT_BASE +#define SB_ABCFG_REG420 0x420 // GPP0_SHADOW_MEM_LIMIT_BASE +#define SB_ABCFG_REG424 0x424 // GPP0_SHADOW_PREF_MEM_LIMIT_BASE +#define SB_ABCFG_REG428 0x428 // GPP0_SHADOW_PREF_MEM_BASE_UPPER +#define SB_ABCFG_REG42C 0x42C // GPP0_SHADOW_PREF_MEM_LIMIT_UPPER +#define SB_ABCFG_REG430 0x430 // GPP0_SHADOW_IO_LIMIT_BASE_UPPER +#define SB_ABCFG_REG43C 0x43C // GPP0_SHADOW_BRIDGE_CONTROL +#define SB_ABCFG_REG444 0x444 // GPP1_SHADOW_COMMAND +#define SB_ABCFG_REG458 0x458 // GPP1_SHADOW_BUS_NUMBER +#define SB_ABCFG_REG45C 0x45C // GPP1_SHADOW_IO_LIMIT_BASE +#define SB_ABCFG_REG460 0x460 // GPP1_SHADOW_MEM_LIMIT_BASE +#define SB_ABCFG_REG464 0x464 // GPP1_SHADOW_PREF_MEM_LIMIT_BASE +#define SB_ABCFG_REG468 0x468 // GPP1_SHADOW_PREF_MEM_BASE_UPPER +#define SB_ABCFG_REG46C 0x46C // GPP1_SHADOW_PREF_MEM_LIMIT_UPPER +#define SB_ABCFG_REG470 0x470 // GPP1_SHADOW_IO_LIMIT_BASE_UPPER +#define SB_ABCFG_REG47C 0x47C // GPP1_SHADOW_BRIDGE_CONTROL +#define SB_ABCFG_REG484 0x484 // GPP2_SHADOW_COMMAND +#define SB_ABCFG_REG498 0x498 // GPP2_SHADOW_BUS_NUMBER +#define SB_ABCFG_REG49C 0x49C // GPP2_SHADOW_IO_LIMIT_BASE +#define SB_ABCFG_REG4A0 0x4A0 // GPP2_SHADOW_MEM_LIMIT_BASE +#define SB_ABCFG_REG4A4 0x4A4 // GPP2_SHADOW_PREF_MEM_LIMIT_BASE +#define SB_ABCFG_REG4A8 0x4A8 // GPP2_SHADOW_PREF_MEM_BASE_UPPER +#define SB_ABCFG_REG4AC 0x4AC // GPP2_SHADOW_PREF_MEM_LIMIT_UPPER +#define SB_ABCFG_REG4B0 0x4B0 // GPP2_SHADOW_IO_LIMIT_BASE_UPPER +#define SB_ABCFG_REG4BC 0x4BC // GPP2_SHADOW_BRIDGE_CONTROL +#define SB_ABCFG_REG4C4 0x4C4 // GPP3_SHADOW_COMMAND +#define SB_ABCFG_REG4D8 0x4D8 // GPP3_SHADOW_BUS_NUMBER +#define SB_ABCFG_REG4DC 0x4DC // GPP3_SHADOW_IO_LIMIT_BASE +#define SB_ABCFG_REG4E0 0x4E0 // GPP3_SHADOW_MEM_LIMIT_BASE +#define SB_ABCFG_REG4E4 0x4E4 // GPP3_SHADOW_PREF_MEM_LIMIT_BASE +#define SB_ABCFG_REG4E8 0x4E8 // GPP3_SHADOW_PREF_MEM_BASE_UPPER +#define SB_ABCFG_REG4EC 0x4EC // GPP3_SHADOW_PREF_MEM_LIMIT_UPPER +#define SB_ABCFG_REG4F0 0x4F0 // GPP3_SHADOW_IO_LIMIT_BASE_UPPER +#define SB_ABCFG_REG4FC 0x4FC // GPP3_SHADOW_BRIDGE_CONTROL +#define SB_ABCFG_REG10040 0x10040 // AL_EVENTCNT0LO +#define SB_ABCFG_REG10044 0x10044 // AL_EVENTCNT1LO +#define SB_ABCFG_REG10048 0x10048 // AL_EVENTCNTSEL +#define SB_ABCFG_REG1004A 0x1004A // AL_EVENTCNT0HI +#define SB_ABCFG_REG1004B 0x1004B // AL_EVENTCNT1HI +#define SB_ABCFG_REG1004C 0x1004C // AL_EVENTCNTCTL +#define SB_ABCFG_REG10050 0x10050 // MISCCTL_10050 +#define SB_ABCFG_REG10054 0x10054 // AL_ARB_CTL +#define SB_ABCFG_REG10056 0x10056 // AL_CLK_CTL +#define SB_ABCFG_REG10058 0x10058 // AL RAB CONTROL +#define SB_ABCFG_REG1005C 0x1005C // AL MLT CONTROL +#define SB_ABCFG_REG10060 0x10060 // AL DMA PREFETCH ENABLE +#define SB_ABCFG_REG10064 0x10064 // AL DMA PREFETCH FLUSH CONTROL +#define SB_ABCFG_REG10068 0x10068 // AL PREFETCH LIMIT +#define SB_ABCFG_REG1006C 0x1006C // AL DMA PREFETCH CONTROL +#define SB_ABCFG_REG10070 0x10070 // MISCCTL_10070 +#define SB_ABCFG_REG10080 0x10080 // CLKMUXSTATUS +#define SB_ABCFG_REG10090 0x10090 // BIF CONTROL 0 +#define SB_ABCFG_REG1009C 0x1009C // MISCCTL_1009C + +// +// RCINDX_P Registers +// +#define SB_RCINDXP_REG01 0x01 | RCINDXP << 29 // PCIEP_SCRATCH +#define SB_RCINDXP_REG10 0x10 | RCINDXP << 29 // +#define SB_RCINDXP_REG20 0x20 | RCINDXP << 29 // PCIE_TX_CNTL +#define SB_RCINDXP_REG50 0x50 | RCINDXP << 29 // PCIE_P_PORT_LANE_STATUS +#define SB_RCINDXP_REG70 0x70 | RCINDXP << 29 // PCIE_RX_CNTL +#define SB_RCINDXP_REGA0 0xA0 | RCINDXP << 29 // PCIE_LC_CNTL +#define SB_RCINDXP_REGA1 0xA1 | RCINDXP << 29 // PCIE_LC_TRAINING_CNTL +#define SB_RCINDXP_REGA2 0xA2 | RCINDXP << 29 // +#define SB_RCINDXP_REGA4 0xA4 | RCINDXP << 29 // +#define SB_RCINDXP_REGA5 0xA5 | RCINDXP << 29 // PCIE_LC_STATE0 +#define SB_RCINDXP_REGC0 0xC0 | RCINDXP << 29 // + +// +// RCINDX_C Registers +// +#define SB_RCINDXC_REG02 0x02 | RCINDXC << 29 // PCIE_HW_DEBUG +#define SB_RCINDXC_REG10 0x10 | RCINDXC << 29 // PCIE_CNTL +#define SB_RCINDXC_REGC1 0xC1 | RCINDXC << 29 // + +// +// AXINDC Registers +// +#define SB_AX_INDXC_REG02 0x02 // PCIEP_HW_DEBUG +#define SB_AX_INDXC_REG10 0x10 +#define SB_AX_INDXC_REG30 0x30 +#define SB_AX_DATAC_REG34 0x34 +#define SB_AX_INDXP_REG38 0x38 +#define SB_AX_DATAP_REG3C 0x3C +#define SB_AX_INDXC_REG40 0x40 | AXINDC << 29 +#define SB_AX_INDXC_REGA4 0xA4 | AXINDC << 29 + +#define SB_AX_INDXP_REGA0 0xA0 | AXINDP << 29 +#define SB_AX_INDXP_REGA4 0xA4 | AXINDP << 29 +#define SB_AX_INDXP_REGB1 0xB1 | AXINDP << 29 + +#define SB_AX_CFG_REG88 0x88 | AXCFG << 29 + +#define AX_INDXC 0 +#define AX_INDXP 1 +#define SB_AB_REG04 0x04 +#define SB_AB_REG40 0x40 + +#define RC_INDXC_REG40 0x40 | RCINDXC << 29 +#define RC_INDXC_REG65 0x65 | RCINDXC << 29 + +// +// SATA Device 0x4390 (IDE) +// 0x4391 (AHCI) +// 0x4392 (AHCI/RAID Promise with RAID driver) +// 0x4393 (RAID5) +// 0x4394/0x4395 (SATA HyperFlash OneNand support/SATA HyperFlash-PCIe support) +// Device 17 (0x11) Func 0 +// +//Sata Controller Mode +#define NATIVE_IDE_MODE 0 +#define RAID_MODE 1 +#define AHCI_MODE 2 +#define LEGACY_IDE_MODE 3 +#define IDE_TO_AHCI_MODE 4 +#define AHCI_MODE_4394 5 +#define IDE_TO_AHCI_MODE_4394 6 + +//Sata Port Configuration +#define SIX_PORTS 0 +#define FOUR_PORTS 1 + +#define SATA_EFUSE_LOCATION 0x10 // EFUSE bit 133 +#define SATA_FIS_BASE_EFUSE_LOC 0x15 // EFUSE bit 169 +#define SATA_EFUSE_BIT 0x20 // +#define SB_SATA_REG00 0x000 // Vendor ID - R- 16 bits +#define SB_SATA_REG02 0x002 // Device ID - RW -16 bits +#define SB_SATA_REG04 0x004 // PCI Command - RW - 16 bits +#define SB_SATA_REG06 0x006 // PCI Status - RW - 16 bits +#define SB_SATA_REG08 0x008 // Revision ID/PCI Class Code - R - 32 bits - Offset: 08 +#define SB_SATA_REG0C 0x00C // Cache Line Size - R/W - 8bits +#define SB_SATA_REG0D 0x00D // Latency Timer - RW - 8 bits +#define SB_SATA_REG0E 0x00E // Header Type - R - 8 bits +#define SB_SATA_REG0F 0x00F // BIST - R - 8 bits +#define SB_SATA_REG10 0x010 // Base Address Register 0 - RW - 32 bits +#define SB_SATA_REG14 0x014 // Base Address Register 1 - RW- 32 bits +#define SB_SATA_REG18 0x018 // Base Address Register 2 - RW - 32 bits +#define SB_SATA_REG1C 0x01C // Base Address Register 3 - RW - 32 bits +#define SB_SATA_REG20 0x020 // Base Address Register 4 - RW - 32 bits +#define SB_SATA_REG24 0x024 // Base Address Register 5 - RW - 32 bits +#define SB_SATA_REG2C 0x02C // Subsystem Vendor ID - R - 16 bits +#define SB_SATA_REG2D 0x02D // Subsystem ID - R - 16 bits +#define SB_SATA_REG30 0x030 // Expansion ROM Base Address - 32 bits +#define SB_SATA_REG34 0x034 // Capabilities Pointer - R - 32 bits +#define SB_SATA_REG3C 0x03C // Interrupt Line - RW - 8 bits +#define SB_SATA_REG3D 0x03D // Interrupt Pin - R - 8 bits +#define SB_SATA_REG3E 0x03E // Min Grant - R - 8 bits +#define SB_SATA_REG3F 0x03F // Max Latency - R - 8 bits +#define SB_SATA_REG40 0x040 // Configuration - RW - 32 bits +#define SB_SATA_REG44 0x044 // Software Data Register - RW - 32 bits +#define SB_SATA_REG48 0x048 +#define SB_SATA_REG50 0x050 // Message Capability - R - 16 bits +#define SB_SATA_REG52 0x052 // Message Control - R/W - 16 bits +#define SB_SATA_REG54 0x054 // Message Address - R/W - 32 bits +#define SB_SATA_REG58 0x058 // Message Data - R/W - 16 bits +#define SB_SATA_REG5C 0x05C // RAMBIST Control Register - R/W - 8 bits +#define SB_SATA_REG5D 0x05D // RAMBIST Status0 Register - R - 8 bits +#define SB_SATA_REG5E 0x05E // RAMBIST Status1 Register - R - 8 bits +#define SB_SATA_REG60 0x060 // Power Management Capabilities - R - 32 bits +#define SB_SATA_REG64 0x064 // Power Management Control + Status - RW - 32 bits +#define SB_SATA_REG68 0x068 // MSI Program - R/W - 8 bits +#define SB_SATA_REG69 0x069 // PCI Burst Timer - R/W - 8 bits +#define SB_SATA_REG70 0x070 // PCI Bus Master - IDE0 - RW - 32 bits +#define SB_SATA_REG74 0x074 // PRD Table Address - IDE0 - RW - 32 bits +#define SB_SATA_REG78 0x078 // PCI Bus Master - IDE1 - RW - 32 bits +#define SB_SATA_REG7C 0x07C // PRD Table Address - IDE1 - RW - 32 bits +#define SB_SATA_REG80 0x080 // Data Transfer Mode - IDE0 - RW - 32 bits +#define SB_SATA_REG84 0x084 // Data Transfer Mode - IDE1 - RW - 32 bits +#define SB_SATA_REG86 0x086 // PY Global Control +#define SB_SATA_REG87 0x087 +#define SB_SATA_REG88 0x088 // PHY Port0 Control - Port0 PY fine tune (0:23) +#define SB_SATA_REG8A 0x08A +#define SB_SATA_REG8C 0x08C // PHY Port1 Control - Port0 PY fine tune (0:23) +#define SB_SATA_REG8E 0x08E +#define SB_SATA_REG90 0x090 // PHY Port2 Control - Port0 PY fine tune (0:23) +#define SB_SATA_REG92 0x092 +#define SB_SATA_REG94 0x094 // PHY Port3 Control - Port0 PY fine tune (0:23) +#define SB_SATA_REG96 0x096 +#define SB_SATA_REG98 0x098 // EEPROM Memory Address - Command + Status - RW - 32 bits +#define SB_SATA_REG9C 0x09C // EEPROM Memory Data - RW - 32 bits +#define SB_SATA_REGA0 0x0A0 // +#define SB_SATA_REGA4 0x0A4 // +#define SB_SATA_REGA5 0x0A5 //; +#define SB_SATA_REGA8 0x0A8 // +#define SB_SATA_REGAD 0x0AD //; +#define SB_SATA_REGB0 0x0B0 // IDE1 Task File Configuration + Status - RW - 32 bits +#define SB_SATA_REGB5 0x0B5 //; +#define SB_SATA_REGBD 0x0BD //; +#define SB_SATA_REGC0 0x0C0 // BA5 Indirect Address - RW - 32 bits +#define SB_SATA_REGC4 0x0C4 // BA5 Indirect Access - RW - 32 bits + +#define SB_SATA_BAR5_REG00 0x000 // PCI Bus Master - IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG04 0x004 // PRD Table Address - IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG08 0x008 // PCI Bus Master - IDE1 - RW - 32 bits +#define SB_SATA_BAR5_REG0C 0x00C // PRD Table Address - IDE1 - RW - 32 bits +#define SB_SATA_BAR5_REG10 0x010 // PCI Bus Master2 - IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG18 0x018 // PCI Bus Master2 - IDE1 - RW - 32 bits +#define SB_SATA_BAR5_REG20 0x020 // PRD Address - IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG24 0x024 // PCI Bus Master Byte Count - IDE0- RW - 32 bits +#define SB_SATA_BAR5_REG28 0x028 // PRD Address - IDE1 - RW - 32 bits +#define SB_SATA_BAR5_REG2C 0x02C // PCI Bus Master Byte Count - IDE1 - RW - 32 bits +#define SB_SATA_BAR5_REG40 0x040 // FIFO Valid Byte Count and Control - IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG44 0x044 // FIFO Valid Byte Count and Control - IDE1 - RW - 32 bits +#define SB_SATA_BAR5_REG48 0x048 // System Configuration Status - Command - RW - 32 bits +#define SB_SATA_BAR5_REG4C 0x04C // System Software Data Register - RW - 32 bits +#define SB_SATA_BAR5_REG50 0x050 // FLAS Memory Address - Command + Status - RW - 32 bits +#define SB_SATA_BAR5_REG54 0x054 // FLAS Memory Data - RW - 32 bits +#define SB_SATA_BAR5_REG58 0x058 // EEPROM Memory Address - Command + Status - RW - 32 bits +#define SB_SATA_BAR5_REG5C 0x05C // EEPROM Memory Data - RW - 32 bits +#define SB_SATA_BAR5_REG60 0x060 // FIFO Port - IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG68 0x068 // FIFO Pointers1- IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG6C 0x06C // FIFO Pointers2- IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG70 0x070 // FIFO Port - IDE1- RW - 32 bits +#define SB_SATA_BAR5_REG78 0x078 // FIFO Pointers1- IDE1- RW - 32 bits +#define SB_SATA_BAR5_REG7C 0x07C // FIFO Pointers2- IDE1- RW - 32 bits +#define SB_SATA_BAR5_REG80 0x080 // IDE0 Task File Register 0- RW - 32 bits +#define SB_SATA_BAR5_REG84 0x084 // IDE0 Task File Register 1- RW - 32 bits +#define SB_SATA_BAR5_REG88 0x088 // IDE0 Task File Register 2- RW - 32 bits +#define SB_SATA_BAR5_REG8C 0x08C // IDE0 Read Data - RW - 32 bits +#define SB_SATA_BAR5_REG90 0x090 // IDE0 Task File Register 0 - Command Buffering - RW - 32 bits +#define SB_SATA_BAR5_REG94 0x094 // IDE0 Task File Register 1 - Command Buffering - RW - 32 bits +#define SB_SATA_BAR5_REG9C 0x09C // IDE0 Virtual DMA/PIO Read Byte Count - RW - 32 bits +#define SB_SATA_BAR5_REGA0 0x0A0 // IDE0 Task File Configuration + Status - RW - 32 bits +#define SB_SATA_BAR5_REGB4 0x0B4 // Data Transfer Mode -IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REGC0 0x0C0 // IDE1 Task File Register 0 - RW - 32 bits +#define SB_SATA_BAR5_REGC4 0x0C4 // IDE1 Task File Register 1 - RW - 32 bits +#define SB_SATA_BAR5_REGC8 0x0C8 // IDE1 Task File Register 2 - RW - 32 bits +#define SB_SATA_BAR5_REGCC 0x0CC // Read/Write Data - RW - 32 bits +#define SB_SATA_BAR5_REGD0 0x0D0 // IDE1 Task File Register 0 - Command Buffering - RW - 32 bits +#define SB_SATA_BAR5_REGD4 0x0D4 // IDE1 Task File Register 1 - Command Buffering - RW - 32 bits +#define SB_SATA_BAR5_REGDC 0x0DC // IDE1 Virtual DMA/PIO Read Byte Count - RW - 32 bits +#define SB_SATA_BAR5_REGE0 0x0E0 // IDE1 Task File Configuration + Status - RW - 32 bits +#define SB_SATA_BAR5_REGF4 0x0F4 // Data Transfer Mode - IDE1 - RW - 32 bits +#define SB_SATA_BAR5_REGF8 0x0F8 // PORT Configuration +#define SB_SATA_BAR5_REGFC 0x0FC +#define SB_SATA_BAR5_REG100 0x0100 // Serial ATA SControl - RW - 32 bits - [Offset: 100h (channel 1) / 180 +#define SB_SATA_BAR5_REG104 0x0104 // Serial ATA Sstatus - RW - 32 bits - [Offset: 104h (channel 1) / 184h (cannel +#define SB_SATA_BAR5_REG108 0x0108 // Serial ATA Serror - RW - 32 bits - [Offset: 108h (channel 1) / 188h (cannel +#define SB_SATA_BAR5_REG10C 0x010C // Serial ATA Sdevice - RW - 32 bits - [Offset: 10Ch (channel 1) / 18Ch (cannel +#define SB_SATA_BAR5_REG144 0x0144 // Serial ATA PY Configuration - RW - 32 bits +#define SB_SATA_BAR5_REG148 0x0148 // SIEN - RW - 32 bits - [Offset: 148 (channel 1) / 1C8 (cannel 2)] +#define SB_SATA_BAR5_REG14C 0x014C // SFISCfg - RW - 32 bits - [Offset: 14C (channel 1) / 1CC (cannel 2)] +#define SB_SATA_BAR5_REG120 0x0120 // +#define SB_SATA_BAR5_REG128 0x0128 // Port Serial ATA Status +#define SB_SATA_BAR5_REG12C 0x012C // Port Serial ATA Control +#define SB_SATA_BAR5_REG130 0x0130 +#define SB_SATA_BAR5_REG1B0 0x01B0 +#define SB_SATA_BAR5_REG230 0x0230 +#define SB_SATA_BAR5_REG2B0 0x02B0 +#define SB_SATA_BAR5_REG330 0x0330 +#define SB_SATA_BAR5_REG3B0 0x03B0 + +// +// FC Device 0x439B +// Device 17 (0x11) Func 1 +// +#define SB_FC_REG00 0x00 // Device/Vendor ID - R +#define SB_FC_REG04 0x04 // Command - RW +#define SB_FC_REG10 0x10 // BAR + +#define SB_FC_MMIO_REG70 0x070 +#define SB_FC_MMIO_REG200 0x200 + +// +// USB OHCI Device 0x4397 +// Device 18 (0x11)/Device 19 (0x12)/Device 22 (0x16) Func 0 +// Device 20 (0x14) Func 5 (FL) +// +#define SB_OHCI_REG00 0x00 // Device/Vendor ID - R (0x43971002) +#define SB_OHCI_REG04 0x04 // Command - RW +#define SB_OHCI_REG06 0x06 // Status - R +#define SB_OHCI_REG08 0x08 // Revision ID/Class Code - R +#define SB_OHCI_REG0C 0x0C // Miscellaneous - RW +#define SB_OHCI_REG10 0x10 // Bar_OCI - RW +#define SB_OHCI_REG2C 0x2C // Subsystem Vendor ID/ Subsystem ID - RW +#define SB_OHCI_REG34 0x34 // Capability Pointer - R +#define SB_OHCI_REG3C 0x3C // Interrupt Line - RW +#define SB_OHCI_REG3D 0x3D // Interrupt Line - RW +#define SB_OHCI_REG40 0x40 // Config Timers - RW +#define SB_OHCI_REG42 0x42 // Port Disable Control - RW (800) +#define SB_OHCI_REG46 0x46 // USB PHY Battery Charger - RW (800) +#define SB_OHCI_REG48 0x48 // Port Force Reset - RW (800) +#define SB_OHCI_REG4C 0x4C // MSI - RW (800) +#define SB_OHCI_REG50 0x50 // Misc Control - RW +#define SB_OHCI_REG51 0x51 +#define SB_OHCI_REG52 0x52 +#define SB_OHCI_REG58 0x58 // Over Current Control - RW +#define SB_OHCI_REG5C 0x5C // Over Current Control - RW (800)?? +#define SB_OHCI_REG60 0x60 // Serial Bus Release Number - R (800)?? +#define SB_OHCI_REG68 0x68 // Over Current PME Enable - RW +#define SB_OHCI_REG74 0x74 // Target Timeout Control - RW (800) +#define SB_OHCI_REGD0 0x0D0 // MSI Control - RW +#define SB_OHCI_REGD4 0x0D4 // MSI Address - RW +#define SB_OHCI_REGD8 0x0D8 // MSI Data - RW +#define SB_OHCI_REGE4 0x0E4 // HT MSI Support +#define SB_OHCI_REGF0 0x0F0 // Function Level Reset Capability +#define SB_OHCI_REGF4 0x0F4 // Function Level Reset Control + +#define SB_OHCI_BAR_REG00 0x00 // cRevision - R +#define SB_OHCI_BAR_REG04 0x04 // cControl +#define SB_OHCI_BAR_REG08 0x08 // cCommandStatus +#define SB_OHCI_BAR_REG0C 0x0C // cInterruptStatus RW +#define SB_OHCI_BAR_REG10 0x10 // cInterruptEnable +#define SB_OHCI_BAR_REG14 0x14 // cInterruptDisable +#define SB_OHCI_BAR_REG18 0x18 // HcCCA +#define SB_OHCI_BAR_REG1C 0x1C // cPeriodCurrentED +#define SB_OHCI_BAR_REG20 0x20 // HcControleadED +#define SB_OHCI_BAR_REG24 0x24 // cControlCurrentED RW +#define SB_OHCI_BAR_REG28 0x28 // HcBulkeadED +#define SB_OHCI_BAR_REG2C 0x2C // cBulkCurrentED- RW +#define SB_OHCI_BAR_REG30 0x30 // HcDoneead +#define SB_OHCI_BAR_REG34 0x34 // cFmInterval +#define SB_OHCI_BAR_REG38 0x38 // cFmRemaining +#define SB_OHCI_BAR_REG3C 0x3C // cFmNumber +#define SB_OHCI_BAR_REG40 0x40 // cPeriodicStart +#define SB_OHCI_BAR_REG44 0x44 // HcLSThresold +#define SB_OHCI_BAR_REG48 0x48 // HcRDescriptorA +#define SB_OHCI_BAR_REG4C 0x4C // HcRDescriptorB +#define SB_OHCI_BAR_REG50 0x50 // HcRStatus +#define SB_OHCI_BAR_REG54 0x54 // HcRhPortStatus (800) +#define SB_OHCI_BAR_REG58 0x58 // HcRhPortStatus NPD (800) +#define SB_OHCI_BAR_REGF0 0xF0 // OHCI Loop Back feature Support (800) + +// +// USB EHCI Device 0x4396 +// Device 18 (0x11)/Device 19 (0x12)/Device 22 (0x16) Func 2 +// +#define SB_EHCI_REG00 0x00 // DEVICE/VENDOR ID - R +#define SB_EHCI_REG04 0x04 // Command - RW +#define SB_EHCI_REG06 0x06 // Status - R +#define SB_EHCI_REG08 0x08 // Revision ID/Class Code - R +#define SB_EHCI_REG0C 0x0C // Miscellaneous - RW +#define SB_EHCI_REG10 0x10 // BAR - RW +#define SB_EHCI_REG2C 0x2C // Subsystem ID/Subsystem Vendor ID - RW +#define SB_EHCI_REG34 0x34 // Capability Pointer - R +#define SB_EHCI_REG3C 0x3C // Interrupt Line - RW +#define SB_EHCI_REG3D 0x3D // Interrupt Line - RW ?? +#define SB_EHCI_REG40 0x40 // Config Timers - RW ?? +#define SB_EHCI_REG4C 0x4C // MSI - RW +#define SB_EHCI_REG50 0x50 // EHCI Misc Control - RW +#define SB_EHCI_REG54 0x54 // EHCI Misc Control - RW +#define SB_EHCI_REG60 0x60 // SBRN - R +#define SB_EHCI_REG61 0x61 // FLADJ - RW +#define SB_EHCI_REG62 0x62 // PORTWAKECAP - RW +#define SB_EHCI_REGC0 0x0C0 // PME control - RW (800) +#define SB_EHCI_REGC4 0x0C4 // PME Data /Status - RW (800) +#define SB_EHCI_REGD0 0x0D0 // MSI Control - RW +#define SB_EHCI_REGD4 0x0D4 // MSI Address - RW +#define SB_EHCI_REGD8 0x0D8 // MSI Data - RW +#define SB_EHCI_REGE4 0x0E4 // EHCI Debug Port Support - RW (800) +#define SB_EHCI_REGF0 0x0F0 // Function Level Reset Capability - R (800) +#define SB_EHCI_REGF4 0x0F4 // Function Level Reset Capability - R (800) + +#define SB_EHCI_BAR_REG00 0x00 // CAPLENGT - R +#define SB_EHCI_BAR_REG02 0x002 // CIVERSION- R +#define SB_EHCI_BAR_REG04 0x004 // CSPARAMS - R +#define SB_EHCI_BAR_REG08 0x008 // CCPARAMS - R +#define SB_EHCI_BAR_REG0C 0x00C // CSP-PORTROUTE - R + +#define SB_EHCI_BAR_REG20 0x020 // USBCMD - RW - 32 bits +#define SB_EHCI_BAR_REG24 0x024 // USBSTS - RW - 32 bits +#define SB_EHCI_BAR_REG28 0x028 // USBINTR -RW - 32 bits +#define SB_EHCI_BAR_REG2C 0x02C // FRINDEX -RW - 32 bits +#define SB_EHCI_BAR_REG30 0x030 // CTRLDSSEGMENT -RW - 32 bits +#define SB_EHCI_BAR_REG34 0x034 // PERIODICLISTBASE -RW - 32 bits +#define SB_EHCI_BAR_REG38 0x038 // ASYNCLISTADDR -RW - 32 bits +#define SB_EHCI_BAR_REG60 0x060 // CONFIGFLAG -RW - 32 bits +#define SB_EHCI_BAR_REG64 0x064 // PORTSC (1-N_PORTS) -RW - 32 bits +#define SB_EHCI_BAR_REGA0 0x0A0 // DebugPort MISC Control - RW - 32 bits (800) +#define SB_EHCI_BAR_REGA4 0x0A4 // Packet Buffer Threshold Values - RW - 32 bits +#define SB_EHCI_BAR_REGA8 0x0A8 // USB PHY Status 0 - R +#define SB_EHCI_BAR_REGAC 0x0AC // USB PHY Status 1 - R +#define SB_EHCI_BAR_REGB0 0x0B0 // USB PHY Status 2 - R +#define SB_EHCI_BAR_REGB4 0x0B4 // UTMI Control - RW (800) +#define SB_EHCI_BAR_REGB8 0x0B8 // Loopback Test +#define SB_EHCI_BAR_REGBC 0x0BC // EHCI MISC Control +#define SB_EHCI_BAR_REGC0 0x0C0 // USB PHY Calibration +#define SB_EHCI_BAR_REGC4 0x0C4 // USB Common PHY Control +#define SB_EHCI_BAR_REGC8 0x0C8 // EHCI Debug Purpose +#define SB_EHCI_BAR_REGCC 0x0CC // Ehci Spare 1 (800) ** +#define SB_EHCI_BAR_REG100 0x100 // USB debug port + +// +// SB800 SB CFG device 0x4385 +// Device 20 (0x14) Func 0 +// +#define SB_CFG_REG00 0x000 // VendorID - R +#define SB_CFG_REG02 0x002 // DeviceID - R +#define SB_CFG_REG04 0x004 // Command- RW +#define SB_CFG_REG05 0x005 // Command- RW +#define SB_CFG_REG06 0x006 // STATUS- RW +#define SB_CFG_REG08 0x008 // Revision ID/Class Code- R +#define SB_CFG_REG0A 0x00A // +#define SB_CFG_REG0B 0x00B // +#define SB_CFG_REG0C 0x00C // Cache Line Size- R +#define SB_CFG_REG0D 0x00D // Latency Timer- R +#define SB_CFG_REG0E 0x00E // Header Type- R +#define SB_CFG_REG0F 0x00F // BIST- R +#define SB_CFG_REG10 0x010 // Base Address 0- R +#define SB_CFG_REG11 0x011 //; +#define SB_CFG_REG12 0x012 //; +#define SB_CFG_REG13 0x013 //; +#define SB_CFG_REG14 0x014 // Base Address 1- R +#define SB_CFG_REG18 0x018 // Base Address 2- R +#define SB_CFG_REG1C 0x01C // Base Address 3- R +#define SB_CFG_REG20 0x020 // Base Address 4- R +#define SB_CFG_REG24 0x024 // Base Address 5- R +#define SB_CFG_REG28 0x028 // Cardbus CIS Pointer- R +#define SB_CFG_REG2C 0x02C // Subsystem Vendor ID- W +#define SB_CFG_REG2E 0x02E // Subsystem ID- W +#define SB_CFG_REG30 0x030 // Expansion ROM Base Address - R +#define SB_CFG_REG34 0x034 // Capability Pointer - R (800) default changed as 0x00 +#define SB_CFG_REG3C 0x03C // Interrupt Line - R +#define SB_CFG_REG3D 0x03D // Interrupt Pin - R +#define SB_CFG_REG3E 0x03E // Min_Gnt - R +#define SB_CFG_REG3F 0x03F // Max_Lat - R +#define SB_CFG_REG90 0x090 // Smbus Base Address - R +#define SB_CFG_REG9C 0x09C // SBResourceMMIO_BASE + +// +// SB800 SATA IDE device 0x439C +// Device 20 (0x14) Func 1 +// + +#define SB_IDE_REG00 0x00 // Vendor ID +#define SB_IDE_REG02 0x02 // Device ID +#define SB_IDE_REG04 0x04 // Command +#define SB_IDE_REG06 0x06 // Status +#define SB_IDE_REG08 0x08 // Revision ID/Class Code +#define SB_IDE_REG09 0x09 // Class Code +#define SB_IDE_REG2C 0x2C // Subsystem ID and Subsystem Vendor ID +#define SB_IDE_REG34 0x34 +#define SB_IDE_REG40 0x40 // Configuration - RW - 32 bits +#define SB_IDE_REG62 0x62 // IDE Internal Control +#define SB_IDE_REG63 0x63 // IDE Internal Control +// +// SB800 AZALIA device 0x4383 +// Device 20 (0x14) Func 2 +// +#define ATI_AZALIA_ExtBlk_Addr 0x0F8 +#define ATI_AZALIA_ExtBlk_DATA 0x0FC + +#define SB_AZ_REG00 0x00 // Vendor ID - R +#define SB_AZ_REG02 0x02 // Device ID - R/W +#define SB_AZ_REG04 0x04 // PCI Command +#define SB_AZ_REG06 0x06 // PCI Status - R/W +#define SB_AZ_REG08 0x08 // Revision ID +#define SB_AZ_REG09 0x09 // Programming Interface +#define SB_AZ_REG0A 0x0A // Sub Class Code +#define SB_AZ_REG0B 0x0B // Base Class Code +#define SB_AZ_REG0C 0x0C // Cache Line Size - R/W +#define SB_AZ_REG0D 0x0D // Latency Timer +#define SB_AZ_REG0E 0x0E // Header Type +#define SB_AZ_REG0F 0x0F // BIST +#define SB_AZ_REG10 0x10 // Lower Base Address Register +#define SB_AZ_REG14 0x14 // Upper Base Address Register +#define SB_AZ_REG2C 0x2C // Subsystem Vendor ID +#define SB_AZ_REG2D 0x2D // Subsystem ID +#define SB_AZ_REG34 0x34 // Capabilities Pointer +#define SB_AZ_REG3C 0x3C // Interrupt Line +#define SB_AZ_REG3D 0x3D // Interrupt Pin +#define SB_AZ_REG3E 0x3E // Minimum Grant +#define SB_AZ_REG3F 0x3F // Maximum Latency +#define SB_AZ_REG40 0x40 // Misc Control 1 +#define SB_AZ_REG42 0x42 // Misc Control 2 Register +#define SB_AZ_REG43 0x43 // Misc Control 3 Register +#define SB_AZ_REG44 0x44 // Interrupt Pin Control Register +#define SB_AZ_REG46 0x46 // Debug Control Register +#define SB_AZ_REG4C 0x4C +#define SB_AZ_REG50 0x50 // Power Management Capability ID +#define SB_AZ_REG52 0x52 // Power Management Capabilities +#define SB_AZ_REG54 0x54 // Power Management Control/Status +#define SB_AZ_REG60 0x60 // MSI Capability ID +#define SB_AZ_REG62 0x62 // MSI Message Control +#define SB_AZ_REG64 0x64 // MSI Message Lower Address +#define SB_AZ_REG68 0x68 // MSI Message Upper Address +#define SB_AZ_REG6C 0x6C // MSI Message Data + +#define SB_AZ_BAR_REG00 0x00 // Global Capabilities - R +#define SB_AZ_BAR_REG02 0x02 // Minor Version - R +#define SB_AZ_BAR_REG03 0x03 // Major Version - R +#define SB_AZ_BAR_REG04 0x04 // Output Payload Capability - R +#define SB_AZ_BAR_REG06 0x06 // Input Payload Capability - R +#define SB_AZ_BAR_REG08 0x08 // Global Control - R/W +#define SB_AZ_BAR_REG0C 0x0C // Wake Enable - R/W +#define SB_AZ_BAR_REG0E 0x0E // State Change Status - R/W +#define SB_AZ_BAR_REG10 0x10 // Global Status - R/W +#define SB_AZ_BAR_REG18 0x18 // Output Stream Payload Capability - R +#define SB_AZ_BAR_REG1A 0x1A // Input Stream Payload Capability - R +#define SB_AZ_BAR_REG20 0x20 // Interrupt Control - R/W +#define SB_AZ_BAR_REG24 0x24 // Interrupt Status - R/W +#define SB_AZ_BAR_REG30 0x30 // Wall Clock Counter - R +#define SB_AZ_BAR_REG38 0x38 // Stream Synchronization - R/W +#define SB_AZ_BAR_REG40 0x40 // CORB Lower Base Address - R/W +#define SB_AZ_BAR_REG44 0x44 // CORB Upper Base Address - RW +#define SB_AZ_BAR_REG48 0x48 // CORB Write Pointer - R/W +#define SB_AZ_BAR_REG4A 0x4A // CORB Read Pointer - R/W +#define SB_AZ_BAR_REG4C 0x4C // CORB Control - R/W +#define SB_AZ_BAR_REG4D 0x4D // CORB Status - R/W +#define SB_AZ_BAR_REG4E 0x4E // CORB Size - R/W +#define SB_AZ_BAR_REG50 0x50 // RIRB Lower Base Address - RW +#define SB_AZ_BAR_REG54 0x54 // RIRB Upper Address - RW +#define SB_AZ_BAR_REG58 0x58 // RIRB Write Pointer - RW +#define SB_AZ_BAR_REG5A 0x5A // RIRB Response Interrupt Count - R/W +#define SB_AZ_BAR_REG5C 0x5C // RIRB Control - R/W +#define SB_AZ_BAR_REG5D 0x5D // RIRB Status - R/W +#define SB_AZ_BAR_REG5E 0x5E // RIRB Size - R/W +#define SB_AZ_BAR_REG60 0x60 // Immediate Command Output Interface - R/W +#define SB_AZ_BAR_REG64 0x64 // Immediate Command Input Interface - R/W +#define SB_AZ_BAR_REG68 0x68 // Immediate Command Input Interface - R/W +#define SB_AZ_BAR_REG70 0x70 // DMA Position Lower Base Address - R/W +#define SB_AZ_BAR_REG74 0x74 // DMA Position Upper Base Address - R/W +#define SB_AZ_BAR_REG2030 0x2030 // Wall Clock Counter Alias - R + +// +// SB800 LPC Device 0x439D +// Device 20 (0x14) Func 3 +// +#define SB_LPC_REG00 0x00 // VID- R +#define SB_LPC_REG02 0x02 // DID- R +#define SB_LPC_REG04 0x04 // CMD- RW +#define SB_LPC_REG06 0x06 // STATUS- RW +#define SB_LPC_REG08 0x08 // Revision ID/Class Code - R +#define SB_LPC_REG0C 0x0C // Cache Line Size - R +#define SB_LPC_REG0D 0x0D // Latency Timer - R +#define SB_LPC_REG0E 0x0E // Header Type - R +#define SB_LPC_REG0F 0x0F // BIST- R +#define SB_LPC_REG10 0x10 // Base Address Reg 0- RW* +#define SB_LPC_REG2C 0x2C // Subsystem ID & Subsystem Vendor ID - Wo/Ro +#define SB_LPC_REG34 0x34 // Capabilities Pointer - Ro +#define SB_LPC_REG40 0x40 // PCI Control - RW +#define SB_LPC_REG44 0x44 // IO Port Decode Enable Register 1- RW +#define SB_LPC_REG45 0x45 // IO Port Decode Enable Register 2- RW +#define SB_LPC_REG46 0x46 // IO Port Decode Enable Register 3- RW +#define SB_LPC_REG47 0x47 // IO Port Decode Enable Register 4- RW +#define SB_LPC_REG48 0x48 // IO/Mem Port Decode Enable Register 5- RW +#define SB_LPC_REG49 0x49 // LPC Sync Timeout Count - RW +#define SB_LPC_REG4A 0x4A // IO/Mem Port Decode Enable Register 6- RW +#define SB_LPC_REG4C 0x4C // Memory Range Register - RW +#define SB_LPC_REG50 0x50 // Rom Protect 0 - RW +#define SB_LPC_REG54 0x54 // Rom Protect 1 - RW +#define SB_LPC_REG58 0x58 // Rom Protect 2 - RW +#define SB_LPC_REG5C 0x5C // Rom Protect 3 - RW +#define SB_LPC_REG60 0x60 // PCI Memory Start Address of LPC Target Cycles - +#define SB_LPC_REG62 0x62 // PCI Memory End Address of LPC Target Cycles - +#define SB_LPC_REG64 0x64 // PCI IO base Address of Wide Generic Port - RW +#define SB_LPC_REG65 0x65 +#define SB_LPC_REG66 0x66 +#define SB_LPC_REG67 0x67 +#define SB_LPC_REG68 0x68 // LPC ROM Address Range 1 (Start Address) - RW +#define SB_LPC_REG69 0x69 +#define SB_LPC_REG6A 0x6A // LPC ROM Address Range 1 (End Address) - RW +#define SB_LPC_REG6B 0x6B +#define SB_LPC_REG6C 0x6C // LPC ROM Address Range 2 (Start Address)- RW +#define SB_LPC_REG6D 0x6D +#define SB_LPC_REG6E 0x6E // LPC ROM Address Range 2 (End Address) - RW +#define SB_LPC_REG6F 0x6F +#define SB_LPC_REG70 0x70 // Firmware ub Select - RW* +#define SB_LPC_REG71 0x71 +#define SB_LPC_REG72 0x72 +#define SB_LPC_REG73 0x73 +#define SB_LPC_REG74 0x74 // Alternative Wide IO Range Enable- W/R +#define SB_LPC_REG78 0x78 // Miscellaneous Control Bits- W/R +#define SB_LPC_REG7C 0x7C // TPM (trusted plant form module) reg- W/R +#define SB_LPC_REG9C 0x9C +#define SB_LPC_REG80 0x80 // MSI Capability Register- R +#define SB_LPC_REGA0 0x0A0 // SPI base address +#define SB_LPC_REGA1 0x0A1 // SPI base address +#define SB_LPC_REGA2 0x0A2 // SPI base address +#define SB_LPC_REGA3 0x0A3 // SPI base address +#define SB_LPC_REGA4 0x0A4 +#define SB_LPC_REGBA 0x0BA // EcControl +#define SB_LPC_REGBB 0x0BB // HostControl + +// +// SB800 PCIB 0x4384 +// Device 20 (0x14) Func 4 +// +#define SB_PCIB_REG04 0x04 // Command +#define SB_PCIB_REG0D 0x0D // Primary Master Latency Timer +#define SB_PCIB_REG1B 0x1B // Secondary Latency Timer +#define SB_PCIB_REG1C 0x1C // IO Base +#define SB_PCIB_REG1D 0x1D // IO Limit +#define SB_PCIB_REG40 0x40 // CPCTRL +#define SB_PCIB_REG42 0x42 // CLKCTRL +#define SB_PCIB_REG48 0x48 // +#define SB_PCIB_REG4A 0x4A // PCICLK Enable Bits +#define SB_PCIB_REG4B 0x4B // Misc Control +#define SB_PCIB_REG4C 0x4C // AutoClockRun Control +#define SB_PCIB_REG50 0x50 // Dual Address Cycle Enable and PCIB_CLK_Stop Override +#define SB_PCIB_REG65 0x65 // Misc Control +#define SB_PCIB_REG66 0x66 // Misc Control +// +// SB800 NIC 0x4384 +// Device 20 (0x14) Func 6 (Func5 OHCI FL device) +// +#define SB_GEC_REG04 0x04 // Command +#define SB_GEC_REG10 0x10 // GEC BAR + +// +// SB800 SB MMIO Base (SMI) +// offset : 0x200 +// +#define SB_SMI_REG00 0x00 // EventStatus +#define SB_SMI_REG04 0x04 // EventEnable +#define SB_SMI_REG08 0x08 // SciTrig +#define SB_SMI_REG0C 0x0C // SciLevl +#define SB_SMI_REG10 0x10 // SmiSciStatus +#define SB_SMI_REG14 0x14 // SmiSciEn +#define SB_SMI_REG18 0x18 // ForceSciEn +#define SB_SMI_REG1C 0x1C // SciRwData +#define SB_SMI_REG20 0x20 // SciS0En +#define SB_SMI_Gevent0 0x40 // SciMap0 +#define SB_SMI_Gevent1 0x41 // SciMap1 +#define SB_SMI_Gevent2 0x42 // SciMap2 +#define SB_SMI_Gevent3 0x43 // SciMap3 +#define SB_SMI_Gevent4 0x44 // SciMap4 +#define SB_SMI_Gevent5 0x45 // SciMap5 +#define SB_SMI_Gevent6 0x46 // SciMap6 +#define SB_SMI_Gevent7 0x47 // SciMap7 +#define SB_SMI_Gevent8 0x48 // SciMap8 +#define SB_SMI_Gevent9 0x49 // SciMap9 +#define SB_SMI_Gevent10 0x4A // SciMap10 +#define SB_SMI_Gevent11 0x4B // SciMap11 +#define SB_SMI_Gevent12 0x4C // SciMap12 +#define SB_SMI_Gevent13 0x4D // SciMap13 +#define SB_SMI_Gevent14 0x4E // SciMap14 +#define SB_SMI_Gevent15 0x4F // SciMap15 +#define SB_SMI_Gevent16 0x50 // SciMap16 +#define SB_SMI_Gevent17 0x51 // SciMap17 +#define SB_SMI_Gevent18 0x52 // SciMap18 +#define SB_SMI_Gevent19 0x53 // SciMap19 +#define SB_SMI_Gevent20 0x54 // SciMap20 +#define SB_SMI_Gevent21 0x55 // SciMap21 +#define SB_SMI_Gevent22 0x56 // SciMap22 +#define SB_SMI_Gevent23 0x57 // SciMap23 +#define SB_SMI_Usbwakup0 0x58 // SciMap24 +#define SB_SMI_Usbwakup1 0x59 // SciMap25 +#define SB_SMI_Usbwakup2 0x5A // SciMap26 +#define SB_SMI_Usbwakup3 0x5B // SciMap27 +#define SB_SMI_SBGppPme0 0x5C // SciMap28 +#define SB_SMI_SBGppPme1 0x5D // SciMap29 +#define SB_SMI_SBGppPme2 0x5E // SciMap30 +#define SB_SMI_SBGppPme3 0x5F // SciMap31 +#define SB_SMI_SBGppHp0 0x60 // SciMap32 +#define SB_SMI_SBGppHp1 0x61 // SciMap33 +#define SB_SMI_SBGppHp2 0x62 // SciMap34 +#define SB_SMI_SBGppHp3 0x63 // SciMap35 +#define SB_SMI_AzaliaPme 0x64 // SciMap36 +#define SB_SMI_SataGevent0 0x65 // SciMap37 +#define SB_SMI_SataGevent1 0x66 // SciMap38 +#define SB_SMI_GecPme 0x67 // SciMap39 +#define SB_SMI_IMCGevent0 0x68 // SciMap40 +#define SB_SMI_IMCGevent1 0x69 // SciMap41 +#define SB_SMI_CIRPme 0x6A // SciMap42 +#define SB_SMI_WakePinGevent 0x6B // SciMap43 +#define SB_SMI_FanThGevent 0x6C // SciMap44 //FanThermalGevent +#define SB_SMI_ASFMasterIntr 0x6D // SciMap45 +#define SB_SMI_ASFSlaveIntr 0x6E // SciMap46 +#define SB_SMI_SMBUS0 0x6F // SciMap47 +#define SB_SMI_TWARN 0x70 // SciMap48 +#define SB_SMI_TMI 0x71 // SciMap49 // TrafficMonitorIntr + +// Empty from 0x72-0x7F +//#Define SB_SMI_REG7C 0x7F // SciMap63 *** + +#define SB_SMI_REG80 0x80 // SmiStatus0 +#define SB_SMI_REG84 0x84 // SmiStatus1 +#define SB_SMI_REG88 0x88 // SmiStatus2 +#define SB_SMI_REG8C 0x8C // SmiStatus3 +#define SB_SMI_REG90 0x90 // SmiStatus4 +#define SB_SMI_REG94 0x94 // SmiPointer +#define SB_SMI_REG96 0x96 // SmiTimer +#define SB_SMI_REG98 0x98 // SmiTrig +#define SB_SMI_REG9C 0x9C // SmiTrig +#define SB_SMI_REGA0 0xA0 +#define SB_SMI_REGA1 0xA1 +#define SB_SMI_REGA2 0xA2 +#define SB_SMI_REGA3 0xA3 +#define SB_SMI_REGA4 0xA4 +#define SB_SMI_REGA5 0xA5 +#define SB_SMI_REGA6 0xA6 +#define SB_SMI_REGA7 0xA7 +#define SB_SMI_REGA8 0xA8 +#define SB_SMI_REGA9 0xA9 +#define SB_SMI_REGAA 0xAA +#define SB_SMI_REGAB 0xAB +#define SB_SMI_REGAC 0xAC +#define SB_SMI_REGAD 0xAD +#define SB_SMI_REGAE 0xAE +#define SB_SMI_REGAF 0xAF +#define SB_SMI_REGB0 0xB0 +#define SB_SMI_REGB1 0xB1 +#define SB_SMI_REGB2 0xB2 +#define SB_SMI_REGB3 0xB3 +#define SB_SMI_REGB4 0xB4 +#define SB_SMI_REGB5 0xB5 +#define SB_SMI_REGB6 0xB6 +#define SB_SMI_REGB7 0xB7 +#define SB_SMI_REGB8 0xB8 +#define SB_SMI_REGB9 0xB9 +#define SB_SMI_REGBA 0xBA +#define SB_SMI_REGBB 0xBB +#define SB_SMI_REGBC 0xBC +#define SB_SMI_REGBD 0xBD +#define SB_SMI_REGBE 0xBE +#define SB_SMI_REGBF 0xBF +#define SB_SMI_REGC0 0xC0 +#define SB_SMI_REGC1 0xC1 +#define SB_SMI_REGC2 0xC2 +#define SB_SMI_REGC3 0xC3 +#define SB_SMI_REGC4 0xC4 +#define SB_SMI_REGC5 0xC5 +#define SB_SMI_REGC6 0xC6 +#define SB_SMI_REGC7 0xC7 +#define SB_SMI_REGC8 0xC8 +#define SB_SMI_REGCA 0xCA // IoTrapping1 +#define SB_SMI_REGCC 0xCC // IoTrapping2 +#define SB_SMI_REGCE 0xCE // IoTrapping3 +#define SB_SMI_REGD0 0xD0 // MemTrapping0 +#define SB_SMI_REGD4 0xD4 // MemRdOvrData0 +#define SB_SMI_REGD8 0xD8 // MemTrapping1 +#define SB_SMI_REGDC 0xDC // MemRdOvrData1 +#define SB_SMI_REGE0 0xE0 // MemTrapping2 +#define SB_SMI_REGE4 0xE4 // MemRdOvrData2 +#define SB_SMI_REGE8 0xE8 // MemTrapping3 +#define SB_SMI_REGEC 0xEC // MemRdOvrData3 +#define SB_SMI_REGF0 0xF0 // CfgTrapping0 +#define SB_SMI_REGF4 0xF4 // CfgTrapping1 +#define SB_SMI_REGF8 0xF8 // CfgTrapping2 +#define SB_SMI_REGFC 0xFC // CfgTrapping3 + +// +// SB800 SB MMIO Base (PMIO) +// offset : 0x300 +// +#define SB_PMIOA_REG00 0x00 // ISA Decode +#define SB_PMIOA_REG04 0x04 // ISA Control +#define SB_PMIOA_REG08 0x08 // PCI Control +#define SB_PMIOA_REG0C 0x0C // StpClkSmaf +#define SB_PMIOA_REG10 0x10 // RetryDetect +#define SB_PMIOA_REG14 0x14 // StuckDetect +#define SB_PMIOA_REG20 0x20 // BiosRamEn +#define SB_PMIOA_REG24 0x24 // AcpiMmioEn +#define SB_PMIOA_REG28 0x28 // AsfEn +#define SB_PMIOA_REG2C 0x2C // Smbus0En +#define SB_PMIOA_REG34 0x34 // IoApicEn +#define SB_PMIOA_REG3C 0x3C // SmartVoltEn +#define SB_PMIOA_REG40 0x40 // SmartVolt2En +#define SB_PMIOA_REG44 0x44 // BootTimerEn +#define SB_PMIOA_REG48 0x48 // WatchDogTimerEn +#define SB_PMIOA_REG4C 0x4C // WatchDogTimerConfig +#define SB_PMIOA_REG50 0x50 // HPETEn +#define SB_PMIOA_REG54 0x54 // SerialIrqConfig +#define SB_PMIOA_REG56 0x56 // RtcControl +#define SB_PMIOA_REG58 0x58 // VRT_T1 +#define SB_PMIOA_REG59 0x59 // VRT_T2 +#define SB_PMIOA_REG5A 0x5A // IntruderControl +#define SB_PMIOA_REG5B 0x5B // RtcShadow +#define SB_PMIOA_REG5C 0x5C +#define SB_PMIOA_REG5D 0x5D +#define SB_PMIOA_REG5E 0x5E // RtcExtIndex +#define SB_PMIOA_REG5F 0x5F // RtcExtData +#define SB_PMIOA_REG60 0x60 // AcpiPm1EvtBlk +#define SB_PMIOA_REG62 0x62 // AcpiPm1CntBlk +#define SB_PMIOA_REG64 0x64 // AcpiPmTmrBlk +#define SB_PMIOA_REG66 0x66 // P_CNTBlk +#define SB_PMIOA_REG68 0x68 // AcpiGpe0Blk +#define SB_PMIOA_REG6A 0x6A // AcpiSmiCmd +#define SB_PMIOA_REG6C 0x6C // AcpiPm2CntBlk +#define SB_PMIOA_REG6E 0x6E // AcpiPmaCntBlk +#define SB_PMIOA_REG74 0x74 // AcpiConfig +#define SB_PMIOA_REG78 0x78 // WakeIoAddr +#define SB_PMIOA_REG7A 0x7A // HaltCountEn +#define SB_PMIOA_REG7C 0x7C // C1eWrPortAdr +#define SB_PMIOA_REG7E 0x7E // CStateEn +#define SB_PMIOA_REG80 0x80 // BreakEvent +#define SB_PMIOA_REG84 0x84 // AutoArbEn +#define SB_PMIOA_REG88 0x88 // CStateControl +#define SB_PMIOA_REG8C 0x8C // StpClkHoldTime +#define SB_PMIOA_REG8E 0x8E // PopUpEndTime +#define SB_PMIOA_REG90 0x90 // C4Control +#define SB_PMIOA_REG94 0x94 // CStateTiming0 +#define SB_PMIOA_REG98 0x98 // CStateTiming1 +#define SB_PMIOA_REG9C 0x9C // C2Count +#define SB_PMIOA_REG9D 0x9D // C3Count +#define SB_PMIOA_REG9E 0x9E // C4Count +#define SB_PMIOA_REGA0 0xA0 // MessageCState +#define SB_PMIOA_REGA4 0xA4 // +#define SB_PMIOA_REGA8 0xA8 // TrafficMonitorIdleTime +#define SB_PMIOA_REGAA 0xAA // TrafficMonitorIntTime +#define SB_PMIOA_REGAC 0xAC // TrafficMonitorTrafficCount +#define SB_PMIOA_REGAE 0xAE // TrafficMonitorIntrCount +#define SB_PMIOA_REGB0 0xB0 // TrafficMonitorTimeTick +#define SB_PMIOA_REGB4 0xB4 // FidVidControl +#define SB_PMIOA_REGB6 0xB6 // TPRESET1 +#define SB_PMIOA_REGB7 0xB7 // Tpreset1b +#define SB_PMIOA_REGB8 0xB8 // TPRESET2 +#define SB_PMIOA_REGB9 0xB9 // Test0 +#define SB_PMIOA_REGBA 0xBA // S_StateControl +#define SB_PMIOA_REGBC 0xBC // ThrottlingControl +#define SB_PMIOA_REGBE 0xBE // ResetControl +#define SB_PMIOA_REGBF 0xBF // ResetControl +#define SB_PMIOA_REGC0 0xC0 // S5Status +#define SB_PMIOA_REGC2 0xC2 // ResetStatus +#define SB_PMIOA_REGC4 0xC4 // ResetCommand +#define SB_PMIOA_REGC5 0xC5 // CF9Shadow +#define SB_PMIOA_REGC6 0xC6 // HTControl +#define SB_PMIOA_REGC8 0xC8 // Misc +#define SB_PMIOA_REGCC 0xCC // IoDrvSth +#define SB_PMIOA_REGD0 0xD0 // CLKRunEn +#define SB_PMIOA_REGD2 0xD2 // PmioDebug +#define SB_PMIOA_REGD6 0xD6 // IMCGating +#define SB_PMIOA_REGD8 0xD8 // MiscIndex +#define SB_PMIOA_REGD9 0xD9 // MiscData +#define SB_PMIOA_REGDA 0xDA // SataConfig +#define SB_PMIOA_REGDC 0xDC // HyperFlashConfig +#define SB_PMIOA_REGDE 0xDE // ABConfig +#define SB_PMIOA_REGE0 0xE0 // ABRegBar +#define SB_PMIOA_REGE6 0xE6 // FcEn +#define SB_PMIOA_REGEA 0xEA // PcibConfig +#define SB_PMIOA_REGEB 0xEB // AzEn +#define SB_PMIOA_REGEC 0xEC // LpcGating +#define SB_PMIOA_REGED 0xED // UsbGating +#define SB_PMIOA_REGEF 0xEF // UsbEnable +#define SB_PMIOA_REGF0 0xF0 // UsbControl +#define SB_PMIOA_REGF3 0xF3 // UsbDebug +#define SB_PMIOA_REGF6 0xF6 // GecEn +#define SB_PMIOA_REGF8 0xF8 // GecConfig +#define SB_PMIOA_REGFC 0xFC // TraceMemoryEn + +// +// SB800 SB MMIO Base (PMIO2) +// offset : 0x400 +// +#define SB_PMIO2_REG00 0x00 // Fan0InputControl +#define SB_PMIO2_REG01 0x01 // Fan0Control +#define SB_PMIO2_REG02 0x02 // Fan0Freq +#define SB_PMIO2_REG03 0x03 // LowDuty0 +#define SB_PMIO2_REG04 0x04 // MidDuty0 + +#define SB_PMIO2_REG10 0x00 // Fan1InputControl +#define SB_PMIO2_REG11 0x01 // Fan1Control +#define SB_PMIO2_REG12 0x02 // Fan1Freq +#define SB_PMIO2_REG13 0x03 // LowDuty1 +#define SB_PMIO2_REG14 0x04 // MidDuty1 + +#define SB_PMIO2_REG 0xFC // TraceMemoryEn + + +// +// SB800 SB MMIO Base (GPIO/IoMux) +// offset : 0x100/0xD00 +// +/* +GPIO from 0 ~ 67, (GEVENT 0-23) 128 ~ 150, 160 ~ 226. +*/ +#define SB_GPIO_REG00 0x00 +#define SB_GPIO_REG32 0x20 +#define SB_GPIO_REG33 0x21 +#define SB_GPIO_REG34 0x22 +#define SB_GPIO_REG35 0x23 +#define SB_GPIO_REG36 0x24 +#define SB_GPIO_REG37 0x25 +#define SB_GPIO_REG38 0x26 +#define SB_GPIO_REG39 0x27 +#define SB_GPIO_REG40 0x28 +#define SB_GPIO_REG41 0x29 +#define SB_GPIO_REG42 0x2A +#define SB_GPIO_REG43 0x2B +#define SB_GPIO_REG44 0x2C +#define SB_GPIO_REG45 0x2D +#define SB_GPIO_REG46 0x2E +#define SB_GPIO_REG47 0x2F +#define SB_GPIO_REG48 0x30 +#define SB_GPIO_REG49 0x31 +#define SB_GPIO_REG50 0x32 +#define SB_GPIO_REG51 0x33 +#define SB_GPIO_REG52 0x34 +#define SB_GPIO_REG53 0x35 +#define SB_GPIO_REG54 0x36 +#define SB_GPIO_REG55 0x37 +#define SB_GPIO_REG56 0x38 +#define SB_GPIO_REG57 0x39 +#define SB_GPIO_REG58 0x3A +#define SB_GPIO_REG59 0x3B +#define SB_GPIO_REG60 0x3C +#define SB_GPIO_REG61 0x3D +#define SB_GPIO_REG62 0x3E +#define SB_GPIO_REG63 0x3F +#define SB_GPIO_REG64 0x40 +#define SB_GPIO_REG65 0x41 +#define SB_GPIO_REG66 0x42 +#define SB_GPIO_REG67 0x43 + +#define SB_GEVENT_REG00 0x60 +#define SB_GEVENT_REG01 0x61 +#define SB_GEVENT_REG02 0x62 +#define SB_GEVENT_REG03 0x63 +#define SB_GEVENT_REG04 0x64 +#define SB_GEVENT_REG05 0x65 +#define SB_GEVENT_REG06 0x66 +#define SB_GEVENT_REG07 0x67 +#define SB_GEVENT_REG08 0x68 +#define SB_GEVENT_REG09 0x69 +#define SB_GEVENT_REG10 0x6A +#define SB_GEVENT_REG11 0x6B +#define SB_GEVENT_REG12 0x6C +#define SB_GEVENT_REG13 0x6D +#define SB_GEVENT_REG14 0x6E +#define SB_GEVENT_REG15 0x6F +#define SB_GEVENT_REG16 0x70 +#define SB_GEVENT_REG17 0x71 +#define SB_GEVENT_REG18 0x72 +#define SB_GEVENT_REG19 0x73 +#define SB_GEVENT_REG20 0x74 +#define SB_GEVENT_REG21 0x75 +#define SB_GEVENT_REG22 0x76 +#define SB_GEVENT_REG23 0x77 +// S5-DOMAIN GPIO +#define SB_GPIO_REG160 0xA0 +#define SB_GPIO_REG161 0xA1 +#define SB_GPIO_REG162 0xA2 +#define SB_GPIO_REG163 0xA3 +#define SB_GPIO_REG164 0xA4 +#define SB_GPIO_REG165 0xA5 +#define SB_GPIO_REG166 0xA6 +#define SB_GPIO_REG167 0xA7 +#define SB_GPIO_REG168 0xA8 +#define SB_GPIO_REG169 0xA9 +#define SB_GPIO_REG170 0xAA +#define SB_GPIO_REG171 0xAB +#define SB_GPIO_REG172 0xAC +#define SB_GPIO_REG173 0xAD +#define SB_GPIO_REG174 0xAE +#define SB_GPIO_REG175 0xAF +#define SB_GPIO_REG176 0xB0 +#define SB_GPIO_REG177 0xB1 +#define SB_GPIO_REG178 0xB2 +#define SB_GPIO_REG179 0xB3 +#define SB_GPIO_REG180 0xB4 +#define SB_GPIO_REG181 0xB5 +#define SB_GPIO_REG182 0xB6 +#define SB_GPIO_REG183 0xB7 +#define SB_GPIO_REG184 0xB8 +#define SB_GPIO_REG185 0xB9 +#define SB_GPIO_REG186 0xBA +#define SB_GPIO_REG187 0xBB +#define SB_GPIO_REG188 0xBC +#define SB_GPIO_REG189 0xBD +#define SB_GPIO_REG190 0xBE +#define SB_GPIO_REG191 0xBF +#define SB_GPIO_REG192 0xC0 +#define SB_GPIO_REG193 0xC1 +#define SB_GPIO_REG194 0xC2 +#define SB_GPIO_REG195 0xC3 +#define SB_GPIO_REG196 0xC4 +#define SB_GPIO_REG197 0xC5 +#define SB_GPIO_REG198 0xC6 +#define SB_GPIO_REG199 0xC7 +#define SB_GPIO_REG200 0xC8 +#define SB_GPIO_REG201 0xC9 +#define SB_GPIO_REG202 0xCA +#define SB_GPIO_REG203 0xCB +#define SB_GPIO_REG204 0xCC +#define SB_GPIO_REG205 0xCD +#define SB_GPIO_REG206 0xCE +#define SB_GPIO_REG207 0xCF +#define SB_GPIO_REG208 0xD0 +#define SB_GPIO_REG209 0xD1 +#define SB_GPIO_REG210 0xD2 +#define SB_GPIO_REG211 0xD3 +#define SB_GPIO_REG212 0xD4 +#define SB_GPIO_REG213 0xD5 +#define SB_GPIO_REG214 0xD6 +#define SB_GPIO_REG215 0xD7 +#define SB_GPIO_REG216 0xD8 +#define SB_GPIO_REG217 0xD9 +#define SB_GPIO_REG218 0xDA +#define SB_GPIO_REG219 0xDB +#define SB_GPIO_REG220 0xDC +#define SB_GPIO_REG221 0xDD +#define SB_GPIO_REG222 0xDE +#define SB_GPIO_REG223 0xDF +#define SB_GPIO_REG224 0xF0 +#define SB_GPIO_REG225 0xF1 +#define SB_GPIO_REG226 0xF2 +#define SB_GPIO_REG227 0xF3 +#define SB_GPIO_REG228 0xF4 + +// +// SB800 SB MMIO Base (SMBUS) +// offset : 0xA00 +// +#define SB_SMBUS_REG12 0x12 // I2CbusConfig + +// +// SB800 SB MMIO Base (MISC) +// offset : 0xE00 +// +#define SB_MISC_REG00 0x00 // ClkCntrl0 +/* +SB_MISC_REG00 EQU 000h + ClkCntrl0 EQU 0FFFFFFFFh +*/ +#define SB_MISC_REG04 0x04 // ClkCntrl1 +/* +SB_MISC_REG04 EQU 004h + ClkCntrl1 EQU 0FFFFFFFFh +*/ +#define SB_MISC_REG08 0x08 // ClkCntrl2 +/* +SB_MISC_REG08 EQU 008h + ClkCntrl2 EQU 0FFFFFFFFh +*/ +#define SB_MISC_REG0C 0x0C // ClkCntrl3 +/* +SB_MISC_REG0C EQU 00Ch + ClkCntrl3 EQU 0FFFFFFFFh +*/ +#define SB_MISC_REG10 0x10 // ClkCntrl4 +/* +SB_MISC_REG10 EQU 010h + ClkCntrl4 EQU 0FFFFFFFFh +*/ +#define SB_MISC_REG14 0x14 // ClkCntrl5 +/* +SB_MISC_REG14 EQU 014h + ClkCntrl5 EQU 0FFFFFFFFh +*/ +#define SB_MISC_REG18 0x18 // ClkCntrl6 +/* +SB_MISC_REG18 EQU 018h + ClkCntrl6 EQU 0FFFFFFFFh +*/ +#define SB_MISC_REG30 0x30 // OscFreqCounter +/* +SB_MISC_REG30 EQU 030h + OscCounter EQU 0FFFFFFFFh ; The 32bit register shows the number of OSC clock per second. +*/ +#define SB_MISC_REG34 0x34 // HpetClkPeriod +/* +SB_MISC_REG34 EQU 034h + HpetClkPeriod EQU 0FFFFFFFFh ; default - 0x429B17Eh (14.31818M). +*/ +#define SB_MISC_REG40 0x40 // MiscCntrl for clock only +/* +SB_MISC_REG40 EQU 040h +*/ + +#define SB_MISC_REG80 0x80 /**< SB_MISC_REG80 + * @par + * StrapStatus [15.0] - SB800 chip Strap Status + * @li <b>0001</b> - Not USED FWH + * @li <b>0002</b> - Not USED LPC ROM + * @li <b>0004</b> - EC enabled + * @li <b>0008</b> - Reserved + * @li <b>0010</b> - Internal Clock mode + */ + +#define ChipSysNotUseFWHRom 0x0001 // EcPwm3 pad +#define ChipSysNotUseLpcRom 0x0002 // Inverted version from EcPwm2 pad (default - 1) + // Note: Both EcPwm3 and EcPwm2 straps pins are used to select boot ROM type. +#define ChipSysEcEnable 0x0004 // Enable Embedded Controller (EC) +#define ChipSysBootFailTmrEn 0x0008 // Enable Watchdog function +#define ChipSysIntClkGen 0x0010 // Select 25Mhz crystal clock or 100Mhz PCI-E clock ** + +#define SB_MISC_REG84 0x84 // StrapOverride +/* +SB_MISC_REG84 EQU 084h + Override FWHDisableStrap EQU BIT0 ; Override FWHDiableStrap value from external pin. + Override UseLpcRomStrap EQU BIT1 ; Override UseLpcRomStrap value from external pin. + Override EcEnableStrap EQU BIT2 ; Override EcEnableStrap value from external pin. + Override BootFailTmrEnStrap EQU BIT3 ; Override BootFailTmrEnStrap value from external pin. + Override DefaultModeStrap EQU BIT5 ; Override DefaultModeStrap value from external pin. + Override I2CRomStrap EQU BIT7 ; Override I2CRomStrap value from external pin. + Override ILAAutorunEnBStrap EQU BIT8 ; Override ILAAutorunEnBStrap value from external pin. + Override FcPllBypStrap EQU BIT9 ; Override FcPllBypStrap value from external pin. + Override PciPllBypStrap EQU BIT10 ; Override PciPllBypStrap value from external pin. + Override ShortResetStrap EQU BIT11 ; Override ShortResetStrap value from external pin. + Override FastBif2ClkStrap EQU BIT13 ; Override FastBif2ClkStrap value from external pin' + PciRomBootStrap EQU BIT15 ; Override PCI Rom Boot Strap value from external pin ?? Not match 0x80 reg ?? + BlinkSlowModestrap EQU BIT16 ; Override Blink Slow mode (100Mhz) from external pin' + ClkGenStrap EQU BIT17 ; Override CLKGEN from external pin. + BIF_GEN2_COMPL_Strap EQU BIT18 ; Override BIF_ GEN2_COMPLIANCE strap from external pin. + StrapOverrideEn EQU BIT31 ; Enable override strapping feature. +*/ +#define SB_MISC_REGC0 0xC0 // CPU_Pstate0 +/* +SB_MISC_REGC0 EQU 0C0h + Core0_PState EQU BIT0+BIT1+BIT2 ; 000: P0 001: P1 010: P2 011: P3 100: P4 101: P5 110: P6 111: P7 + Core1_PState EQU BIT4+BIT5+BIT6 + Core2_PState EQU BIT8+BIT9+BIT10 + Core3_PState EQU BIT12+BIT13+BIT14 + Core4_PState EQU BIT16++BIT17+BIT18 + Core5_PState EQU BIT20+BIT21+BIT22 + Core6_PState EQU BIT24+BIT25+BIT26 + Core7_PState EQU BIT28+BIT29+BIT30 +*/ +#define SB_MISC_REGC4 0xC4 // CPU_Pstate1 +/* +SB_MISC_REGC4 EQU 0C4h + Core8_PState EQU BIT0+BIT1+BIT2 ; 000: P0 001: P1 010: P2 011: P3 100: P4 101: P5 110: P6 111: P7 + Core9_PState EQU BIT4+BIT5+BIT6 + Core10_PState EQU BIT8+BIT9+BIT10 + Core11_PState EQU BIT12+BIT13+BIT14 + Core12_PState EQU BIT16++BIT17+BIT18 + Core13_PState EQU BIT20+BIT21+BIT22 + Core14_PState EQU BIT24+BIT25+BIT26 + Core15_PState EQU BIT28+BIT29+BIT30 +*/ +#define SB_MISC_REGD0 0xD0 // CPU_Cstate0 +/* +SB_MISC_REGD0 EQU 0D0h + Core0_CState EQU BIT0+BIT1+BIT2 ; 000: C0 001: C1 010: C2 011: C3 100: C4 101: C5 110: C6 111: C7 + Core1_CState EQU BIT4+BIT5+BIT6 + Core2_CState EQU BIT8+BIT9+BIT10 + Core3_CState EQU BIT12+BIT13+BIT14 + Core4_CState EQU BIT16++BIT17+BIT18 + Core5_CState EQU BIT20+BIT21+BIT22 + Core6_CState EQU BIT24+BIT25+BIT26 + Core7_CState EQU BIT28+BIT29+BIT30 +*/ +#define SB_MISC_REGD4 0xD4 // CPU_Cstate1 +/* +SB_MISC_REGD4 EQU 0D4h + Core8_CState EQU BIT0+BIT1+BIT2 ; 000: C0 001: C1 010: C2 011: C3 100: C4 101: C5 110: C6 111: C7 + Core9_CState EQU BIT4+BIT5+BIT6 + Core10_CState EQU BIT8+BIT9+BIT10 + Core11_CState EQU BIT12+BIT13+BIT14 + Core12_CState EQU BIT16++BIT17+BIT18 + Core13_CState EQU BIT20+BIT21+BIT22 + Core14_CState EQU BIT24+BIT25+BIT26 + Core15_CState EQU BIT28+BIT29+BIT30 +*/ +#define SB_MISC_REGF0 0xF0 // SataPortSts ?? EC touch only +/* +SB_MISC_REGF0 EQU 0F0h + Port0Sts EQU BIT0 ; The selected status of Port 0. + Port1Sts EQU BIT1 ; The selected status of Port 1 + Port2Sts EQU BIT2 ; The selected status of Port 2. + Port3Sts EQU BIT3 ; The selected status of Port 3 + Port4Sts EQU BIT4 ; The selected status of Port 4. + Port5Sts EQU BIT5 ; The selected status of Port 5 + SataPortSel EQU BIT24+BIT25 ; 00 - Select "led" for Port 0 to 5 + ; 01 - Select "delete" for Port 0 to 5 + ; 10 - Select "err" for Port 0 to 5 + ; 11 - Select "led" for Port 0 to 5 +*/ + + + +#define SB_RTC_REG00 0x00 // Seconds - RW +#define SB_RTC_REG01 0x01 // Seconds Alarm - RW +#define SB_RTC_REG02 0x02 // Minutes - RW +#define SB_RTC_REG03 0x03 // Minutes Alarm - RW +#define SB_RTC_REG04 0x04 // ours - RW +#define SB_RTC_REG05 0x05 // ours Alarm- RW +#define SB_RTC_REG06 0x06 // Day of Week - RW +#define SB_RTC_REG07 0x07 // Date of Mont - RW +#define SB_RTC_REG08 0x08 // Mont - RW +#define SB_RTC_REG09 0x09 // Year - RW +#define SB_RTC_REG0A 0x0A // Register A - RW +#define SB_RTC_REG0B 0x0B // Register B - RW +#define SB_RTC_REG0C 0x0C // Register C - R +#define SB_RTC_REG0D 0x0D // DateAlarm - RW +#define SB_RTC_REG32 0x32 // AltCentury - RW +#define SB_RTC_REG48 0x48 // Century - RW +#define SB_RTC_REG50 0x50 // Extended RAM Address Port - RW +#define SB_RTC_REG53 0x53 // Extended RAM Data Port - RW +#define SB_RTC_REG7E 0x7E // RTC Time Clear - RW +#define SB_RTC_REG7F 0x7F // RTC RAM Enable - RW + +#define SB_ECMOS_REG00 0x00 // scratch - reg +//;BIT0=0 AsicDebug is enabled +//;BIT1=0 SLT S3 runs +#define SB_ECMOS_REG01 0x01 +#define SB_ECMOS_REG02 0x02 +#define SB_ECMOS_REG03 0x03 +#define SB_ECMOS_REG04 0x04 +#define SB_ECMOS_REG05 0x05 +#define SB_ECMOS_REG06 0x06 +#define SB_ECMOS_REG07 0x07 +#define SB_ECMOS_REG08 0x08 // save 32BIT Physical address of Config structure +#define SB_ECMOS_REG09 0x09 +#define SB_ECMOS_REG0A 0x0A +#define SB_ECMOS_REG0B 0x0B + +#define SB_ECMOS_REG0C 0x0C //;save MODULE_ID +#define SB_ECMOS_REG0D 0x0D //;Reserve for NB + +#define SB_IOMAP_REG00 0x000 // Dma_C 0 +#define SB_IOMAP_REG02 0x002 // Dma_C 1 +#define SB_IOMAP_REG04 0x004 // Dma_C 2 +#define SB_IOMAP_REG06 0x006 // Dma_C 3 +#define SB_IOMAP_REG08 0x008 // Dma_Status +#define SB_IOMAP_REG09 0x009 // Dma_WriteRest +#define SB_IOMAP_REG0A 0x00A // Dma_WriteMask +#define SB_IOMAP_REG0B 0x00B // Dma_WriteMode +#define SB_IOMAP_REG0C 0x00C // Dma_Clear +#define SB_IOMAP_REG0D 0x00D // Dma_MasterClr +#define SB_IOMAP_REG0E 0x00E // Dma_ClrMask +#define SB_IOMAP_REG0F 0x00F // Dma_AllMask +#define SB_IOMAP_REG20 0x020 // IntrCntrlReg1 +#define SB_IOMAP_REG21 0x021 // IntrCntrlReg2 +#define SB_IOMAP_REG40 0x040 // TimerC0 +#define SB_IOMAP_REG41 0x041 // TimerC1 +#define SB_IOMAP_REG42 0x042 // TimerC2 +#define SB_IOMAP_REG43 0x043 // Tmr1CntrlWord +#define SB_IOMAP_REG61 0x061 // Nmi_Status +#define SB_IOMAP_REG70 0x070 // Nmi_Enable +#define SB_IOMAP_REG71 0x071 // RtcDataPort +#define SB_IOMAP_REG72 0x072 // AlternatRtcAddrPort +#define SB_IOMAP_REG73 0x073 // AlternatRtcDataPort +#define SB_IOMAP_REG80 0x080 // Dma_Page_Reserved0 +#define SB_IOMAP_REG81 0x081 // Dma_PageC2 +#define SB_IOMAP_REG82 0x082 // Dma_PageC3 +#define SB_IOMAP_REG83 0x083 // Dma_PageC1 +#define SB_IOMAP_REG84 0x084 // Dma_Page_Reserved1 +#define SB_IOMAP_REG85 0x085 // Dma_Page_Reserved2 +#define SB_IOMAP_REG86 0x086 // Dma_Page_Reserved3 +#define SB_IOMAP_REG87 0x087 // Dma_PageC0 +#define SB_IOMAP_REG88 0x088 // Dma_Page_Reserved4 +#define SB_IOMAP_REG89 0x089 // Dma_PageC6 +#define SB_IOMAP_REG8A 0x08A // Dma_PageC7 +#define SB_IOMAP_REG8B 0x08B // Dma_PageC5 +#define SB_IOMAP_REG8C 0x08C // Dma_Page_Reserved5 +#define SB_IOMAP_REG8D 0x08D // Dma_Page_Reserved6 +#define SB_IOMAP_REG8E 0x08E // Dma_Page_Reserved7 +#define SB_IOMAP_REG8F 0x08F // Dma_Refres +#define SB_IOMAP_REG92 0x092 // FastInit +#define SB_IOMAP_REGA0 0x0A0 // IntrCntrl2Reg1 +#define SB_IOMAP_REGA1 0x0A1 // IntrCntrl2Reg2 +#define SB_IOMAP_REGC0 0x0C0 // Dma2_C4Addr +#define SB_IOMAP_REGC2 0x0C2 // Dma2_C4Cnt +#define SB_IOMAP_REGC4 0x0C4 // Dma2_C5Addr +#define SB_IOMAP_REGC6 0x0C6 // Dma2_C5Cnt +#define SB_IOMAP_REGC8 0x0C8 // Dma2_C6Addr +#define SB_IOMAP_REGCA 0x0CA // Dma2_C6Cnt +#define SB_IOMAP_REGCC 0x0CC // Dma2_C7Addr +#define SB_IOMAP_REGCE 0x0CE // Dma2_C7Cnt +#define SB_IOMAP_REGD0 0x0D0 // Dma_Status +#define SB_IOMAP_REGD2 0x0D2 // Dma_WriteRest +#define SB_IOMAP_REGD4 0x0D4 // Dma_WriteMask +#define SB_IOMAP_REGD6 0x0D6 // Dma_WriteMode +#define SB_IOMAP_REGD8 0x0D8 // Dma_Clear +#define SB_IOMAP_REGDA 0x0DA // Dma_Clear +#define SB_IOMAP_REGDC 0x0DC // Dma_ClrMask +#define SB_IOMAP_REGDE 0x0DE // Dma_ClrMask +#define SB_IOMAP_REGF0 0x0F0 // NCP_Error +#define SB_IOMAP_REG40B 0x040B // DMA1_Extend +#define SB_IOMAP_REG4D0 0x04D0 // IntrEdgeControl +#define SB_IOMAP_REG4D6 0x04D6 // DMA2_Extend +#define SB_IOMAP_REGC00 0x0C00 // Pci_Intr_Index +#define SB_IOMAP_REGC01 0x0C01 // Pci_Intr_Data +#define SB_IOMAP_REGC14 0x0C14 // Pci_Error +#define SB_IOMAP_REGC50 0x0C50 // CMIndex +#define SB_IOMAP_REGC51 0x0C51 // CMData +#define SB_IOMAP_REGC52 0x0C52 // GpmPort +#define SB_IOMAP_REGC6F 0x0C6F // Isa_Misc +#define SB_IOMAP_REGCD0 0x0CD0 // PMio2_Index +#define SB_IOMAP_REGCD1 0x0CD1 // PMio2_Data +#define SB_IOMAP_REGCD4 0x0CD4 // BIOSRAM_Index +#define SB_IOMAP_REGCD5 0x0CD5 // BIOSRAM_Data +#define SB_IOMAP_REGCD6 0x0CD6 // PM_Index +#define SB_IOMAP_REGCD7 0x0CD7 // PM_Data +#define SB_IOMAP_REGCF9 0x0CF9 // CF9Rst reg + + +#define SB_SPI_MMIO_REG00 0x00 //SPI_ +#define SB_SPI_MMIO_REG0C 0x0C //SPI_Cntrl1 Register + +#define AMD_NB_REG78 0x78 +#define AMD_NB_SCRATCH AMD_NB_REG78 +#define MailBoxPort 0x3E + +// GPP Link Configuration +#define GPP_CFGMODE_X4000 0x0 +#define GPP_CFGMODE_X2200 0x2 +#define GPP_CFGMODE_X2110 0x3 +#define GPP_CFGMODE_X1111 0x4 + +#define MAX_TRAINING_RETRY 0x4000 +#define MAX_GPP_RESETS 8 //lx-temp to confirm with jason + + +#pragma pack (pop) +
Added: trunk/src/vendorcode/amd/cimx/sb800/SBCMN.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/SBCMN.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,1058 @@ +/** + * @file + * + * Southbridge Initial routine + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: CIMx-SB + * @e sub-project: + * @e $Revision:$ @e $Date:$ + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" +// +// Declaration of local functions +// + +VOID abcfgTbl (IN ABTBLENTRY* pABTbl); + +/** + * sbUsbPhySetting - USB Phy Calibration Adjustment + * + * + * @param[in] Value Controller PCI config address (bus# + device# + function#) + * + */ +VOID sbUsbPhySetting (IN UINT32 Value); + + +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page LegacyInterfaceCalls Legacy Interface Calls + * <TD>@subpage SB_POWERON_INIT_Page "SB_POWERON_INIT"</TD><TD></TD> + * <TD>@subpage SB_BEFORE_PCI_INIT_Page "SB_BEFORE_PCI_INIT"</TD><TD></TD> + * <TD>@subpage SB_AFTER_PCI_INIT_Page "SB_AFTER_PCI_INIT"</TD><TD></TD> + * <TD>@subpage SB_LATE_POST_INIT_Page "SB_LATE_POST_INIT"</TD><TD></TD> + * <TD>@subpage SB_BEFORE_PCI_RESTORE_INIT_Page "SB_BEFORE_PCI_RESTORE_INIT"</TD><TD></TD> + * <TD>@subpage SB_AFTER_PCI_RESTORE_INIT_Page "SB_AFTER_PCI_RESTORE_INIT"</TD><TD></TD> + * <TD>@subpage SB_SMM_SERVICE_Page "SB_SMM_SERVICE"</TD><TD></TD> + * <TD>@subpage SB_SMM_ACPION_Page "SB_SMM_ACPION"</TD><TD></TD> + * + * @page LegacyInterfaceCallOuts Legacy Interface CallOuts + * <TD>@subpage CB_SBGPP_RESET_ASSERT_Page CB_SBGPP_RESET_ASSERT + * <TD>@subpage CB_SBGPP_RESET_DEASSERT_Page CB_SBGPP_RESET_DEASSERT + * +*/ + +/** + * sbEarlyPostByteInitTable - PCI device registers initial during early POST. + * + */ +REG8MASK sbEarlyPostByteInitTable[] = +{ + // SMBUS Device (Bus 0, Dev 20, Func 0) + {0x00, SMBUS_BUS_DEV_FUN, 0}, + {SB_CFG_REG10, 0X00, (SBCIMx_Version & 0xFF)}, //Program the version information + {SB_CFG_REG11, 0X00, (SBCIMx_Version >> 8)}, + {0xFF, 0xFF, 0xFF}, + + // IDE Device (Bus 0, Dev 20, Func 1) + {0x00, IDE_BUS_DEV_FUN, 0}, + {SB_IDE_REG62 + 1, ~BIT0, BIT5}, // Enabling IDE Explicit Pre-Fetch IDE PCI Config 0x62[8]=0 + // Allow MSI capability of IDE controller to be visible. IDE PCI Config 0x62[13]=1 + {0xFF, 0xFF, 0xFF}, + + // Azalia Device (Bus 0, Dev 20, Func 2) + {0x00, AZALIA_BUS_DEV_FUN, 0}, + {SB_AZ_REG4C, ~BIT0, BIT0}, + {0xFF, 0xFF, 0xFF}, + + // LPC Device (Bus 0, Dev 20, Func 3) + {0x00, LPC_BUS_DEV_FUN, 0}, + {SB_LPC_REG40, ~BIT2, BIT2}, // RPR 1.1 Enabling LPC DMA Function 0x40[2]=1b 0x78[0]=0b + {SB_LPC_REG78, ~BIT0, 00}, // RPR 1.1 Enabling LPC DMA Function 0x40[2]=1b 0x78[0]=0b + {SB_LPC_REG78, ~BIT1, 00}, // Disables MSI capability + {SB_LPC_REGBB, ~BIT0, BIT0 + BIT3 + BIT4 + BIT5}, // Enabled SPI Prefetch from HOST. + {0xFF, 0xFF, 0xFF}, + + // PCIB Bridge (Bus 0, Dev 20, Func 4) + {0x00, PCIB_BUS_DEV_FUN, 0}, + {SB_PCIB_REG40, 0xFF, BIT5}, // RPR PCI-bridge Subtractive Decode + {SB_PCIB_REG4B, 0xFF, BIT7}, // + {SB_PCIB_REG66, 0xFF, BIT4}, // RPR Enabling One-Prefetch-Channel Mode, PCIB_PCI_config 0x64 [20] + {SB_PCIB_REG65, 0xFF, BIT7}, // RPR proper operation of CLKRUN#. + {SB_PCIB_REG0D, 0x00, 0x40}, // Setting Latency Timers to 0x40, Enables the PCIB to retain ownership + {SB_PCIB_REG1B, 0x00, 0x40}, // of the bus on the Primary side and on the Secondary side when GNT# is deasserted. + {SB_PCIB_REG66 + 1, 0xFF, BIT1}, // RPR Enable PCI bus GNT3#.. + {0xFF, 0xFF, 0xFF}, + + // SATA Device (Bus 0, Dev 17, Func 0) + {0x00, SATA_BUS_DEV_FUN, 0}, + {SB_SATA_REG44, 0xff, BIT0}, // Enables the SATA watchdog timer register prior to the SATA BIOS post + {SB_SATA_REG44 + 2, 0, 0x20}, // RPR 8.12 SATA PCI Watchdog timer setting + // [SB01923] Set timer out to 0x20 to fix IDE to SATA Bridge dropping drive issue. + {0xFF, 0xFF, 0xFF}, +}; + + +/** + * sbPmioEPostInitTable - Southbridge ACPI MMIO initial during POST. + * + */ +AcpiRegWrite sbPmioEPostInitTable[] = +{ + // HPET workaround + {PMIO_BASE >> 8, SB_PMIOA_REG54 + 3, 0xFC, BIT0 + BIT1}, + {PMIO_BASE >> 8, SB_PMIOA_REG54 + 2, 0x7F, BIT7}, + {PMIO_BASE >> 8, SB_PMIOA_REG54 + 2, 0x7F, 0x00}, + // End of HPET workaround + // Enable SB800 A12 ACPI bits at PMIO 0xC0 [30,10:3] + // ClrAllStsInThermalEvent 3 Set to 1 to allow ASF remote power down/power cycle, Thermal event, Fan slow event to clear all the Gevent status and enabled bits. The bit should be set to 1 all the time. + // UsbGoodClkDlyEn 4 Set to 1 to delay de-assertion of Usb clk by 6 Osc clk. The bit should be set to 1 all the time. + // ForceNBCPUPwr 5 Set to 1 to force CPU pwrGood to be toggled along with NB pwrGood. + // MergeUsbPerReq 6 Set to 1 to merge usb perdical traffic into usb request as one of break event. + // IMCWatchDogRstEn 7 Set to 1 to allow IMC watchdog timer to reset entire acpi block. The bit should be set to 1 when IMC is enabled. + // GeventStsFixEn 8 1: Gevent status is not reset by its enable bit. 0: Gevent status is reset by its enable bit. + // PmeTimerFixEn 9 Set to 1 to reset Pme Timer when going to sleep state. + // UserRst2EcEn 10 Set to 1 to route user reset event to Ec. The bit should be set to 1 when IMC is enabled. + // Smbus0ClkSEn 30 Set to 1 to enable SMBus0 controller clock stretch support. + {PMIO_BASE >> 8, SB_PMIOA_REGC4, ~(BIT2 + BIT4), BIT2 + BIT4}, + {PMIO_BASE >> 8, SB_PMIOA_REGC0, 0, 0xF9}, + // PM_reg xC1 [3] = 1b, per RPR 2.7 CPU PwrGood Setting + {PMIO_BASE >> 8, SB_PMIOA_REGC0 + 1, 0x04, 0x0B}, + // RtcSts 19-17 RTC_STS set only in Sleep State. + // GppPme 20 Set to 1 to enable PME request from SB GPP. + // Pcireset 22 Set to 1 to allow SW to reset PCIe. + {PMIO_BASE >> 8, SB_PMIOA_REGC2, 0x20, 0x58}, + {PMIO_BASE >> 8, SB_PMIOA_REGC2 + 1, 0, 0x40}, + + //Item Id: SB02037: RTC_STS should be set in S state + //set PMIO 0xC0 [19:16] Set to 1110 to allow RTC_STS to be set only in non_G0 state. + //{PMIO_BASE >> 8, SB_PMIOA_REGC2, (UINT8)~(0x0F), 0x0E}, + + //Item Id: SB02034 + //Title: SB GPP NIC auto wake at second time sleep + //set PMIO 0xC4 bit 2 to 1 then set PMIO 0xC0 bit 20 to 1 to enable fix for SB02034 + + {PMIO_BASE >> 8, SB_PMIOA_REGC2, ~(BIT4), BIT4}, + + //{GPIO_BASE >> 8, SB_GPIO_REG62 , 0x00, 0x4E}, + {PMIO_BASE >> 8, SB_PMIOA_REG74, 0x00, BIT0 + BIT1 + BIT2 + BIT4}, + {PMIO_BASE >> 8, SB_PMIOA_REGDE + 1, ~(BIT0 + BIT1), BIT0 + BIT1}, + {PMIO_BASE >> 8, SB_PMIOA_REGDE, ~BIT4, BIT4}, + {PMIO_BASE >> 8, SB_PMIOA_REGBA, ~BIT3, BIT3}, + {PMIO_BASE >> 8, SB_PMIOA_REGBA + 1, ~BIT6, BIT6}, + {PMIO_BASE >> 8, SB_PMIOA_REGBC, ~BIT1, BIT1}, + {PMIO_BASE >> 8, SB_PMIOA_REGED, ~(BIT0 + BIT1), 0}, + //RPR Hiding Flash Controller PM_IO 0xDC[7] = 0x0 & PM_IO 0xDC [1:0]=0x01 + {PMIO_BASE >> 8, SB_PMIOA_REGDC, 0x7C, BIT0}, + // RPR Turning off FC clock + {MISC_BASE >> 8, SB_MISC_REG40 + 1, ~(BIT3 + BIT2), BIT3 + BIT2}, + {MISC_BASE >> 8, SB_MISC_REG40 + 2, ~BIT0, BIT0}, + {SMI_BASE >> 8, SB_SMI_Gevent0, 0, 29}, + {SMI_BASE >> 8, SB_SMI_Gevent1, 0, 1}, + {SMI_BASE >> 8, SB_SMI_Gevent2, 0, 29}, + {SMI_BASE >> 8, SB_SMI_Gevent3, 0, 29}, + {SMI_BASE >> 8, SB_SMI_Gevent4, 0, 4}, + {SMI_BASE >> 8, SB_SMI_Gevent5, 0, 5}, + {SMI_BASE >> 8, SB_SMI_Gevent6, 0, 6}, + {SMI_BASE >> 8, SB_SMI_Gevent7, 0, 29}, + + {SMI_BASE >> 8, SB_SMI_Gevent9, 0, 29}, + {SMI_BASE >> 8, SB_SMI_Gevent10, 0, 29}, + {SMI_BASE >> 8, SB_SMI_Gevent11, 0, 29}, + {SMI_BASE >> 8, SB_SMI_Gevent12, 0, 29}, + {SMI_BASE >> 8, SB_SMI_Gevent13, 0, 29}, + {SMI_BASE >> 8, SB_SMI_Gevent14, 0, 29}, + {SMI_BASE >> 8, SB_SMI_Gevent15, 0, 29}, + {SMI_BASE >> 8, SB_SMI_Gevent16, 0, 29}, + {SMI_BASE >> 8, SB_SMI_Gevent17, 0, 29}, + {SMI_BASE >> 8, SB_SMI_Gevent18, 0, 29}, + {SMI_BASE >> 8, SB_SMI_Gevent19, 0, 29}, + {SMI_BASE >> 8, SB_SMI_Gevent20, 0, 29}, + {SMI_BASE >> 8, SB_SMI_Gevent21, 0, 29}, + {SMI_BASE >> 8, SB_SMI_Gevent22, 0, 29}, + {SMI_BASE >> 8, SB_SMI_Gevent23, 0, 29}, +// + {SMI_BASE >> 8, SB_SMI_Usbwakup0, 0, 11}, + {SMI_BASE >> 8, SB_SMI_Usbwakup1, 0, 11}, + {SMI_BASE >> 8, SB_SMI_Usbwakup2, 0, 11}, + {SMI_BASE >> 8, SB_SMI_Usbwakup3, 0, 11}, + {SMI_BASE >> 8, SB_SMI_IMCGevent0, 0, 12}, + {SMI_BASE >> 8, SB_SMI_IMCGevent1, 0, 29}, + {SMI_BASE >> 8, SB_SMI_FanThGevent, 0, 13}, + {SMI_BASE >> 8, SB_SMI_SBGppPme0, 0, 15}, + {SMI_BASE >> 8, SB_SMI_SBGppPme1, 0, 16}, + {SMI_BASE >> 8, SB_SMI_SBGppPme2, 0, 17}, + {SMI_BASE >> 8, SB_SMI_SBGppPme3, 0, 18}, + {SMI_BASE >> 8, SB_SMI_SBGppHp0, 0, 29}, + {SMI_BASE >> 8, SB_SMI_SBGppHp1, 0, 29}, + {SMI_BASE >> 8, SB_SMI_SBGppHp2, 0, 29}, + {SMI_BASE >> 8, SB_SMI_SBGppHp3, 0, 29}, + {SMI_BASE >> 8, SB_SMI_GecPme, 0, 19}, + {SMI_BASE >> 8, SB_SMI_CIRPme, 0, 23}, + {SMI_BASE >> 8, SB_SMI_Gevent8, 0, 26}, + {SMI_BASE >> 8, SB_SMI_AzaliaPme, 0, 27}, + {SMI_BASE >> 8, SB_SMI_SataGevent0, 0, 30}, + {SMI_BASE >> 8, SB_SMI_SataGevent1, 0, 31}, + + {SMI_BASE >> 8, SB_SMI_WakePinGevent, 0, 29}, + {SMI_BASE >> 8, SB_SMI_ASFMasterIntr, 0, 29}, + {SMI_BASE >> 8, SB_SMI_ASFSlaveIntr, 0, 29}, + +// {SMI_BASE >> 8, SB_SMI_REG04, ~BIT4, BIT4}, +// {SMI_BASE >> 8, SB_SMI_REG04 + 1, ~BIT0, BIT0}, +// {SMI_BASE >> 8, SB_SMI_REG04 + 2, ~BIT3, BIT3}, + {SMI_BASE >> 8, SB_SMI_REG08, ~BIT4, 0}, + {SMI_BASE >> 8, SB_SMI_REG08+3, ~BIT2, 0}, +// {SMI_BASE >> 8, SB_SMI_REG0C, ~BIT4, BIT4}, + {SMI_BASE >> 8, SB_SMI_REG0C + 2, ~BIT3, BIT3}, + {SMI_BASE >> 8, SB_SMI_TWARN, 0, 9}, + {SMI_BASE >> 8, SB_SMI_TMI, 0, 29}, + {0xFF, 0xFF, 0xFF, 0xFF}, +}; + +/** + * abTblEntry800 - AB-Link Configuration Table for SB800 + * + */ +ABTBLENTRY abTblEntry800[] = +{ + // RPR Enable downstream posted transactions to pass non-posted transactions. + {ABCFG, SB_ABCFG_REG10090, BIT8 + BIT16, BIT8 + BIT16}, + + // RPR Enable SB800 to issue memory read/write requests in the upstream direction. + {AXCFG, SB_AB_REG04, BIT2, BIT2}, + + // RPR Enabling IDE/PCIB Prefetch for Performance Enhancement + // PCIB prefetch ABCFG 0x10060 [20] = 1 ABCFG 0x10064 [20] = 1 + {ABCFG, SB_ABCFG_REG10060, BIT20, BIT20}, // PCIB prefetch enable + {ABCFG, SB_ABCFG_REG10064, BIT20, BIT20}, // PCIB prefetch enable + + // RPR Controls the USB OHCI controller prefetch used for enhancing performance of ISO out devices. + // RPR Setting B-Link Prefetch Mode (ABCFG 0x80 [18:17] = 11) + {ABCFG, SB_ABCFG_REG80, BIT0 + BIT17 + BIT18, BIT0 + BIT17 + BIT18}, + + // RPR Enabled SMI ordering enhancement. ABCFG 0x90[21] + // RPR USB Delay A-Link Express L1 State. ABCFG 0x90[17] + {ABCFG, SB_ABCFG_REG90, BIT21 + BIT17, BIT21 + BIT17}, + + // RPR Disable the credit variable in the downstream arbitration equation + // RPR Register bit to qualify additional address bits into downstream register programming. (A12 BIT1 default is set) + {ABCFG, SB_ABCFG_REG9C, BIT0, BIT0}, + + // RPR Enabling Detection of Upstream Interrupts ABCFG 0x94 [20] = 1 + // ABCFG 0x94 [19:0] = cpu interrupt delivery address [39:20] + {ABCFG, SB_ABCFG_REG94, BIT20, BIT20 + 0x00FEE}, + + // RPR Programming cycle delay for AB and BIF clock gating + // RPR Enable the AB and BIF clock-gating logic. + // RPR Enable the A-Link int_arbiter enhancement to allow the A-Link bandwidth to be used more efficiently + // RPR Enable the requester ID for upstream traffic. [16]: SB/NB link [17]: GPP + {ABCFG, SB_ABCFG_REG10054, 0x00FFFFFF, 0x010407FF}, + {ABCFG, SB_ABCFG_REG98, 0xFFFF00FF, 0x00034700}, + {ABCFG, SB_ABCFG_REG54, 0x00FF0000, 0x00040000}, + // RPR Non-Posted Memory Write Support + {AX_INDXC, SB_AX_INDXC_REG10, BIT9, BIT9}, + {ABCFG, 0, 0, (UINT8) 0xFF}, // This dummy entry is to clear ab index + { (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF}, +}; + +/** + * SbPcieOrderRule - AB-Link Configuration Table for ablink Post Pass Np Downstream/Upstream Feature + * + */ +ABTBLENTRY SbPcieOrderRule[] = +{ +// abPostPassNpDownStreamTbl + {ABCFG, SB_ABCFG_REG10060, BIT31, BIT31}, + {ABCFG, SB_ABCFG_REG1009C, BIT4 + BIT5, BIT4 + BIT5}, + {ABCFG, SB_ABCFG_REG9C, BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7, BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7}, + {ABCFG, SB_ABCFG_REG90, BIT21 + BIT22 + BIT23, BIT21 + BIT22 + BIT23}, + {ABCFG, SB_ABCFG_REGF0, BIT6 + BIT5, BIT6 + BIT5}, + {AXINDC, SB_AX_INDXC_REG02, BIT9, BIT9}, + {ABCFG, SB_ABCFG_REG10090, BIT9 + BIT10 + BIT11 + BIT12, BIT9 + BIT10 + BIT11 + BIT12}, +// abPostPassNpUpStreamTbl + {ABCFG, SB_ABCFG_REG58, BIT10, BIT10}, + {ABCFG, SB_ABCFG_REGF0, BIT3 + BIT4, BIT3 + BIT4}, + {ABCFG, SB_ABCFG_REG54, BIT1, BIT1}, + { (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF}, +}; + +/** + * commonInitEarlyBoot - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB. + * + * This settings should be done during S3 resume also + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +commonInitEarlyBoot ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 abValue; + UINT16 dwTempVar; + SB_CPUID_DATA CpuId; + UINT8 cimNativepciesupport; + UINT8 cimIrConfig; + UINT8 Data; + + cimNativepciesupport = (UINT8) pConfig->NativePcieSupport; + cimIrConfig = (UINT8) pConfig->IrConfig; +#if SB_CIMx_PARAMETER == 0 + cimNativepciesupport = cimNativepciesupportDefault; + cimIrConfig = cimIrConfigDefault; +#endif + + //IR init Logical device 0x05 + if ( cimIrConfig ) { + // Enable EC_PortActive + RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4), AccWidthUint16 | S3_SAVE, 0xFFFE, BIT0); + EnterEcConfig (); + RWEC8 (0x07, 0x00, 0x05); //Select logical device 05, IR controller + RWEC8 (0x60, 0x00, 0x05); //Set Base Address to 550h + RWEC8 (0x61, 0x00, 0x50); + RWEC8 (0x70, 0xF0, 0x05); //Set IRQ to 05h + RWEC8 (0x30, 0x00, 0x01); //Enable logical device 5, IR controller + Data = 0xAB; + WriteIO (0x550, AccWidthUint8, &Data); + ReadIO (0x551, AccWidthUint8, &Data); + Data = ((Data & 0xFC ) | cimIrConfig); + WriteIO (0x551, AccWidthUint8, &Data); + ExitEcConfig (); + Data = 0xA0; // EC APIC index + WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &Data); + Data = 0x05; // IRQ5 + WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &Data); + } else { + EnterEcConfig (); + RWEC8 (0x07, 0x00, 0x05); //Select logical device 05, IR controller + RWEC8 (0x30, 0x00, 0x00); //Disable logical device 5, IR controller + ExitEcConfig (); + } + + + CpuidRead (0x01, &CpuId); + + // + // SB CFG programming + // + //Make BAR registers of smbus visible. + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, 0); + //Early post initialization of pci config space + programPciByteTable ((REG8MASK*) FIXUP_PTR (&sbEarlyPostByteInitTable[0]), sizeof (sbEarlyPostByteInitTable) / sizeof (REG8MASK) ); + if ( pConfig->BuildParameters.SmbusSsid != NULL ) { + RWPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.SmbusSsid); + } + //Make BAR registers of smbus invisible. + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, BIT6); + + // + // LPC CFG programming + // + // SSID for LPC Controller + if (pConfig->BuildParameters.LpcSsid != NULL ) { + RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.LpcSsid); + } + // LPC MSI + if ( pConfig->BuildParameters.LpcMsi) { + RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG78, AccWidthUint32 | S3_SAVE, ~BIT1, BIT1); + } + + // + // PCIB CFG programming + // + //Disable or Enable PCI Clks based on input + RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG42, AccWidthUint8 | S3_SAVE, ~(BIT5 + BIT4 + BIT3 + BIT2), ((pConfig->PciClks) & 0x0F) << 2 ); + RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG4A, AccWidthUint8 | S3_SAVE, ~(BIT1 + BIT0), (pConfig->PciClks) >> 4 ); + // PCIB MSI + if ( pConfig->BuildParameters.PcibMsi) { + RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG40, AccWidthUint8 | S3_SAVE, ~BIT3, BIT3); + } + + // + // AB CFG programming + // + // Read Arbiter address, Arbiter address is in PMIO 6Ch + ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6C, AccWidthUint16, &dwTempVar); + RWIO (dwTempVar, AccWidthUint8, 0, 0); // Write 0 to enable the arbiter + + abLinkInitBeforePciEnum (pConfig); // Set ABCFG registers + // AB MSI + if ( pConfig->BuildParameters.AbMsi) { + abValue = readAlink (SB_ABCFG_REG94 | (UINT32) (ABCFG << 29)); + abValue = abValue | BIT20; + writeAlink (SB_ABCFG_REG94 | (UINT32) (ABCFG << 29), abValue); + } + + + // + // SB Specific Function programming + // + + // PCIE Native setting + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGBA + 1, AccWidthUint8, ~BIT14, 0); + if ( pConfig->NativePcieSupport == 1) { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG74 + 3, AccWidthUint8, ~(BIT3 + BIT1 + BIT0), BIT2 + BIT0); + } else { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG74 + 3, AccWidthUint8, ~(BIT3 + BIT1 + BIT0), BIT2); + } + +#ifdef ACPI_SLEEP_TRAP + // Set SLP_TYPE as SMI event + RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGB0, AccWidthUint8, ~(BIT2 + BIT3), BIT2); + // Disabled SLP function for S1/S3/S4/S5 + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGBE, AccWidthUint8, ~BIT5, 0x00); + // Set S state transition disabled (BIT0) force ACPI to send SMI message when writing to SLP_TYP Acpi register. (BIT1) + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG08 + 3, AccWidthUint8, ~(BIT0 + BIT1), BIT1); + // Enabled Global Smi ( BIT7 clear as 0 to enable ) + RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REG98 + 3 , AccWidthUint8, ~BIT7, 0x00); +#endif + if ( pConfig->SbUsbPll == 0) { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF3, AccWidthUint8, 0, 0x20); + } + // Set Stutter timer settings + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80 + 1, AccWidthUint8, ~(BIT3 + BIT4), BIT3 + BIT4); + // Set LDTSTP# duration to 10us for HydraD CPU, or when HT link is 200MHz + if ((pConfig->AnyHT200MhzLink) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x100080) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x100090) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x1000A0)) { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94, AccWidthUint8, 0, 0x0A); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80 + 3, AccWidthUint8 | S3_SAVE, 0xFE, 0x28); + } else { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94, AccWidthUint8, 0, 0x01); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80 + 3, AccWidthUint8 | S3_SAVE, 0xFE, 0x20); + } + + //PM_Reg 0x7A[15] (CountHaltMsgEn) should be set when C1e option is enabled + //PM_Reg 0x7A[3:0] (NumOfCpu) should be set to 1h when C1e option is enabled + //PM_Reg 0x80[13] has to set to 1 to enable Message C scheme. + if (pConfig->MTC1e) { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7A, AccWidthUint16 | S3_SAVE, 0x7FF0, BIT15 + 1); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80 + 1, AccWidthUint8 | S3_SAVE, ~BIT5, BIT5); + } + + programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr)); +} + +/** + * abSpecialSetBeforePciEnum - Special setting ABCFG registers before PCI emulation. + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +abSpecialSetBeforePciEnum ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 abValue; + abValue = readAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29)); + abValue &= 0xf0; + if ( pConfig->SbPcieOrderRule && abValue ) { + abValue = readAlink (SB_RCINDXC_REG02 | (UINT32) (RCINDXC << 29)); + abValue = abValue | BIT9; + writeAlink (SB_RCINDXC_REG02 | (UINT32) (RCINDXC << 29), abValue); + } +} + +VOID +usbDesertPll ( + IN AMDSBCFG* pConfig + ) +{ + if ( pConfig->SbUsbPll == 0) { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF3, AccWidthUint8, 0, 0x00); + } +} + +/** + * commonInitEarlyPost - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB. + * + * This settings might not program during S3 resume + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +commonInitEarlyPost ( + IN AMDSBCFG* pConfig + ) +{ + UINT8 dbPortStatus; + UINT8 cimSpreadSpectrum; + UINT32 cimSpreadSpectrumType; + AMDSBCFG* pTmp; + pTmp = pConfig; + + cimSpreadSpectrum = pConfig->SpreadSpectrum; + cimSpreadSpectrumType = pConfig->BuildParameters.SpreadSpectrumType; +#if SB_CIMx_PARAMETER == 0 + cimSpreadSpectrum = cimSpreadSpectrumDefault; + cimSpreadSpectrumType = cimSpreadSpectrumTypeDefault; +#endif + programSbAcpiMmioTbl ((AcpiRegWrite*) FIXUP_PTR (&sbPmioEPostInitTable[0])); + + // CallBackToOEM (PULL_UP_PULL_DOWN_SETTINGS, NULL, pConfig); + + if ( cimSpreadSpectrum ) { + // Misc_Reg_40[25]=1 -> allow to change spread profile + // Misc_Reg19=83 -> new spread profile + // Misc_Reg[12:10]=9975be + // Misc_Reg0B=91 + // Misc_Reg09=21 + // Misc_Misc_Reg_08[0]=1 -> enable spread + RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x43, AccWidthUint8, ~BIT1, BIT1); + RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x19, AccWidthUint8, 0, 0x83); + getChipSysMode (&dbPortStatus); + if ( ((dbPortStatus & ChipSysIntClkGen) != ChipSysIntClkGen) ) { + RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x1A, AccWidthUint8, ~(BIT5 + BIT6 + BIT7), 0x80); + } + + if ( cimSpreadSpectrumType == 0 ) { + RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x12, AccWidthUint8, 0, 0x99); + RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x11, AccWidthUint8, 0, 0x75); + RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccWidthUint8, 0, 0xBE); + RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x0B, AccWidthUint8, 0, 0x91); + RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x09, AccWidthUint8, 0, 0x21); + } else { // Spread profile for Ontario CPU related platform + // This spread profile setting is for Ontario HDMI & DVI output from DP with -0.425% + // Misc_Reg[12:10]=828FA8 + // Misc_Reg0B=11 + // Misc_Reg09=21 + // Misc_Reg10[25:24]=01b + RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x12, AccWidthUint8, 0, 0x82); + RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x11, AccWidthUint8, 0, 0x8F); + RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccWidthUint8, 0, 0xA8); + RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x0B, AccWidthUint8, 0, 0x11); + RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x09, AccWidthUint8, 0, 0x21); + RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x13, AccWidthUint8, 0xFC, 0x1); + } + + RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG08, AccWidthUint8, 0xFE, 0x01); + } else { + RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG08, AccWidthUint8, 0xFE, 0x00); + } + + // RPR PLL 100Mhz Reference Clock Buffer setting for internal clock generator mode + getChipSysMode (&dbPortStatus); + if ( ((dbPortStatus & ChipSysIntClkGen) == ChipSysIntClkGen) ) { + RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG04 + 1, AccWidthUint8, ~BIT5, BIT5); + } + + // Set ASF SMBUS master function enabled here (temporary) + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG28, AccWidthUint16 | S3_SAVE, ~(BIT0 + BIT2), BIT0 + BIT2); + + programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr)); +#ifndef NO_EC_SUPPORT + // Software IMC enable + if (((pConfig->BuildParameters.ImcEnableOverWrite == 1) && ((dbPortStatus & ChipSysEcEnable) == 0)) || ((pConfig->BuildParameters.ImcEnableOverWrite == 2) && ((dbPortStatus & ChipSysEcEnable) == ChipSysEcEnable))) { + if (validateImcFirmware (pConfig)) { + softwareToggleImcStrapping (pConfig); + } else { + CallBackToOEM (IMC_FIRMWARE_FAIL, 0, pConfig); + } + } +#endif + +} +/** + * abLinkInitBeforePciEnum - Set ABCFG registers before PCI emulation. + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +abLinkInitBeforePciEnum ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 cimResetCpuOnSyncFlood; + ABTBLENTRY *pAbTblPtr; + AMDSBCFG* Temp; + + cimResetCpuOnSyncFlood = pConfig->ResetCpuOnSyncFlood; +#if SB_CIMx_PARAMETER == 0 + cimResetCpuOnSyncFlood = cimResetCpuOnSyncFloodDefault; +#endif + Temp = pConfig; + if ( pConfig->SbPcieOrderRule ) { + pAbTblPtr = (ABTBLENTRY *) FIXUP_PTR (&SbPcieOrderRule[0]); + abcfgTbl (pAbTblPtr); + } + pAbTblPtr = (ABTBLENTRY *) FIXUP_PTR (&abTblEntry800[0]); + abcfgTbl (pAbTblPtr); + if ( cimResetCpuOnSyncFlood ) { + rwAlink (SB_ABCFG_REG10050 | (UINT32) (ABCFG << 29), ~BIT2, BIT2); + } +} + +/** + * abcfgTbl - Program ABCFG by input table. + * + * + * @param[in] pABTbl ABCFG config table. + * + */ +VOID +abcfgTbl ( + IN ABTBLENTRY* pABTbl + ) +{ + UINT32 ddValue; + + while ( (pABTbl->regType) != 0xFF ) { + if ( pABTbl->regType > AXINDC ) { + ddValue = pABTbl->regIndex | (pABTbl->regType << 29); + writeAlink (ddValue, ((readAlink (ddValue)) & (0xFFFFFFFF^ (pABTbl->regMask))) | pABTbl->regData); + } else { + ddValue = 0x30 | (pABTbl->regType << 29); + writeAlink (ddValue, pABTbl->regIndex); + ddValue = 0x34 | (pABTbl->regType << 29); + writeAlink (ddValue, ((readAlink (ddValue)) & (0xFFFFFFFF^ (pABTbl->regMask))) | pABTbl->regData); + } + ++pABTbl; + } + + //Clear ALink Access Index + ddValue = 0; + WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &ddValue); +} + +/** + * commonInitLateBoot - Prepare Southbridge register setting to boot to OS. + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +commonInitLateBoot ( + IN AMDSBCFG* pConfig + ) +{ + UINT8 dbValue; + UINT32 ddVar; + // We need to do the following setting in late post also because some bios core pci enumeration changes these values + // programmed during early post. + // RPR 4.5 Master Latency Timer + + dbValue = 0x40; + WritePCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG0D, AccWidthUint8, &dbValue); + WritePCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG1B, AccWidthUint8, &dbValue); + + //SB P2P AutoClock control settings. + ddVar = (pConfig->PcibAutoClkCtrlHigh << 16) | (pConfig->PcibAutoClkCtrlLow); + WritePCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG4C, AccWidthUint32, &ddVar); + ddVar = (pConfig->PcibClkStopOverride); + RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG50, AccWidthUint16, 0x3F, (UINT16) (ddVar << 6)); + + RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBB, AccWidthUint8, 0xBF | S3_SAVE, BIT3 + BIT4 + BIT5); + + // USB Phy Calibration Adjustment + ddVar = (USB1_EHCI_BUS_DEV_FUN << 16); + sbUsbPhySetting (ddVar); + ddVar = (USB2_EHCI_BUS_DEV_FUN << 16); + sbUsbPhySetting (ddVar); + ddVar = (USB3_EHCI_BUS_DEV_FUN << 16); + sbUsbPhySetting (ddVar); + + c3PopupSetting (pConfig); + FusionRelatedSetting (pConfig); +} + +/** + * sbUsbPhySetting - USB Phy Calibration Adjustment + * + * + * @param[in] Value Controller PCI config address (bus# + device# + function#) + * + */ +VOID +sbUsbPhySetting ( + IN UINT32 Value + ) +{ + UINT32 ddBarAddress; + UINT32 ddPhyStatus03; + UINT32 ddPhyStatus4; + UINT8 dbRevId; + //Get BAR address + ReadPCI ((UINT32) Value + SB_EHCI_REG10, AccWidthUint32, &ddBarAddress); + if ( (ddBarAddress != - 1) && (ddBarAddress != 0) ) { + ReadMEM ( ddBarAddress + SB_EHCI_BAR_REGA8, AccWidthUint32, &ddPhyStatus03); + ReadMEM ( ddBarAddress + SB_EHCI_BAR_REGAC, AccWidthUint32, &ddPhyStatus4); + ddPhyStatus03 &= 0x07070707; + ddPhyStatus4 &= 0x00000007; + if ( (ddPhyStatus03 != 0x00) | (ddPhyStatus4 != 0x00) ) { + // RPR 7.7 USB 2.0 Ports Driving Strength step 1 + //Make BAR registers of smbus visible. + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, 0); + ReadPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG08, AccWidthUint8, &dbRevId); + //Make BAR registers of smbus invisible. + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, BIT6); + if (dbRevId == 0x41) { // A12 + RWMEM (ddBarAddress + SB_EHCI_BAR_REGC0, AccWidthUint32, 0xFFFF00FF, 0x1500); + RWMEM (ddBarAddress + SB_EHCI_BAR_REGC4, AccWidthUint32, 0xFFFFF0FF, 0); + } else if (dbRevId == 0x42) { // A13 + RWMEM (ddBarAddress + SB_EHCI_BAR_REGC0, AccWidthUint32, 0xFFFF00FF, 0x0F00); + RWMEM (ddBarAddress + SB_EHCI_BAR_REGC4, AccWidthUint32, 0xFFFFF0FF, 0x0100); + } + } + } +} + +/** + * hpetInit - Program Southbridge HPET function + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * @param[in] pStaticOptions Platform build configuration table. + * + */ +VOID +hpetInit ( + IN AMDSBCFG* pConfig, + IN BUILDPARAM *pStaticOptions + ) +{ + DESCRIPTION_HEADER* pHpetTable; + UINT8 cimHpetTimer; + UINT8 cimHpetMsiDis; + + cimHpetTimer = (UINT8) pConfig->HpetTimer; + cimHpetMsiDis = (UINT8) pConfig->HpetMsiDis; +#if SB_CIMx_PARAMETER == 0 + cimHpetTimer = cimHpetTimerDefault; + cimHpetMsiDis = cimHpetMsiDisDefault; +#endif + pHpetTable = NULL; + if ( cimHpetTimer == TRUE ) { + //Program the HPET BAR address + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFF800, pStaticOptions->HpetBase); + //Enabling decoding of HPET MMIO + //Enable HPET MSI support + //Enable High Precision Event Timer (also called Multimedia Timer) interrupt + if ( cimHpetMsiDis == FALSE ) { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFF800, BIT0 + BIT1 + BIT2 + BIT3 + BIT4); + } else { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFF800, BIT0 + BIT1); + } + + } else { + if ( ! (pConfig->S3Resume) ) { + //pHpetTable = (DESCRIPTION_HEADER*) ACPI_LocateTable ('TEPH'); //gcc multi-character character constant warning + pHpetTable = (DESCRIPTION_HEADER*) ACPI_LocateTable (0x54455048);//'TEPH' + } + if ( pHpetTable != NULL ) { + //pHpetTable->Signature = 'HPET'; + pHpetTable->Signature = 0x48504554; //'HPET' + } + } +} + +/** + * c3PopupSetting - Program Southbridge C state function + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +c3PopupSetting ( + IN AMDSBCFG* pConfig + ) +{ + AMDSBCFG* Temp; + UINT8 dbValue; + Temp = pConfig; + //RPR C-State and VID/FID Change + dbValue = getNumberOfCpuCores (); + if (dbValue > 1) { + //PM 0x80[2]=1, For system with dual core CPU, set this bit to 1 to automatically clear BM_STS when the C3 state is being initiated. + //PM 0x80[1]=1, For system with dual core CPU, set this bit to 1 and BM_STS will cause C3 to wakeup regardless of BM_RLD + //PM 0x7E[6]=1, Enable pop-up for C3. For internal bus mastering or BmReq# from the NB, the SB will de-assert + //LDTSTP# (pop-up) to allow DMA traffic, then assert LDTSTP# again after some idle time. + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80, AccWidthUint8 | S3_SAVE, ~(BIT1 + BIT2), (BIT1 + BIT2)); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7E, AccWidthUint8 | S3_SAVE, ~BIT6, BIT6); + } + //SB800 needs to changed for RD790 support + //PM 0x80 [8] = 0 for system with RS780 + //Note: RS690 north bridge has AllowLdtStop built for both display and PCIE traffic to wake up the HT link. + //BmReq# needs to be ignored otherwise may cause LDTSTP# not to toggle. + //PM_IO 0x80[3]=1, Ignore BM_STS_SET message from NB + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80, AccWidthUint16 | S3_SAVE, ~(BIT9 + BIT8 + BIT7 + BIT4 + BIT3 + BIT2 + BIT1 + BIT0), 0x21F); + //LdtStartTime = 10h for minimum LDTSTP# de-assertion duration of 16us in StutterMode. This is to guarantee that + //the HT link has been safely reconnected before it can be disconnected again. If C3 pop-up is enabled, the 16us also + //serves as the minimum idle time before LDTSTP# can be asserted again. This allows DMA to finish before the HT + //link is disconnected. + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94 + 2, AccWidthUint8, 0, 0x10); + + //This setting provides 16us delay before the assertion of LDTSTOP# when C3 is entered. The + //delay will allow USB DMA to go on in a continuous manner + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG98 + 1, AccWidthUint8, 0, 0x10); + // Not in the RPR so far, it's hand writing from ASIC + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7C, AccWidthUint8 | S3_SAVE, 0, 0x85); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7C + 1, AccWidthUint8 | S3_SAVE, 0, 0x01); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7E + 1, AccWidthUint8 | S3_SAVE, ~(BIT7 + BIT5), BIT7 + BIT5); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88 + 1, AccWidthUint8 | S3_SAVE, ~BIT4, BIT4); + // RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94, AccWidthUint8, 0, 0x10); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG98 + 3, AccWidthUint8, 0, 0x10); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGB4 + 1, AccWidthUint8, 0, 0x0B); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8 | S3_SAVE, 0xFF, BIT4); + if (pConfig->LdtStpDisable) { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8 | S3_SAVE, ~BIT5, 0); + } +} + +/** + * FusionRelatedSetting - Program Fusion C related function + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +FusionRelatedSetting ( + IN AMDSBCFG* pConfig + ) +{ + UINT8 cimAcDcMsg; + UINT8 cimTimerTickTrack; + UINT8 cimClockInterruptTag; + UINT8 cimOhciTrafficHanding; + UINT8 cimEhciTrafficHanding; + UINT8 cimFusionMsgCMultiCore; + UINT8 cimFusionMsgCStage; + UINT32 ddValue; + + cimAcDcMsg = (UINT8) pConfig->AcDcMsg; + cimTimerTickTrack = (UINT8) pConfig->TimerTickTrack; + cimClockInterruptTag = (UINT8) pConfig->ClockInterruptTag; + cimOhciTrafficHanding = (UINT8) pConfig->OhciTrafficHanding; + cimEhciTrafficHanding = (UINT8) pConfig->EhciTrafficHanding; + cimFusionMsgCMultiCore = (UINT8) pConfig->FusionMsgCMultiCore; + cimFusionMsgCStage = (UINT8) pConfig->FusionMsgCStage; +#if SB_CIMx_PARAMETER == 0 + cimAcDcMsg = cimAcDcMsgDefault; + cimTimerTickTrack = cimTimerTickTrackDefault; + cimClockInterruptTag = cimClockInterruptTagDefault; + cimOhciTrafficHanding = cimOhciTrafficHandingDefault; + cimEhciTrafficHanding = cimEhciTrafficHandingDefault; + cimFusionMsgCMultiCore = cimFusionMsgCMultiCoreDefault; + cimFusionMsgCStage = cimFusionMsgCStageDefault; +#endif + ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGA0, AccWidthUint32 | S3_SAVE, &ddValue); + ddValue = ddValue & 0xC07F00A0; + if ( cimAcDcMsg ) { + ddValue = ddValue | BIT0; + } + if ( cimTimerTickTrack ) { + ddValue = ddValue | BIT1; + } + if ( cimClockInterruptTag ) { + ddValue = ddValue | BIT10; + } + if ( cimOhciTrafficHanding ) { + ddValue = ddValue | BIT13; + } + if ( cimEhciTrafficHanding ) { + ddValue = ddValue | BIT15; + } + if ( cimFusionMsgCMultiCore ) { + ddValue = ddValue | BIT23; + } + if ( cimFusionMsgCStage ) { + ddValue = (ddValue | (BIT6 + BIT4 + BIT3 + BIT2)); + } + WriteMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGA0, AccWidthUint32 | S3_SAVE, &ddValue); +} +#ifndef NO_EC_SUPPORT +/** + * validateImcFirmware - Validate IMC Firmware. + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + * @retval TRUE Pass + * @retval FALSE Failed + */ +BOOLEAN +validateImcFirmware ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 ImcSig; + UINT32 ImcSigAddr; + UINT32 ImcAddr; + UINT32 CurAddr; + UINT32 ImcBinSig0; + UINT32 ImcBinSig1; + UINT16 ImcBinSig2; + UINT8 dbIMCChecksume; + UINT8 dbIMC; + ImcAddr = 0; + + // Software IMC enable + ImcSigAddr = 0x80000; // start from 512k to 64M + ImcSig = 0x0; // + while ( ( ImcSig != 0x55aa55aa ) && ( ImcSigAddr <= 0x4000000 ) ) { + CurAddr = 0xffffffff - ImcSigAddr + 0x20001; + ReadMEM (CurAddr, AccWidthUint32, &ImcSig); + ReadMEM ((CurAddr + 4), AccWidthUint32, &ImcAddr); + ImcSigAddr <<= 1; + } + + dbIMCChecksume = 0xff; + if ( ImcSig == 0x55aa55aa ) { + // "_AMD_IMC_C" at offset 0x2000 of the binary + ReadMEM ((ImcAddr + 0x2000), AccWidthUint32, &ImcBinSig0); + ReadMEM ((ImcAddr + 0x2004), AccWidthUint32, &ImcBinSig1); + ReadMEM ((ImcAddr + 0x2008), AccWidthUint16, &ImcBinSig2); + if ((ImcBinSig0 == 0x444D415F) && (ImcBinSig1 == 0x434D495F) && (ImcBinSig2 == 0x435F) ) { + dbIMCChecksume = 0; + for ( CurAddr = ImcAddr; CurAddr < ImcAddr + 0x10000; CurAddr++ ) { + ReadMEM (CurAddr, AccWidthUint8, &dbIMC); + dbIMCChecksume = dbIMCChecksume + dbIMC; + } + } + } + if ( dbIMCChecksume ) { + return FALSE; + } else { + return TRUE; + } +} + +/** + * softwareToggleImcStrapping - Software Toggle IMC Firmware Strapping. + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +softwareToggleImcStrapping ( + IN AMDSBCFG* pConfig + ) +{ + UINT8 dbValue; + UINT8 dbPortStatus; + UINT32 abValue; + UINT32 abValue1; + + getChipSysMode (&dbPortStatus); + + ReadPMIO (SB_PMIOA_REGBF, AccWidthUint8, &dbValue); + //if ( (dbValue & (BIT6 + BIT7)) != 0xC0 ) { // PwrGoodOut =1, PwrGoodEnB=1 + //The strapStatus register is not mapped into StrapOveride not in the same bit position. The following is difference. + + //StrapStatus StrapOverride + // bit4 bit17 + // bit6 bit12 + // bit12 bit15 + // bit15 bit16 + // bit16 bit18 + ReadMEM ((ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80), AccWidthUint32, &abValue); + abValue1 = abValue; + if (abValue & BIT4) { + abValue1 = (abValue1 & ~BIT4) | BIT17; + } + if (abValue & BIT6) { + abValue1 = (abValue1 & ~BIT6) | BIT12; + } + if (abValue & BIT12) { + abValue1 = (abValue1 & ~BIT12) | BIT15; + } + if (abValue & BIT15) { + abValue1 = (abValue1 & ~BIT15) | BIT16; + } + if (abValue & BIT16) { + abValue1 = (abValue1 & ~BIT16) | BIT18; + } + abValue1 |= BIT31; // Overwrite enable + if ((dbPortStatus & ChipSysEcEnable) == 0) { + abValue1 |= BIT2; // bit2- EcEnableStrap + } else { + abValue1 &= ~BIT2; // bit2=0 EcEnableStrap + } + WriteMEM ((ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG84), AccWidthUint32, &abValue1); + dbValue |= BIT6; // PwrGoodOut =1 + dbValue &= ~BIT7; // PwrGoodEnB =0 + WritePMIO (SB_PMIOA_REGBF, AccWidthUint8, &dbValue); + + dbValue = 06; + WriteIO (0xcf9, AccWidthUint8, &dbValue); + SbStall (0xffffffff); +} +#endif + +#ifndef NO_HWM_SUPPORT +/** + * validateImcFirmware - Validate IMC Firmware. + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +hwmInit ( + IN AMDSBCFG* pConfig + ) +{ + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xB2, AccWidthUint8 | S3_SAVE, 0, 0x55); + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xB3, AccWidthUint8 | S3_SAVE, 0, 0x55); + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x91, AccWidthUint8 | S3_SAVE, 0, 0x55); + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x92, AccWidthUint8 | S3_SAVE, 0, 0x55); + + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x00, AccWidthUint8 | S3_SAVE, 0, 0x06); + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x10, AccWidthUint8 | S3_SAVE, 0, 0x06); + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x20, AccWidthUint8 | S3_SAVE, 0, 0x06); + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x30, AccWidthUint8 | S3_SAVE, 0, 0x06); + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x40, AccWidthUint8 | S3_SAVE, 0, 0x06); + + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x66, AccWidthUint8 | S3_SAVE, 0, 0x01); + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x6B, AccWidthUint8 | S3_SAVE, 0, 0x01); + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x70, AccWidthUint8 | S3_SAVE, 0, 0x01); + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x75, AccWidthUint8 | S3_SAVE, 0, 0x01); + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x7A, AccWidthUint8 | S3_SAVE, 0, 0x01); + + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xF8, AccWidthUint8 | S3_SAVE, 0, 0x05); + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xF9, AccWidthUint8 | S3_SAVE, 0, 0x06); + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xFF, AccWidthUint8 | S3_SAVE, 0, 0x42); + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xE9, AccWidthUint8 | S3_SAVE, 0, 0xFF); + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xEB, AccWidthUint8 | S3_SAVE, 0, 0x1F); + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xEF, AccWidthUint8 | S3_SAVE, 0, 0x04); + RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xFB, AccWidthUint8 | S3_SAVE, 0, 0x00); +} +#endif
Added: trunk/src/vendorcode/amd/cimx/sb800/SBDEF.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/SBDEF.h Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,252 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + + +//AMD Library Routines (AMDLIB.C) +UINT8 getNumberOfCpuCores (OUT VOID); +UINT32 readAlink (IN UINT32 Index); +VOID writeAlink (IN UINT32 Index, IN UINT32 Data); +VOID rwAlink (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask); + +//AMD Library Routines (LEGACY.C) +UINT32 GetFixUp (OUT VOID); + +//AMD Library Routines (IOLIB.C) +VOID ReadIO (IN UINT16 Address, IN UINT8 OpFlag, IN VOID *Value); +VOID WriteIO (IN UINT16 Address, IN UINT8 OpFlag, IN VOID *Value); +VOID RWIO (IN UINT16 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data); + + + +//AMD Library Routines (MEMLIB.C) +VOID ReadMEM (IN UINT32 Address, IN UINT8 OpFlag, IN VOID* Value); +VOID WriteMEM (IN UINT32 Address, IN UINT8 OpFlag, IN VOID* Value); +VOID RWMEM (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data); + +//AMD Library Routines (PCILIB.C) +VOID ReadPCI (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value); +VOID WritePCI (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value); +VOID RWPCI (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data); + +//AMD Library Routines (SBPELIB.C) +/** + * Read Southbridge Revision ID cie Base + * + * + * @retval 0xXXXXXXXX Revision ID + * + */ +UINT8 getRevisionID (OUT VOID); + +/** + * programPciByteTable - Program PCI register by table (8 bits data) + * + * + * + * @param[in] pPciByteTable - Table data pointer + * @param[in] dwTableSize - Table length + * + */ +VOID programPciByteTable (IN REG8MASK* pPciByteTable, IN UINT16 dwTableSize); + +/** + * programSbAcpiMmioTbl - Program SB ACPI MMIO register by table (8 bits data) + * + * + * + * @param[in] pAcpiTbl - Table data pointer + * + */ +VOID programSbAcpiMmioTbl (IN AcpiRegWrite *pAcpiTbl); + +/** + * getChipSysMode - Get Chip status + * + * + * @param[in] Value - Return Chip strap status + * StrapStatus [15.0] - SB800 chip Strap Status + * @li <b>0001</b> - Not USED FWH + * @li <b>0002</b> - Not USED LPC ROM + * @li <b>0004</b> - EC enabled + * @li <b>0008</b> - Reserved + * @li <b>0010</b> - Internal Clock mode + * + */ +VOID getChipSysMode (IN VOID* Value); + +/** + * Read Southbridge CIMx configuration structure pointer + * + * + * + * @retval 0xXXXXXXXX CIMx configuration structure pointer. + * + */ +AMDSBCFG* getConfigPointer (OUT VOID); + +//AMD Library Routines (PMIOLIB.C) +/** + * Read PMIO + * + * + * + * @param[in] Address - PMIO Offset value + * @param[in] OpFlag - Access sizes + * @param[in] Value - Read Data Buffer + * + */ +VOID ReadPMIO (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value); + +/** + * Write PMIO + * + * + * + * @param[in] Address - PMIO Offset value + * @param[in] OpFlag - Access sizes + * @param[in] Value - Write Data Buffer + * + */ +VOID WritePMIO (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value); + +/** + * RWPMIO - Read/Write PMIO + * + * + * + * @param[in] Address - PMIO Offset value + * @param[in] OpFlag - Access sizes + * @param[in] AndMask - Data And Mask 32 bits + * @param[in] OrMask - Data OR Mask 32 bits + * + */ +VOID RWPMIO (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask); + +//AMD Library Routines (PMIO2LIB.C) + +/** + * Read PMIO2 + * + * + * + * @param[in] Address - PMIO2 Offset value + * @param[in] OpFlag - Access sizes + * @param[in] Value - Read Data Buffer + * + */ +VOID ReadPMIO2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value); + +/** + * Write PMIO 2 + * + * + * + * @param[in] Address - PMIO2 Offset value + * @param[in] OpFlag - Access sizes + * @param[in] Value - Write Data Buffer + * + */ +VOID WritePMIO2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value); + +/** + * RWPMIO2 - Read/Write PMIO2 + * + * + * + * @param[in] Address - PMIO2 Offset value + * @param[in] OpFlag - Access sizes + * @param[in] AndMask - Data And Mask 32 bits + * @param[in] OrMask - Data OR Mask 32 bits + * + */ +VOID RWPMIO2 (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask); +//AMD Library Routines (ECLIB.C) +// ECLIB Routines + +// #ifndef NO_EC_SUPPORT + +/** + * EnterEcConfig - Force EC into Config mode + * + * + * + * + */ +VOID EnterEcConfig (VOID); + +/** + * ExitEcConfig - Force EC exit Config mode + * + * + * + * + */ +VOID ExitEcConfig (VOID); + +/** + * ReadEC8 - Read EC register data + * + * + * + * @param[in] Address - EC Register Offset Value + * @param[in] Value - Read Data Buffer + * + */ +VOID ReadEC8 (IN UINT8 Address, IN UINT8* Value); + +/** + * WriteEC8 - Write date into EC register + * + * + * + * @param[in] Address - EC Register Offset Value + * @param[in] Value - Write Data Buffer + * + */ +VOID WriteEC8 (IN UINT8 Address, IN UINT8* Value); + +/** + * RWEC8 - Read/Write EC register + * + * + * + * @param[in] Address - EC Register Offset Value + * @param[in] AndMask - Data And Mask 8 bits + * @param[in] OrMask - Data OR Mask 8 bits + * + */ +VOID RWEC8 (IN UINT8 Address, IN UINT8 AndMask, IN UINT8 OrMask); + +/** + * IsZoneFuncEnable - check every zone support function with BitMap from user define + * + */ +BOOLEAN IsZoneFuncEnable ( UINT16 Flag, UINT8 func, UINT8 Zone); + +VOID sbECfancontrolservice (IN AMDSBCFG* pConfig); +VOID SBIMCFanInitializeS3 (VOID); +VOID GetSbAcpiMmioBase (OUT UINT32* AcpiMmioBase); +VOID GetSbAcpiPmBase (OUT UINT16* AcpiPmBase); + +// #endif +
Added: trunk/src/vendorcode/amd/cimx/sb800/SBMAIN.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/SBMAIN.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,248 @@ +/** + * @file + * + * SB Initialization. + * + * Init IOAPIC/IOMMU/Misc NB features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: CIMx-SB + * @e sub-project: + * @e $Revision:$ @e $Date:$ + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" + +#ifndef B1_IMAGE + +/*----------------------------------------------------------------------------------------*/ +/** + * sbBeforePciInit - Config Southbridge before PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ + +VOID +sbBeforePciInit ( + IN AMDSBCFG* pConfig + ) +{ + commonInitEarlyBoot (pConfig); + commonInitEarlyPost (pConfig); +#ifndef NO_EC_SUPPORT + ecInitBeforePciEnum (pConfig); +#endif + usbInitBeforePciEnum (pConfig); // USB POST TIME Only + sataInitBeforePciEnum (pConfig); // Init SATA class code and PHY + gecInitBeforePciEnum (pConfig); // Init GEC + azaliaInitBeforePciEnum (pConfig); // Detect and configure High Definition Audio + sbPcieGppEarlyInit (pConfig); // Gpp port init + abSpecialSetBeforePciEnum (pConfig); + usbDesertPll (pConfig); +} + +/** + * sbAfterPciInit - Config Southbridge after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +sbAfterPciInit ( + IN AMDSBCFG* pConfig + ) +{ + usbInitAfterPciInit (pConfig); // Init USB MMIO + sataInitAfterPciEnum (pConfig); // SATA port enumeration + gecInitAfterPciEnum (pConfig); + azaliaInitAfterPciEnum (pConfig); // Detect and configure High Definition Audio + +#ifndef NO_HWM_SUPPORT + hwmInit (pConfig); +#endif +} + +/** + * sbMidPostInit - Config Southbridge during middle of POST + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +sbMidPostInit ( + IN AMDSBCFG* pConfig + ) +{ + sataInitMidPost (pConfig); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * sbLatePost - Prepare Southbridge to boot to OS. + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +sbLatePost ( + IN AMDSBCFG* pConfig + ) +{ +// UINT16 dwVar; + BUILDPARAM *pStaticOptions; + pStaticOptions = &(pConfig->BuildParameters); + commonInitLateBoot (pConfig); + sataInitLatePost (pConfig); + gecInitLatePost (pConfig); + hpetInit (pConfig, pStaticOptions); // SB Configure HPET base and enable bit +#ifndef NO_EC_SUPPORT + ecInitLatePost (pConfig); +#endif + sbPcieGppLateInit (pConfig); + +} + +/*----------------------------------------------------------------------------------------*/ +/** + * sbBeforePciRestoreInit - Config Southbridge before ACPI S3 resume PCI config device restore + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ + +VOID +sbBeforePciRestoreInit ( + IN AMDSBCFG* pConfig + ) +{ + pConfig->S3Resume = 1; + commonInitEarlyBoot (pConfig); // set /SMBUS/ACPI/IDE/LPC/PCIB + abLinkInitBeforePciEnum (pConfig); // Set ABCFG registers + usbInitBeforePciEnum (pConfig); // USB POST TIME Only + sataInitBeforePciEnum (pConfig); + gecInitBeforePciEnum (pConfig); // Init GEC + azaliaInitBeforePciEnum (pConfig); // Detect and configure High Definition Audio + sbPcieGppEarlyInit (pConfig); // Gpp port init + abSpecialSetBeforePciEnum (pConfig); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * sbAfterPciRestoreInit - Config Southbridge after ACPI S3 resume PCI config device restore + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ + +VOID +sbAfterPciRestoreInit ( + IN AMDSBCFG* pConfig + ) +{ + BUILDPARAM *pStaticOptions; + + pConfig->S3Resume = 1; + + usbSetPllDuringS3 (pConfig); + pStaticOptions = &(pConfig->BuildParameters); + commonInitLateBoot (pConfig); + sataInitAfterPciEnum (pConfig); + gecInitAfterPciEnum (pConfig); + azaliaInitAfterPciEnum (pConfig); // Detect and configure High Definition Audio + hpetInit (pConfig, pStaticOptions); // SB Configure HPET base and enable bit + sataInitLatePost (pConfig); + c3PopupSetting (pConfig); + +#ifndef NO_HWM_SUPPORT + SBIMCFanInitializeS3 (); +#endif +} + +/*----------------------------------------------------------------------------------------*/ +/** + * sbSmmAcpiOn - Config Southbridge during ACPI_ON + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +sbSmmAcpiOn ( + IN AMDSBCFG* pConfig + ) +{ + // Commented the following code since we need to leave the IRQ1/12 filtering enabled always as per latest + // recommendation in RPR. This is required to fix the keyboard stuck issue when playing games under Windows + AMDSBCFG* pTmp; //lx-dummy for /W4 build + pTmp = pConfig; + + // Disable Power Button SMI + RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGB2, AccWidthUint8, ~(BIT4 + BIT5), 0); + RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGAC, AccWidthUint8, ~(BIT6 + BIT7), 0); +} + +#endif + +/*----------------------------------------------------------------------------------------*/ +/** + * Call Back routine. + * + * + * + * @param[in] Func Callback ID. + * @param[in] Data Callback specific data. + * @param[in] pConfig Southbridge configuration structure pointer. + */ +UINTN +CallBackToOEM ( + IN UINT32 Func, + IN UINT32 Data, + IN AMDSBCFG* pConfig + ) +{ + UINT32 Result; + Result = 0; + if ( pConfig->StdHeader.CALLBACK.CalloutPtr == NULL ) return Result; + Result = (pConfig->StdHeader.CALLBACK.CalloutPtr) ( Func, Data, pConfig); + + return Result; +} + +
Added: trunk/src/vendorcode/amd/cimx/sb800/SBPELIB.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/SBPELIB.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,188 @@ +/** + * @file + * + * Southbridge IO access common routine + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: CIMx-SB + * @e sub-project: + * @e $Revision:$ @e $Date:$ + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" + +/** + * Read Southbridge Revision ID cie Base + * + * + * @retval 0xXXXXXXXX Revision ID + * + */ +UINT8 +getRevisionID ( + OUT VOID + ) +{ + UINT8 dbVar0; + ReadPCI (((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG08), AccWidthUint8, &dbVar0); + return dbVar0; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * programPciByteTable - Program PCI register by table (8 bits data) + * + * + * + * @param[in] pPciByteTable - Table data pointer + * @param[in] dwTableSize - Table length + * + */ +VOID +programPciByteTable ( + IN REG8MASK* pPciByteTable, + IN UINT16 dwTableSize + ) +{ + UINT8 i; + UINT8 dbBusNo; + UINT8 dbDevFnNo; + UINT32 ddBDFR; + + dbBusNo = pPciByteTable->bRegIndex; + dbDevFnNo = pPciByteTable->bANDMask; + pPciByteTable++; + + for ( i = 1; i < dwTableSize; i++ ) { + if ( (pPciByteTable->bRegIndex == 0xFF) && (pPciByteTable->bANDMask == 0xFF) && (pPciByteTable->bORMask == 0xFF) ) { + pPciByteTable++; + dbBusNo = pPciByteTable->bRegIndex; + dbDevFnNo = pPciByteTable->bANDMask; + pPciByteTable++; + i++; + } else { + ddBDFR = (dbBusNo << 24) + (dbDevFnNo << 16) + (pPciByteTable->bRegIndex) ; + RWPCI (ddBDFR, AccWidthUint8 | S3_SAVE, pPciByteTable->bANDMask, pPciByteTable->bORMask); + pPciByteTable++; + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * programSbAcpiMmioTbl - Program SB ACPI MMIO register by table (8 bits data) + * + * + * + * @param[in] pAcpiTbl - Table data pointer + * + */ +VOID +programSbAcpiMmioTbl ( + IN AcpiRegWrite *pAcpiTbl + ) +{ + UINT8 i; + UINT32 ddtempVar; + if (pAcpiTbl != NULL) { + for ( i = 1; pAcpiTbl->MmioBase < 0xf0; i++ ) { + ddtempVar = 0xFED80000 | (pAcpiTbl->MmioBase) << 8 | pAcpiTbl->MmioReg; + RWMEM (ddtempVar, AccWidthUint8, ((pAcpiTbl->DataANDMask) | 0xFFFFFF00), pAcpiTbl->DataOrMask); + pAcpiTbl++; + } + } +} + +/** + * getChipSysMode - Get Chip status + * + * + * @param[in] Value - Return Chip strap status + * StrapStatus [15.0] - SB800 chip Strap Status + * @li <b>0001</b> - Not USED FWH + * @li <b>0002</b> - Not USED LPC ROM + * @li <b>0004</b> - EC enabled + * @li <b>0008</b> - Reserved + * @li <b>0010</b> - Internal Clock mode + * + */ +VOID +getChipSysMode ( + IN VOID* Value + ) +{ + ReadMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80, AccWidthUint8, Value); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Read Southbridge CIMx configuration structure pointer + * + * + * + * @retval 0xXXXXXXXX CIMx configuration structure pointer. + * + */ +AMDSBCFG* +getConfigPointer ( + OUT VOID + ) +{ + UINT8 dbReg; + UINT8 dbValue; + UINT8 i; + UINT32 ddValue; + ddValue = 0; + dbReg = SB_ECMOS_REG08; + + for ( i = 0; i <= 3; i++ ) { + WriteIO (SB_IOMAP_REG72, AccWidthUint8, &dbReg); + ReadIO (SB_IOMAP_REG73, AccWidthUint8, &dbValue); + ddValue |= (dbValue << (i * 8)); + dbReg++; + } + return ( (AMDSBCFG*) (UINTN)ddValue); +} + +/** + * getEfuseStatue - Get Efuse status + * + * + * @param[in] Value - Return Chip strap status + * + */ +VOID +getEfuseStatus ( + IN VOID* Value + ) +{ + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, ~BIT5, BIT5); + WriteMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, Value); + ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8 + 1, AccWidthUint8, Value); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, ~BIT5, 0); +}
Added: trunk/src/vendorcode/amd/cimx/sb800/SBPOR.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/SBPOR.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,347 @@ + +/** + * @file + * + * Southbridge Init during POWER-ON + * + * Prepare Southbridge environment during power on stage. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: CIMx-SB + * @e sub-project: + * @e $Revision:$ @e $Date:$ + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" +/** + * sbPorInitPciTable - PCI device registers initial during the power on stage. + */ +const static REG8MASK sbPorInitPciTable[] = +{ + // SATA device + {0x00, SATA_BUS_DEV_FUN, 0}, + {SB_SATA_REG84 + 3, ~BIT2, 0}, + {SB_SATA_REG84 + 1, ~(BIT4 + BIT5), BIT4 + BIT5}, + {SB_SATA_REGA0, ~(BIT2 + BIT3 + BIT4 + BIT5 + BIT6), BIT2 + BIT3 + BIT4 + BIT5}, + {0xFF, 0xFF, 0xFF}, + // LPC Device (Bus 0, Dev 20, Func 3) + {0x00, LPC_BUS_DEV_FUN, 0}, + {SB_LPC_REG48, 0x00, BIT0 + BIT1 + BIT2}, + {SB_LPC_REG7C, 0x00, BIT0 + BIT2}, + {SB_LPC_REGBB, 0xFF, BIT3 + BIT4 + BIT5}, + // A12 set 0xBB [5:3] = 111 to improve SPI timing margin. + // A12 Set 0xBA [6:5] = 11 improve SPI timing margin. (SPI Prefetch enhancement) + {SB_LPC_REGBB, 0xBE, BIT0 + BIT3 + BIT4 + BIT5}, + {SB_LPC_REGBA, 0x9F, BIT5 + BIT6}, + {0xFF, 0xFF, 0xFF}, + // P2P Bridge (Bus 0, Dev 20, Func 4) + {0x00, PCIB_BUS_DEV_FUN, 0}, + {SB_PCIB_REG4B, 0xFF, BIT6 + BIT7 + BIT4}, + // Enable IO but not allocate any IO range. This is for post code display on debug port behind P2P bridge. + {SB_PCIB_REG1C, 0x00, 0xF0}, + {SB_PCIB_REG1D, 0x00, 0x00}, + {SB_PCIB_REG04, 0x00, 0x21}, + {SB_PCIB_REG40, 0xDF, 0x20}, + {SB_PCIB_REG50, 0x02, 0x01}, + {0xFF, 0xFF, 0xFF}, +}; + +/** + * sbPmioPorInitTable - Southbridge ACPI MMIO initial during the power on stage. + */ +const static AcpiRegWrite sbPmioPorInitTable[] = +{ + {PMIO_BASE >> 8, SB_PMIOA_REG5D, 0x00, BIT0}, + {PMIO_BASE >> 8, SB_PMIOA_REGD2, 0xCF, BIT4 + BIT5}, + {SMBUS_BASE >> 8, SB_SMBUS_REG12, 0x00, BIT0}, + {PMIO_BASE >> 8, SB_PMIOA_REG28, 0xFF, BIT0}, + {PMIO_BASE >> 8, SB_PMIOA_REG44 + 3, 0x7F, BIT7}, + {PMIO_BASE >> 8, SB_PMIOA_REG48, 0xFF, BIT0}, + {PMIO_BASE >> 8, SB_PMIOA_REG00, 0xFF, 0x0E}, + {PMIO_BASE >> 8, SB_PMIOA_REG00 + 2, 0xFF, 0x40}, + {PMIO_BASE >> 8, SB_PMIOA_REG00 + 3, 0xFF, 0x08}, + {PMIO_BASE >> 8, SB_PMIOA_REG34, 0xEF, BIT0 + BIT1}, + {PMIO_BASE >> 8, SB_PMIOA_REGEC, 0xFD, BIT1}, + {PMIO_BASE >> 8, SB_PMIOA_REG5B, 0xF9, BIT1 + BIT2}, + {PMIO_BASE >> 8, SB_PMIOA_REG08, 0xFE, BIT2 + BIT4}, + {PMIO_BASE >> 8, SB_PMIOA_REG08 + 1, 0xFF, BIT0}, + {PMIO_BASE >> 8, SB_PMIOA_REG54, 0x00, BIT4 + BIT7}, + {PMIO_BASE >> 8, SB_PMIOA_REG04 + 3, 0xFD, BIT1}, + {PMIO_BASE >> 8, SB_PMIOA_REG74, 0xF6, BIT0 + BIT3}, + {PMIO_BASE >> 8, SB_PMIOA_REGF0, ~BIT2, 0x00}, + // RPR GEC I/O Termination Setting + // PM_Reg 0xF6 = Power-on default setting + // PM_Reg 0xF7 = Power-on default setting + // PM_Reg 0xF8 = 0x6C + // PM_Reg 0xF9 = 0x21 + // PM_Reg 0xFA = 0x00 SB800 A12 GEC I/O Pad settings for 3.3V CMOS + {PMIO_BASE >> 8, SB_PMIOA_REGF8, 0x00, 0x6C}, + {PMIO_BASE >> 8, SB_PMIOA_REGF8 + 1, 0x00, 0x27}, + {PMIO_BASE >> 8, SB_PMIOA_REGF8 + 2, 0x00, 0x00}, + {PMIO_BASE >> 8, SB_PMIOA_REGC4, 0xFE, 0x14}, + {PMIO_BASE >> 8, SB_PMIOA_REGC0 + 2, 0xBF, 0x40}, + + {PMIO_BASE >> 8, SB_PMIOA_REGBE, 0xDF, BIT5},//ENH210907 SB800: request to no longer clear kb_pcirst_en (bit 1) of PM_Reg BEh per the RPR + + {0xFF, 0xFF, 0xFF, 0xFF}, +}; + +/** + * sbPowerOnInit - Config Southbridge during power on stage. + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +sbPowerOnInit ( + IN AMDSBCFG* pConfig + ) +{ + + UINT8 dbPortStatus; + UINT8 dbSysConfig; + UINT32 abValue; + UINT8 dbValue; + UINT8 dbEfuse; + UINT8 dbCg2WR; + UINT8 dbCg1Pll; + UINT8 cimNbSbGen2; + UINT8 cimSataMode; + UINT8 cimSpiFastReadEnable; + UINT8 cimSpiFastReadSpeed; + UINT8 SataPortNum; + + cimNbSbGen2 = pConfig->NbSbGen2; + cimSataMode = pConfig->SATAMODE.SataModeReg; +// Adding Fast Read Function support + if (pConfig->BuildParameters.SpiFastReadEnable != NULL ) { + cimSpiFastReadEnable = (UINT8) pConfig->BuildParameters.SpiFastReadEnable; + } else { + cimSpiFastReadEnable = cimSpiFastReadEnableDefault; + } + cimSpiFastReadSpeed = (UINT8) pConfig->BuildParameters.SpiFastReadSpeed; +#if SB_CIMx_PARAMETER == 0 + cimNbSbGen2 = cimNbSbGen2Default; + cimSataMode = (UINT8) ((cimSataMode & 0xFB) | cimSataSetMaxGen2Default); + cimSataMode = (UINT8) ((cimSataMode & 0x0F) | (cimSATARefClkSelDefault + cimSATARefDivSelDefault)); + cimSpiFastReadEnable = cimSpiFastReadEnableDefault; + cimSpiFastReadSpeed = cimSpiFastReadSpeedDefault; +#endif + +// SB800 Only Enabled (Mmio_mem_enablr) // Default value is correct + RWPMIO (SB_PMIOA_REG24, AccWidthUint8, 0xFF, BIT0); + +// Set A-Link bridge access address. This address is set at device 14h, function 0, +// register 0f0h. This is an I/O address. The I/O address must be on 16-byte boundary. + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGE0, AccWidthUint32, 00, ALINK_ACCESS_INDEX); + writeAlink (0x80000004, 0x04); // RPR 4.2 Enable SB800 to issue memory read/write requests in the upstream direction + abValue = readAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29)); // RPR 4.5 Disable the credit variable in the downstream arbitration equation + abValue = abValue | BIT0; + writeAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29), abValue); + writeAlink (0x30, 0x10); // AXINDC 0x10[9]=1, Enabling Non-Posted memory write for K8 platform. + writeAlink (0x34, readAlink (0x34) | BIT9); + + dbEfuse = FUSE_ID_EFUSE_LOC; + getEfuseStatus (&dbEfuse); + if ( dbEfuse == M1_D1_FUSE_ID ) { + dbEfuse = MINOR_ID_EFUSE_LOC; + getEfuseStatus (&dbEfuse); + if ( dbEfuse == M1_MINOR_ID ) { + // Limit ALink speed to 2.5G if Hudson-M1 + cimNbSbGen2 = 0; + } + } +// Step 1: +// AXINDP_Reg 0xA4[0] = 0x1 +// Step 2: +// AXCFG_Reg 0x88[3:0] = 0x2 +// Step3: +// AXINDP_Reg 0xA4[18] = 0x1 + if ( cimNbSbGen2 == TRUE ) { + rwAlink (SB_AX_INDXP_REGA4, 0xFFFFFFFF, BIT0); + rwAlink ((UINT32)SB_AX_CFG_REG88, 0xFFFFFFF0, 0x2); + rwAlink (SB_AX_INDXP_REGA4, 0xFFFFFFFF, BIT18); + } + +// Set Build option into SB + WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG64, AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioPmeBaseAddress)); + RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA0, AccWidthUint32 | S3_SAVE, 0x001F, (pConfig->BuildParameters.SpiRomBaseAddress)); + RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint32 | S3_SAVE, 0, (pConfig->BuildParameters.GecShadowRomBase + 1)); +// Enabled SMBUS0/SMBUS1 (ASF) Base Address + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG2C, AccWidthUint16, 06, (pConfig->BuildParameters.Smbus0BaseAddress) + BIT0); //protect BIT[2:1] + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG28, AccWidthUint16, 00, (pConfig->BuildParameters.Smbus1BaseAddress)); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG60, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1EvtBlkAddr)); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG62, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1CntBlkAddr)); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG64, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmTmrBlkAddr)); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG66, AccWidthUint16, 00, (pConfig->BuildParameters.CpuControlBlkAddr)); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG68, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiGpe0BlkAddr)); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6A, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr)); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6C, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmaCntBlkAddr)); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6E, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr) + 8); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG48, AccWidthUint32, 00, (pConfig->BuildParameters.WatchDogTimerBase)); + + dbEfuse = SATA_FIS_BASE_EFUSE_LOC; + getEfuseStatus (&dbEfuse); + + programSbAcpiMmioTbl ((AcpiRegWrite*) FIXUP_PTR (&sbPmioPorInitTable[0])); + + + SataPortNum = 0; + for ( SataPortNum = 0; SataPortNum < 0x06; SataPortNum++ ) { + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, 1 << SataPortNum); + SbStall (2); + RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, (0xFF ^ (1 << SataPortNum)) , 0x00); + SbStall (2); + } + + + //The following bits must be set before enabling SPI prefetch. + // Set SPI MMio bit offset 00h[19] to 1 and offset 00h[26:24] to 111, offset 0ch[21:16] to 1, Set LPC cfg BBh[6] to 0 ( by default it is 0). + // if Ec is enable + // Maximum spi speed that can be supported by SB is 22M (SPI Mmio offset 0ch[13:12] to 10) if the rom can run at the speed. + // else + // Maximum spi speed that can be supported by SB is 33M (SPI Mmio offset 0ch[13:12] to 01 in normal mode or offset 0ch[15:14] in fast mode) if the rom can run at + // the speed. + getChipSysMode (&dbSysConfig); + if (pConfig->BuildParameters.SpiSpeed < 0x02) { + pConfig->BuildParameters.SpiSpeed = 0x01; + if (dbSysConfig & ChipSysEcEnable) pConfig->BuildParameters.SpiSpeed = 0x02; + } + + if (pConfig->SbSpiSpeedSupport) { + RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, (BIT19 + BIT24 + BIT25 + BIT26)); + RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, 0xFFC0FFFF, 1 << 16 ); + RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint16 | S3_SAVE, ~(BIT13 + BIT12), (pConfig->BuildParameters.SpiSpeed << 12)); + } + // SPI Fast Read Function + if ( cimSpiFastReadEnable ) { + RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFBFFFF, BIT18); + } else { + RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFBFFFF, 0x00); + } + + if ( cimSpiFastReadSpeed ) { + RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint16 | S3_SAVE, ~(BIT15 + BIT14), ( cimSpiFastReadSpeed << 14)); + } + //Program power on pci init table + programPciByteTable ( (REG8MASK*) FIXUP_PTR (&sbPorInitPciTable[0]), sizeof (sbPorInitPciTable) / sizeof (REG8MASK) ); + + programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr)); + + dbValue = 0x0A; + WriteIO (SB_IOMAP_REG70, AccWidthUint8, &dbValue); + ReadIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue); + dbValue &= 0xEF; + WriteIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue); + +// Change the CG PLL multiplier to x1.1 + if ( pConfig->UsbRxMode !=0 ) { + dbCg2WR = 0x00; + dbCg1Pll = 0x3A; + ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, &dbCg2WR); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, 0, 0x3A); + ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD9, AccWidthUint8, &dbCg1Pll); + dbCg2WR &= BIT4; + if (( dbCg2WR == 0x00 ) && ( dbCg1Pll !=0x10 )) + { + RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x18, AccWidthUint8, 0xE1, 0x10); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, 0, 0x3A); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD9, AccWidthUint8, 0, USB_PLL_Voltage); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, 0xEF, 0x10); + dbValue = 0x06; + WriteIO (0xCF9, AccWidthUint8, &dbValue); + } else { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, 0xEF, 0x00); + } + } + + RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint32 | S3_SAVE, ~(pConfig->BuildParameters.BiosSize << 4), 0); + + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0, (pConfig->SATAMODE.SataModeReg) & 0xFD ); + + if (dbEfuse & BIT0) { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0xFB, 0x04); + } + + ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, &dbPortStatus); + if ( ((dbPortStatus & 0xF0) == 0x10) ) { + RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_PMIOA_REG08, AccWidthUint8, 0, BIT5); + } + + if ( pConfig->BuildParameters.LegacyFree ) { + RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0x0003C000); + } else { + RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0xFF03FFD5); + } + + dbValue = 0x09; + WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &dbValue); + ReadIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue); + if ( !pConfig->BuildParameters.EcKbd ) { + // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input + dbValue = dbValue & 0xF9; + } + if ( pConfig->BuildParameters.LegacyFree ) { + // Disable IRQ1/IRQ12 filter enable for Legacy free with USB KBC emulation. + dbValue = dbValue & 0x9F; + } + // Enabled IRQ input + dbValue = dbValue | BIT4; + WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue); + +#ifndef NO_EC_SUPPORT + getChipSysMode (&dbPortStatus); + if ( ((dbPortStatus & ChipSysEcEnable) == 0x00) ) { + // EC is disabled by jumper setting or board config + RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4), AccWidthUint16 | S3_SAVE, 0xFFFE, BIT0); + } else { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xF7, 0x08); + ecPowerOnInit ( pConfig); + } +#endif + + ReadMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80, AccWidthUint8, &dbValue); + if (dbValue & ChipSysIntClkGen) { + ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, &dbValue); + if (dbValue & BIT2) { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC0 + 2, AccWidthUint8, 0xDF, 0x20); + } else { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xFB, 0x40); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC0 + 2, AccWidthUint8, 0xDF, 0x20); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xFB, 0x00); + } + } + + // Restore GPP clock to on as it may be off during last POST when some device was disabled; + // the device can't be detected if enabled again as the values retain on S5 and warm reset. + RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG00, AccWidthUint32, 0xFFFFFFFF, 0xFFFFFFFF); + RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG04, AccWidthUint8, 0xFF, 0xFF); + + // Set PMx88[5]to enable LdtStp# output to do the C3 or FidVid transation + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8, 0xFF, BIT5); +}
Added: trunk/src/vendorcode/amd/cimx/sb800/SBSUBFUN.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/SBSUBFUN.h Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,514 @@ +/** + * @file + * + * Southbridge CIMx Function Support Define (All) + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: CIMx-SB + * @e sub-project: + * @e $Revision:$ @e $Date:$ + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +// Southbridge SBMAIN Routines + +/** + * Southbridge Main Function Public Function + * + */ + +/** + * sbBeforePciInit - Config Southbridge before PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID sbBeforePciInit (IN AMDSBCFG* pConfig); + + +/** + * sbAfterPciInit - Config Southbridge after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID sbAfterPciInit (IN AMDSBCFG* pConfig); + +/** + * sbMidPostInit - Config Southbridge during middle of POST + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID sbMidPostInit (IN AMDSBCFG* pConfig); + +/** + * sbLatePost - Prepare Southbridge to boot to OS. + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID sbLatePost (IN AMDSBCFG* pConfig); + +/** + * sbBeforePciRestoreInit - Config Southbridge before ACPI S3 resume PCI config device restore + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID sbBeforePciRestoreInit (IN AMDSBCFG* pConfig); + +/** + * sbAfterPciRestoreInit - Config Southbridge after ACPI S3 resume PCI config device restore + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID sbAfterPciRestoreInit (IN AMDSBCFG* pConfig); + +/** + * sbSmmAcpiOn - Config Southbridge during ACPI_ON + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID sbSmmAcpiOn (IN AMDSBCFG* pConfig); + +/** + * CallBackToOEM - Call Back routine. + * + * + * + * @param[in] Func Callback ID. + * @param[in] Data Callback specific data. + * @param[in] pConfig Southbridge configuration structure pointer. + */ +UINTN CallBackToOEM (IN UINT32 Func, IN UINT32 Data, IN AMDSBCFG* pConfig); + + +// Southbridge SBPOR Routines + +/** + * Southbridge power-on initial Public Function + * + */ + +/** + * sbPowerOnInit - Config Southbridge during power on stage. + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID sbPowerOnInit (IN AMDSBCFG* pConfig); + + +// Southbridge Common Routines + +/** + * Southbridge Common Public Function + * + */ + +/** + * commonInitEarlyBoot - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB. + * + * This settings should be done during S3 resume also + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID commonInitEarlyBoot (IN AMDSBCFG* pConfig); + +/** + * commonInitEarlyPost - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB. + * + * This settings might not program during S3 resume + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID commonInitEarlyPost (IN AMDSBCFG* pConfig); + +/** + * commonInitLateBoot - Prepare Southbridge register setting to boot to OS. + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID commonInitLateBoot (IN AMDSBCFG* pConfig); + +/** + * abSpecialSetBeforePciEnum - Special setting ABCFG registers before PCI emulation. + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID abSpecialSetBeforePciEnum (IN AMDSBCFG* pConfig); + +VOID usbSetPllDuringS3 (IN AMDSBCFG* pConfig); +VOID usbDesertPll (IN AMDSBCFG* pConfig); + +/** + * hpetInit - Program Southbridge HPET function + * + * ** Eric + * + * @param[in] pConfig Southbridge configuration structure pointer. + * @param[in] pStaticOptions Platform build configuration table. + * + */ +VOID hpetInit (IN AMDSBCFG* pConfig, IN BUILDPARAM *pStaticOptions); + +/** + * c3PopupSetting - Program Southbridge C state function + * + * ** Eric + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID c3PopupSetting (IN AMDSBCFG* pConfig); + +/** + * FusionRelatedSetting - Program Fusion C related function + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID FusionRelatedSetting (IN AMDSBCFG* pConfig); + +/** + * Southbridge Common Private Function + * + */ + +/** + * abLinkInitBeforePciEnum - Set ABCFG registers before PCI emulation. + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID abLinkInitBeforePciEnum (IN AMDSBCFG* pConfig); + +// Southbridge SATA Routines + +/** + * Southbridge SATA Controller Public Function + * + */ + +/** + * sataInitMidPost - Config SATA controller in Middle POST. + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID sataInitMidPost (IN AMDSBCFG* pConfig); + +/** + * sataInitAfterPciEnum - Config SATA controller after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID sataInitAfterPciEnum (IN AMDSBCFG* pConfig); + +/** + * sataInitBeforePciEnum - Config SATA controller before PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID sataInitBeforePciEnum (IN AMDSBCFG* pConfig); + +/** + * sataInitLatePost - Prepare SATA controller to boot to OS. + * + * - Set class ID to AHCI (if set to AHCI * Mode) + * - Enable AHCI interrupt + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID sataInitLatePost (IN AMDSBCFG* pConfig); + +// Southbridge GEC Routines + +/** + * Southbridge GEC Controller Public Function + * + */ + +/** + * gecInitBeforePciEnum - Config GEC controller before PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID gecInitBeforePciEnum (IN AMDSBCFG* pConfig); + +/** + * gecInitAfterPciEnum - Config GEC controller after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID gecInitAfterPciEnum (IN AMDSBCFG* pConfig); + +/** + * gecInitLatePost - Prepare GEC controller to boot to OS. + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID gecInitLatePost (IN AMDSBCFG* pConfig); + +// Southbridge USB Routines + +/** + * Southbridge USB Controller Public Function + * + */ + +/** + * Config USB controller before PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID usbInitBeforePciEnum (IN AMDSBCFG* pConfig); + +/** + * Config USB controller after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID usbInitAfterPciInit (IN AMDSBCFG* pConfig); + +/** + * Config USB1 EHCI controller after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID usb1EhciInitAfterPciInit (IN AMDSBCFG* pConfig); +VOID usb2EhciInitAfterPciInit (IN AMDSBCFG* pConfig); +VOID usb3EhciInitAfterPciInit (IN AMDSBCFG* pConfig); +VOID usb1OhciInitAfterPciInit (IN AMDSBCFG* pConfig); +VOID usb2OhciInitAfterPciInit (IN AMDSBCFG* pConfig); +VOID usb3OhciInitAfterPciInit (IN AMDSBCFG* pConfig); +VOID usb4OhciInitAfterPciInit (IN AMDSBCFG* pConfig); + +// Southbridge SMI Service Routines (SMM.C) + +/** + * Southbridge SMI Service Routines Public Function + * + */ + +/** + * Southbridge SMI service module + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID sbSmmService (IN AMDSBCFG* pConfig); + +/** + * softwareSMIservice - Software SMI service + * + * ** Eric + * + * @param[in] VOID Southbridge software SMI service ID. + * + */ +VOID softwareSMIservice (IN VOID); + +// Southbridge GPP Controller Routines + +/** + * Southbridge GPP Controller Routines Public Function + * + */ + +/** + * GPP early programming and link training. On exit all populated EPs should be fully operational. + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID sbPcieGppEarlyInit (IN AMDSBCFG* pConfig); + +/** + * sbPcieGppLateInit - Late PCIE initialization for SB800 GPP component + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID sbPcieGppLateInit (IN AMDSBCFG* pConfig); + +// Southbridge HD Controller Routines (AZALIA.C) + +/** + * Southbridge HD Controller Routines (AZALIA.C) Public Function + * + */ + +/** + * Config HD Audio Before PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID azaliaInitBeforePciEnum (IN AMDSBCFG* pConfig); + +/** + * Config HD Audio after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID azaliaInitAfterPciEnum (IN AMDSBCFG* pConfig); + + +// Southbridge EC Routines + +#ifndef NO_EC_SUPPORT +/** + * Southbridge EC Controller Public Function + * + */ + +/** + * Config EC controller during power-on + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ + VOID ecPowerOnInit (IN AMDSBCFG* pConfig); + +/** + * Config EC controller before PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ + VOID ecInitBeforePciEnum (IN AMDSBCFG* pConfig); + +/** + * Prepare EC controller to boot to OS. + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ + VOID ecInitLatePost (IN AMDSBCFG* pConfig); + +/** + * validateImcFirmware - Validate IMC Firmware. + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + * @retval TRUE Pass + * @retval FALSE Failed + */ + BOOLEAN validateImcFirmware (IN AMDSBCFG* pConfig); + +/** + * validateImcFirmware - Validate IMC Firmware. + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ + VOID softwareToggleImcStrapping (IN AMDSBCFG* pConfig); +#endif + +#ifndef NO_HWM_SUPPORT +/** + * validateImcFirmware - Validate IMC Firmware. + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ + VOID hwmInit (IN AMDSBCFG* pConfig); +#endif +
Added: trunk/src/vendorcode/amd/cimx/sb800/SBTYPE.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/SBTYPE.h Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,1111 @@ + +/** + * @file + * + * Southbridge CIMx configuration structure define + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: CIMx-SB + * @e sub-project: + * @e $Revision:$ @e $Date:$ + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#ifndef _AMD_SBTYPE_H_ +#define _AMD_SBTYPE_H_ + +#pragma pack (push, 1) + +/** + * Entry point of Southbridge CIMx + * + * + * @param[in] Param1 Southbridge CIMx Function ID. + * @param[in] Param2 Southbridge Input Data. + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +typedef UINT32 (*SBCIM_HOOK_ENTRY) (UINT32 Param1, UINT32 Param2, void* pConfig); +/** + * SMM_SERVICE_ROUTINE - Southbridge SMI service routine + * + */ +typedef void (*SMM_SERVICE_ROUTINE) (void); + + +/** + * The STATIC platform information for CIMx Module. + * + */ +typedef struct _BUILDPARAM { + UINT32 BiosSize:3; /**< BiosSize + * @par + * BIOSSize [2.0] - BIOS Image Size + * @li <b>0</b> - 1M + * @li <b>1</b> - 2M + * @li <b>3</b> - 4M + * @li <b>7</b> - 8M + * In SB800, default ROM size is 1M Bytes, if your platform ROM bigger then 1M + * you have to set the ROM size outside CIMx module and before AGESA module get call + * + */ + UINT32 LegacyFree:1; /**< LegacyFree + * @par + * Config Southbridge CIMx module for Legacy Free Mode + */ + UINT32 SpiSpeed:2; /**< SpiSpeed + * @par + * SPI Speed [1.0] - the clock speed for non-fast read command + * @li <b>00</b> - 66Mhz + * @li <b>01</b> - 33Mhz + * @li <b>10</b> - 22Mhz + * @li <b>11</b> - 16.5Mhz + * + */ + UINT32 ImcEnableOverWrite:2; /**< ImcEnableOverWrite + * @par + * Imc Enable OverWrite + * @li <b>00</b> - by default strapping + * @li <b>01</b> - On + * @li <b>10</b> - Off + * + */ + UINT32 SpiFastReadEnable:1; /**< SpiFastReadEnable + * @par + * @li <b>00</b> - Disable SPI Fast Read Function + * @li <b>01</b> - Enable SPI Fast Read Function + */ + UINT32 SpiFastReadSpeed:2; /**< SpiFastReadSpeed + * @par + * @li <b>00</b> - 66Mhz + * @li <b>01</b> - 33Mhz + * @li <b>10</b> - 22Mhz + * @li <b>11</b> - 16.5Mhz + */ + UINT32 SpreadSpectrumType:1; /**< SpreadSpectrumType + * @par + * @li <b>0</b> - Spread Spectrum for normal platform + * @li <b>1</b> - Spread Spectrum for Ontario platform + */ +/** Dummy0 - Reserved */ + UINT32 Dummy0:4; + UINT32 EcKbd:1; /**< EcKbd + * @par + * EcKbd [16] - Platform use EC (as SIO) or SIO chip for PS/2 Keyboard and Mouse + * @li <b>0</b> - Use SIO PS/2 function. + * @li <b>1</b> - Use EC PS/2 function instead of SIO PS/2 function. ** + * @li <b>**</b> When set 1, EC function have to enable, otherwise, CIMx treat as legacy-free system. + */ +/** EcChannel0 - Reserved */ + UINT32 EcChannel0:1; +/** UsbMsi - Reserved */ + UINT32 UsbMsi:1; +/** HdAudioMsi - Reserved */ + UINT32 HdAudioMsi:1; +/** LpcMsi - Reserved */ + UINT32 LpcMsi:1; +/** PcibMsi - Reserved */ + UINT32 PcibMsi:1; +/** AbMsi - Reserved */ + UINT32 AbMsi:1; +/** Dummy1 - Reserved */ + UINT32 Dummy1:9; + + UINT32 Smbus0BaseAddress; /**< Smbus0BaseAddress + * @par + * Smbus BASE Address + */ + UINT32 Smbus1BaseAddress; /**< Smbus1BaseAddress + * @par + * Smbus1 (ASF) BASE Address + */ + UINT32 SioPmeBaseAddress; /**< SioPmeBaseAddress + * @par + * SIO PME BASE Address + */ + UINT32 WatchDogTimerBase; /**< WatchDogTimerBase + * @par + * Watch Dog Timer Address + */ + UINT32 GecShadowRomBase; /**< GecShadowRomBase + * @par + * GEC (NIC) SHADOWROM BASE Address + */ + UINT32 SpiRomBaseAddress; /**< SpiRomBaseAddress + * @par + * SPI ROM BASE Address + */ + UINT16 AcpiPm1EvtBlkAddr; /**< AcpiPm1EvtBlkAddr + * @par + * ACPI PM1 event block Address + */ + UINT16 AcpiPm1CntBlkAddr; /**< AcpiPm1CntBlkAddr + * @par + * ACPI PM1 Control block Address + */ + UINT16 AcpiPmTmrBlkAddr; /**< AcpiPmTmrBlkAddr + * @par + * ACPI PM timer block Address + */ + UINT16 CpuControlBlkAddr; /**< CpuControlBlkAddr + * @par + * ACPI CPU control block Address + */ + UINT16 AcpiGpe0BlkAddr; /**< AcpiGpe0BlkAddr + * @par + * ACPI GPE0 block Address + */ + UINT16 SmiCmdPortAddr; /**< SmiCmdPortAddr + * @par + * SMI command port Address + */ + UINT16 AcpiPmaCntBlkAddr; /**< AcpiPmaCntBlkAddr + * @par + * ACPI PMA Control block Address + */ + UINT32 HpetBase; /**< HpetBase + * @par + * HPET Base address + */ + UINT32 SataIDESsid; /**< SataIDESsid + * @par + * SATA IDE mode SSID + */ + UINT32 SataRAIDSsid; /**< SataRAIDSsid + * @par + * SATA RAID mode SSID + */ + UINT32 SataRAID5Ssid; /**< SataRAID5Ssid + * @par + * SATA RAID5 mode SSID + */ + UINT32 SataAHCISsid; /**< SataAHCISsid + * @par + * SATA AHCI mode SSID + */ + UINT32 OhciSsid; /**< OhciSsid + * @par + * OHCI Controller SSID + */ + UINT32 EhciSsid; /**< EhciSsid + * @par + * EHCI Controller SSID + */ + UINT32 Ohci4Ssid; /**< Ohci4Ssid + * @par + * OHCI4 Controller SSID (Force USB 1.1 mode) + */ + UINT32 SmbusSsid; /**< SmbusSsid + * @par + * SMBUS controller SSID + */ + UINT32 IdeSsid; /**< IdeSsid + * @par + * IDE (Sata) controller SSID + */ + UINT32 AzaliaSsid; /**< AzaliaSsid + * @par + * HD Audio controller SSID + */ + UINT32 LpcSsid; /**< LpcSsid + * @par + * LPC controller SSID + */ + UINT32 PCIBSsid; /**< PCIBSsid + * @par + * PCIB controller SSID + */ +} BUILDPARAM; + +/** + * The EC fan MSGREG struct for CIMx Module. * + */ +typedef struct _EC_struct { + UINT8 MSGFun81zone0MSGREG0; ///<Thermal zone + UINT8 MSGFun81zone0MSGREG1; ///<Thermal zone + UINT8 MSGFun81zone0MSGREG2; ///<Thermal zone control byte 1 + UINT8 MSGFun81zone0MSGREG3; ///<Thermal zone control byte 2 + UINT8 MSGFun81zone0MSGREG4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius. + UINT8 MSGFun81zone0MSGREG5; ///<Hysteresis inforamtion + UINT8 MSGFun81zone0MSGREG6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 + UINT8 MSGFun81zone0MSGREG7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located. + UINT8 MSGFun81zone0MSGREG8; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry + UINT8 MSGFun81zone0MSGREG9; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry + + //EC LDN9 funtion 81 zone 1 + UINT8 MSGFun81zone1MSGREG0; ///<Thermal zone + UINT8 MSGFun81zone1MSGREG1; ///<Thermal zone + UINT8 MSGFun81zone1MSGREG2; ///<Thermal zone control byte 1 + UINT8 MSGFun81zone1MSGREG3; ///<Thermal zone control byte 2 + UINT8 MSGFun81zone1MSGREG4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius. + UINT8 MSGFun81zone1MSGREG5; ///<Hysteresis inforamtion + UINT8 MSGFun81zone1MSGREG6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 + UINT8 MSGFun81zone1MSGREG7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located. + UINT8 MSGFun81zone1MSGREG8; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry + UINT8 MSGFun81zone1MSGREG9; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry + + //EC LDN9 funtion 81 zone 2 + UINT8 MSGFun81zone2MSGREG0; ///<Thermal zone + UINT8 MSGFun81zone2MSGREG1; ///<Thermal zone + UINT8 MSGFun81zone2MSGREG2; ///<Thermal zone control byte 1 + UINT8 MSGFun81zone2MSGREG3; ///<Thermal zone control byte 2 + UINT8 MSGFun81zone2MSGREG4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius. + UINT8 MSGFun81zone2MSGREG5; ///<Hysteresis inforamtion + UINT8 MSGFun81zone2MSGREG6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 + UINT8 MSGFun81zone2MSGREG7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located. + UINT8 MSGFun81zone2MSGREG8; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry + UINT8 MSGFun81zone2MSGREG9; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry + + //EC LDN9 funtion 81 zone 3 + UINT8 MSGFun81zone3MSGREG0; ///<Thermal zone + UINT8 MSGFun81zone3MSGREG1; ///<Thermal zone + UINT8 MSGFun81zone3MSGREG2; ///<Thermal zone control byte 1 + UINT8 MSGFun81zone3MSGREG3; ///<Thermal zone control byte 2 + UINT8 MSGFun81zone3MSGREG4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius. + UINT8 MSGFun81zone3MSGREG5; ///<Hysteresis inforamtion + UINT8 MSGFun81zone3MSGREG6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 + UINT8 MSGFun81zone3MSGREG7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located. + UINT8 MSGFun81zone3MSGREG8; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry + UINT8 MSGFun81zone3MSGREG9; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry + + //EC LDN9 funtion 83 zone 0 + UINT8 MSGFun83zone0MSGREG0; ///<Thermal zone + UINT8 MSGFun83zone0MSGREG1; ///<Thermal zone + UINT8 MSGFun83zone0MSGREG2; ///<_AC0 + UINT8 MSGFun83zone0MSGREG3; ///<_AC1 + UINT8 MSGFun83zone0MSGREG4; ///<_AC2 + UINT8 MSGFun83zone0MSGREG5; ///<_AC3 + UINT8 MSGFun83zone0MSGREG6; ///<_AC4 + UINT8 MSGFun83zone0MSGREG7; ///<_AC5 + UINT8 MSGFun83zone0MSGREG8; ///<_AC6 + UINT8 MSGFun83zone0MSGREG9; ///<_AC7 + UINT8 MSGFun83zone0MSGREGA; ///<_CRT + UINT8 MSGFun83zone0MSGREGB; ///<_PSV + + //EC LDN9 funtion 83 zone 1 + UINT8 MSGFun83zone1MSGREG0; ///<Thermal zone + UINT8 MSGFun83zone1MSGREG1; ///<Thermal zone + UINT8 MSGFun83zone1MSGREG2; ///<_AC0 + UINT8 MSGFun83zone1MSGREG3; ///<_AC1 + UINT8 MSGFun83zone1MSGREG4; ///<_AC2 + UINT8 MSGFun83zone1MSGREG5; ///<_AC3 + UINT8 MSGFun83zone1MSGREG6; ///<_AC4 + UINT8 MSGFun83zone1MSGREG7; ///<_AC5 + UINT8 MSGFun83zone1MSGREG8; ///<_AC6 + UINT8 MSGFun83zone1MSGREG9; ///<_AC7 + UINT8 MSGFun83zone1MSGREGA; ///<_CRT + UINT8 MSGFun83zone1MSGREGB; ///<_PSV + + //EC LDN9 funtion 83 zone 2 + UINT8 MSGFun83zone2MSGREG0; ///<Thermal zone + UINT8 MSGFun83zone2MSGREG1; ///<Thermal zone + UINT8 MSGFun83zone2MSGREG2; ///<_AC0 + UINT8 MSGFun83zone2MSGREG3; ///<_AC1 + UINT8 MSGFun83zone2MSGREG4; ///<_AC2 + UINT8 MSGFun83zone2MSGREG5; ///<_AC3 + UINT8 MSGFun83zone2MSGREG6; ///<_AC4 + UINT8 MSGFun83zone2MSGREG7; ///<_AC5 + UINT8 MSGFun83zone2MSGREG8; ///<_AC6 + UINT8 MSGFun83zone2MSGREG9; ///<_AC7 + UINT8 MSGFun83zone2MSGREGA; ///<_CRT + UINT8 MSGFun83zone2MSGREGB; ///<_PSV + + //EC LDN9 funtion 83 zone 3 + UINT8 MSGFun83zone3MSGREG0; ///<Thermal zone + UINT8 MSGFun83zone3MSGREG1; ///<Thermal zone + UINT8 MSGFun83zone3MSGREG2; ///<_AC0 + UINT8 MSGFun83zone3MSGREG3; ///<_AC1 + UINT8 MSGFun83zone3MSGREG4; ///<_AC2 + UINT8 MSGFun83zone3MSGREG5; ///<_AC3 + UINT8 MSGFun83zone3MSGREG6; ///<_AC4 + UINT8 MSGFun83zone3MSGREG7; ///<_AC5 + UINT8 MSGFun83zone3MSGREG8; ///<_AC6 + UINT8 MSGFun83zone3MSGREG9; ///<_AC7 + UINT8 MSGFun83zone3MSGREGA; ///<_CRT + UINT8 MSGFun83zone3MSGREGB; ///<_PSV + + //EC LDN9 funtion 85 zone 0 + UINT8 MSGFun85zone0MSGREG0; ///<Thermal zone + UINT8 MSGFun85zone0MSGREG1; ///<Thermal zone + UINT8 MSGFun85zone0MSGREG2; ///<AL0 PWM level in percentage (0 - 100%) + UINT8 MSGFun85zone0MSGREG3; ///<AL1 PWM level in percentage (0 - 100%) + UINT8 MSGFun85zone0MSGREG4; ///<AL2 PWM level in percentage (0 - 100%) + UINT8 MSGFun85zone0MSGREG5; ///<AL3 PWM level in percentage (0 - 100%) + UINT8 MSGFun85zone0MSGREG6; ///<AL4 PWM level in percentage (0 - 100%) + UINT8 MSGFun85zone0MSGREG7; ///<AL5 PWM level in percentage (0 - 100%) + UINT8 MSGFun85zone0MSGREG8; ///<AL6 PWM level in percentage (0 - 100%) + UINT8 MSGFun85zone0MSGREG9; ///<AL7 PWM level in percentage (0 - 100%) + + //EC LDN9 funtion 85 zone 1 + UINT8 MSGFun85zone1MSGREG0; ///<Thermal zone + UINT8 MSGFun85zone1MSGREG1; ///<Thermal zone + UINT8 MSGFun85zone1MSGREG2; ///<AL0 PWM level in percentage (0 - 100%) + UINT8 MSGFun85zone1MSGREG3; ///<AL1 PWM level in percentage (0 - 100%) + UINT8 MSGFun85zone1MSGREG4; ///<AL2 PWM level in percentage (0 - 100%) + UINT8 MSGFun85zone1MSGREG5; ///<AL3 PWM level in percentage (0 - 100%) + UINT8 MSGFun85zone1MSGREG6; ///<AL4 PWM level in percentage (0 - 100%) + UINT8 MSGFun85zone1MSGREG7; ///<AL5 PWM level in percentage (0 - 100%) + UINT8 MSGFun85zone1MSGREG8; ///<AL6 PWM level in percentage (0 - 100%) + UINT8 MSGFun85zone1MSGREG9; ///<AL7 PWM level in percentage (0 - 100%) + + //EC LDN9 funtion 85 zone 2 + UINT8 MSGFun85zone2MSGREG0; ///<Thermal zone + UINT8 MSGFun85zone2MSGREG1; ///<Thermal zone + UINT8 MSGFun85zone2MSGREG2; ///<AL0 PWM level in percentage (0 - 100%) + UINT8 MSGFun85zone2MSGREG3; ///<AL1 PWM level in percentage (0 - 100%) + UINT8 MSGFun85zone2MSGREG4; ///<AL2 PWM level in percentage (0 - 100%) + UINT8 MSGFun85zone2MSGREG5; ///<AL3 PWM level in percentage (0 - 100%) + UINT8 MSGFun85zone2MSGREG6; ///<AL4 PWM level in percentage (0 - 100%) + UINT8 MSGFun85zone2MSGREG7; ///<AL5 PWM level in percentage (0 - 100%) + UINT8 MSGFun85zone2MSGREG8; ///<AL6 PWM level in percentage (0 - 100%) + UINT8 MSGFun85zone2MSGREG9; ///<AL7 PWM level in percentage (0 - 100%) + + //EC LDN9 funtion 85 zone 3 + UINT8 MSGFun85zone3MSGREG0; ///<Thermal zone + UINT8 MSGFun85zone3MSGREG1; ///<Thermal zone + UINT8 MSGFun85zone3MSGREG2; ///<AL0 PWM level in percentage (0 - 100%) + UINT8 MSGFun85zone3MSGREG3; ///<AL1 PWM level in percentage (0 - 100%) + UINT8 MSGFun85zone3MSGREG4; ///<AL2 PWM level in percentage (0 - 100%) + UINT8 MSGFun85zone3MSGREG5; ///<AL3 PWM level in percentage (0 - 100%) + UINT8 MSGFun85zone3MSGREG6; ///<AL4 PWM level in percentage (0 - 100%) + UINT8 MSGFun85zone3MSGREG7; ///<AL5 PWM level in percentage (0 - 100%) + UINT8 MSGFun85zone3MSGREG8; ///<AL6 PWM level in percentage (0 - 100%) + UINT8 MSGFun85zone3MSGREG9; ///<AL7 PWM level in percentage (0 - 100%) + + //EC LDN9 funtion 89 TEMPIN channel 0 + UINT8 MSGFun89zone0MSGREG0; ///<Thermal zone + UINT8 MSGFun89zone0MSGREG1; ///<Thermal zone + UINT8 MSGFun89zone0MSGREG2; ///<At DWORD bit 0-7 + UINT8 MSGFun89zone0MSGREG3; ///<At DWORD bit 15-8 + UINT8 MSGFun89zone0MSGREG4; ///<At DWORD bit 23-16 + UINT8 MSGFun89zone0MSGREG5; ///<At DWORD bit 31-24 + UINT8 MSGFun89zone0MSGREG6; ///<Ct DWORD bit 0-7 + UINT8 MSGFun89zone0MSGREG7; ///<Ct DWORD bit 15-8 + UINT8 MSGFun89zone0MSGREG8; ///<Ct DWORD bit 23-16 + UINT8 MSGFun89zone0MSGREG9; ///<Ct DWORD bit 31-24 + UINT8 MSGFun89zone0MSGREGA; ///<Mode bit 0-7 + + //EC LDN9 funtion 89 TEMPIN channel 1 + UINT8 MSGFun89zone1MSGREG0; ///<Thermal zone + UINT8 MSGFun89zone1MSGREG1; ///<Thermal zone + UINT8 MSGFun89zone1MSGREG2; ///<At DWORD bit 0-7 + UINT8 MSGFun89zone1MSGREG3; ///<At DWORD bit 15-8 + UINT8 MSGFun89zone1MSGREG4; ///<At DWORD bit 23-16 + UINT8 MSGFun89zone1MSGREG5; ///<At DWORD bit 31-24 + UINT8 MSGFun89zone1MSGREG6; ///<Ct DWORD bit 0-7 + UINT8 MSGFun89zone1MSGREG7; ///<Ct DWORD bit 15-8 + UINT8 MSGFun89zone1MSGREG8; ///<Ct DWORD bit 23-16 + UINT8 MSGFun89zone1MSGREG9; ///<Ct DWORD bit 31-24 + UINT8 MSGFun89zone1MSGREGA; ///<Mode bit 0-7 + + //EC LDN9 funtion 89 TEMPIN channel 2 + UINT8 MSGFun89zone2MSGREG0; ///<Thermal zone + UINT8 MSGFun89zone2MSGREG1; ///<Thermal zone + UINT8 MSGFun89zone2MSGREG2; ///<At DWORD bit 0-7 + UINT8 MSGFun89zone2MSGREG3; ///<At DWORD bit 15-8 + UINT8 MSGFun89zone2MSGREG4; ///<At DWORD bit 23-16 + UINT8 MSGFun89zone2MSGREG5; ///<At DWORD bit 31-24 + UINT8 MSGFun89zone2MSGREG6; ///<Ct DWORD bit 0-7 + UINT8 MSGFun89zone2MSGREG7; ///<Ct DWORD bit 15-8 + UINT8 MSGFun89zone2MSGREG8; ///<Ct DWORD bit 23-16 + UINT8 MSGFun89zone2MSGREG9; ///<Ct DWORD bit 31-24 + UINT8 MSGFun89zone2MSGREGA; ///<Mode bit 0-7 + + //EC LDN9 funtion 89 TEMPIN channel 3 + UINT8 MSGFun89zone3MSGREG0; ///<Thermal zone + UINT8 MSGFun89zone3MSGREG1; ///<Thermal zone + UINT8 MSGFun89zone3MSGREG2; ///<At DWORD bit 0-7 + UINT8 MSGFun89zone3MSGREG3; ///<At DWORD bit 15-8 + UINT8 MSGFun89zone3MSGREG4; ///<At DWORD bit 23-16 + UINT8 MSGFun89zone3MSGREG5; ///<At DWORD bit 31-24 + UINT8 MSGFun89zone3MSGREG6; ///<Ct DWORD bit 0-7 + UINT8 MSGFun89zone3MSGREG7; ///<Ct DWORD bit 15-8 + UINT8 MSGFun89zone3MSGREG8; ///<Ct DWORD bit 23-16 + UINT8 MSGFun89zone3MSGREG9; ///<Ct DWORD bit 31-24 + UINT8 MSGFun89zone3MSGREGA; ///<Mode bit 0-7 + + // FLAG for Fun83/85/89 support + UINT16 IMCFUNSupportBitMap; /// Bit0=81FunZone0 support(1=On;0=Off); bit1-3=81FunZone1-Zone3;Bit4-7=83FunZone0-Zone3;Bit8-11=85FunZone0-Zone3;Bit11-15=89FunZone0-Zone3; +} EC_struct; +/** SBGPPPORTCONFIG - Southbridge GPP port config structure */ +typedef struct { + UINT32 PortPresent:1; /**< Port connection + * @par + * @li <b>0</b> - Port doesn't have slot. No need to train the link + * @li <b>1</b> - Port connection defined and needs to be trained + */ + UINT32 PortDetected:1; /**< Link training status + * @par + * @li <b>0</b> - EP not detected + * @li <b>1</b> - EP detected + */ + UINT32 PortIsGen2:2; /**< Port link speed configuration + * @par + * @li <b>00</b> - Auto + * @li <b>01</b> - Forced GEN1 + * @li <b>10</b> - Forced GEN2 + * @li <b>11</b> - Reserved + */ + + UINT32 PortHotPlug:1; /**< Support hot plug? + * @par + * @li <b>0</b> - No support + * @li <b>1</b> - support + */ +/** PortMisc - Reserved */ + UINT32 PortMisc:27; +} SBGPPPORTCONFIG; + +/** CODECENTRY - Southbridge HD Audio OEM Codec structure */ +typedef struct _CODECENTRY { +/** Nid - Reserved ?? */ + UINT8 Nid; +/** Byte40 - Reserved ?? */ + UINT32 Byte40; +} CODECENTRY; + +/** CODECTBLLIST - Southbridge HD Audio Codec table list */ +typedef struct _CODECTBLLIST { +/** CodecID - Codec ID */ + UINT32 CodecID; +/** CodecTablePtr - Codec table pointer */ + CODECENTRY* CodecTablePtr; +} CODECTBLLIST; + +/** Sata Controller structure */ +typedef struct _SATAST { + UINT8 SataController:1; /**< SataController + * @par + * Sata Controller + * @li <b>0</b> - disable + * @li <b>1</b> - enable + */ + UINT8 SataIdeCombMdPriSecOpt:1; /**< SataIdeCombMdPriSecOpt - Reserved */ + UINT8 SataSetMaxGen2:1; /**< SataSetMaxGen2 + * @par + * Sata Controller Set to Max Gen2 mode + * @li <b>0</b> - disable + * @li <b>1</b> - enable + */ + UINT8 SataIdeCombinedMode:1; /**< SataIdeCombinedMode + * @par + * Sata IDE Controller set to Combined Mode + * @li <b>0</b> - enable + * @li <b>1</b> - disable + */ +/** SATARefClkSel - Reserved */ + UINT8 SATARefClkSel:2; // 4:5 +/** SATARefDivSel - Reserved */ + UINT8 SATARefDivSel:2; // 6:7 +} SATAST; + +/** _USBST Controller structure + * + * Usb Ohci1 Contoller is define at BIT0 + * - 0:disable 1:enable + * (Bus 0 Dev 18 Func0) * + * Usb Ehci1 Contoller is define at BIT1 + * - 0:disable 1:enable + * (Bus 0 Dev 18 Func2) * + * Usb Ohci2 Contoller is define at BIT2 + * - 0:disable 1:enable + * (Bus 0 Dev 19 Func0) * + * Usb Ehci2 Contoller is define at BIT3 + * - 0:disable 1:enable + * (Bus 0 Dev 19 Func2) * + * Usb Ohci3 Contoller is define at BIT4 + * - 0:disable 1:enable + * (Bus 0 Dev 22 Func0) * + * Usb Ehci3 Contoller is define at BIT5 + * - 0:disable 1:enable + * (Bus 0 Dev 22 Func2) * + * Usb Ohci4 Contoller is define at BIT6 + * - 0:disable 1:enable + * (Bus 0 Dev 20 Func5) * + */ +typedef struct _USBST { + UINT8 Ohci1:1; ///< Ohci0 controller - 0:disable, 1:enable + UINT8 Ehci1:1; ///< Ehci1 controller - 0:disable, 1:enable + UINT8 Ohci2:1; ///< Ohci2 controller - 0:disable, 1:enable + UINT8 Ehci2:1; ///< Ehci2 controller - 0:disable, 1:enable + UINT8 Ohci3:1; ///< Ohci3 controller - 0:disable, 1:enable + UINT8 Ehci3:1; ///< Ehci3 controller - 0:disable, 1:enable + UINT8 Ohci4:1; ///< Ohci4 controller - 0:disable, 1:enable + UINT8 UTemp:1; ///< Reserved +} USBST; + +/** + * _AZALIAPIN - HID Azalia or GPIO define structure. + * + */ +typedef struct _AZALIAPIN { + UINT8 AzaliaSdin0:2; /**< AzaliaSdin0 + * @par + * SDIN0 is define at BIT0 & BIT1 + * @li <b>00</b> - GPIO PIN + * @li <b>10</b> - As a Azalia SDIN pin + */ + UINT8 AzaliaSdin1:2; /**< AzaliaSdin1 + * @par + * SDIN0 is define at BIT2 & BIT3 + * @li <b>00</b> - GPIO PIN + * @li <b>10</b> - As a Azalia SDIN pin + */ + UINT8 AzaliaSdin2:2; /**< AzaliaSdin2 + * @par + * SDIN0 is define at BIT4 & BIT5 + * @li <b>00</b> - GPIO PIN + * @li <b>10</b> - As a Azalia SDIN pin + */ + UINT8 AzaliaSdin3:2; /**< AzaliaSdin3 + * @par + * SDIN0 is define at BIT6 & BIT7 + * @li <b>00</b> - GPIO PIN + * @li <b>10</b> - As a Azalia SDIN pin + */ +} AZALIAPIN; + +/** AMDSBCFG - Southbridge CIMx configuration structure (Main) */ +typedef struct _AMDSBCFG { +/** StdHeader - Standard header for all AGESA/CIMx services. */ + AMD_CONFIG_PARAMS StdHeader; + +/** BuildParameters - The STATIC platform information for CIMx Module. */ + BUILDPARAM BuildParameters; + //offset 90 bytes (32-121) + //MsgXchgBiosCimx //offset 4 bytes (122-125) + // SATA Configuration + + union /**< union - Reserved */ + { /**< SATAMODE - Sata Controller structure */ +/** SataModeReg - Reserved */ + UINT8 SataModeReg; +/** SataMode - Reserved */ + SATAST SataMode; + } SATAMODE; +/** S3Resume - Flag of ACPI S3 Resume. */ + UINT8 S3Resume:1; // 8 +/** RebootRequired - Flag of Reboot system is required. */ + UINT8 RebootRequired:1; // 9 +/** SbSpiSpeedSupport - Reserved */ + UINT8 SbSpiSpeedSupport:1; // 10 +/**< SpreadSpectrum + * @par + * Spread Spectrum function + * @li <b>0</b> - disable + * @li <b>1</b> - enable + */ + UINT8 SpreadSpectrum:1; // 11 +/** NbSbGen2 - Reserved */ + UINT8 NbSbGen2:1; // 12 + UINT8 GppGen2:1; // 13 + UINT8 GppMemWrImprove:1; // 14 +/** MsgXchgBiosCimxReserved - Reserved */ + UINT8 MsgXchgBiosCimxReserved:1; // 15 (BB USED) +/**< SataClass - SATA Controller mode [16:18] + * @par + * @li <b>000</b> - Native IDE mode + * @li <b>001</b> - RAID mode + * @li <b>010</b> - AHCI mode + * @li <b>011</b> - Legacy IDE mode + * @li <b>100</b> - IDE->AHCI mode + * @li <b>101</b> - AHCI mode as 4394 ID (AMD driver) + * @li <b>110</b> - IDE->AHCI mode as 4394 ID (AMD driver) + */ + UINT16 SataClass:3; // 16:18 +/**< Sata IDE Controller mode + * @par + * @li <b>0</b> - Legacy IDE mode + * @li <b>1</b> - Native IDE mode + */ + UINT16 SataIdeMode:1; // 19 +/**< SataEspPort - SATA port is external accessible on a signal only connector (eSATA:) + * @par + * @li <b> BIT0 </b> - PORT0 set as ESP port + * @li <b> BIT1 </b> - PORT1 set as ESP port + * @li <b> BIT2 </b> - PORT2 set as ESP port + * @li <b> BIT3 </b> - PORT3 set as ESP port + * @li <b> BIT4 </b> - PORT4 set as ESP port + * @li <b> BIT5 </b> - PORT5 set as ESP port + */ + UINT16 SataEspPort:6; // 20:25 +/** SataPortPower - Reserved */ + UINT16 SataPortPower:6; // 31:26 + + // SATA Debug Option //offset 4 bytes (126-129) + +/**< SataPortMode - Force Each PORT to GEN1/GEN2 mode + * @par + * @li <b> 0 </b> Auto for each PORTs + * @li <b> BIT0 = 1</b> - PORT0 set to GEN1 + * @li <b> BIT1 = 1</b> - PORT0 set to GEN2 + * @li <b> BIT2 = 1</b> - PORT1 set to GEN1 + * @li <b> BIT3 = 1</b> - PORT1 set to GEN2 + * @li <b> BIT4 = 1</b> - PORT2 set to GEN1 + * @li <b> BIT5 = 1</b> - PORT2 set to GEN2 + * @li <b> BIT6 = 1</b> - PORT3 set to GEN1 + * @li <b> BIT7 = 1</b> - PORT3 set to GEN2 + * @li <b> BIT8 = 1</b> - PORT4 set to GEN1 + * @li <b> BIT9 = 1</b> - PORT4 set to GEN2 + * @li <b> BIT10 = 1</b> - PORT5 set to GEN1 + * @li <b> BIT11 = 1</b> - PORT5 set to GEN2 + */ + UINT32 SataPortMode:12; //11:0 +/** SATAClkSelOpt - Reserved */ + UINT32 SATAClkSelOpt:4; // Removed from coding side +/** SataAggrLinkPmCap - Reserved */ + UINT32 SataAggrLinkPmCap:1; //16, 0:OFF 1:ON +/** SataPortMultCap - Reserved */ + UINT32 SataPortMultCap:1; //17, 0:OFF 1:ON +/** SataClkAutoOff - Reserved */ + UINT32 SataClkAutoOff:1; //18, AutoClockOff 0:Disabled, 1:Enabled +/** SataPscCap - Reserved */ + UINT32 SataPscCap:1; //19, 0:Enable PSC capability, 1:Disable PSC capability +/** BIOSOSHandoff - Reserved */ + UINT32 BIOSOSHandoff:1; //20 +/** SataFisBasedSwitching - Reserved */ + UINT32 SataFisBasedSwitching:1; //21 +/** SataCccSupport - Reserved */ + UINT32 SataCccSupport:1; //22 +/** SataSscCap - Reserved */ + UINT32 SataSscCap:1; //23, 0:Enable SSC capability, 1:Disable SSC capability +/** SataMsiCapability - Reserved */ + UINT32 SataMsiCapability:1; //24 0:Hidden 1:Visible. This feature is disabled per RPR, but remains the interface. +/** SataForceRaid - Reserved */ + UINT32 SataForceRaid:1; //25 0:No function 1:Force RAID +/** SataDebugDummy - Reserved */ + UINT32 SataDebugDummy:6; //31:26 +// +// USB Configuration //offset 4 bytes (130-133) +// + +/** USBDeviceConfig - USB Controller Configuration + * + * - Usb Ohci1 Contoller is define at BIT0 + * - 0:disable 1:enable + * (Bus 0 Dev 18 Func0) * + * - Usb Ehci1 Contoller is define at BIT1 + * - 0:disable 1:enable + * (Bus 0 Dev 18 Func2) * + * - Usb Ohci2 Contoller is define at BIT2 + * - 0:disable 1:enable + * (Bus 0 Dev 19 Func0) * + * - Usb Ehci2 Contoller is define at BIT3 + * - 0:disable 1:enable + * (Bus 0 Dev 19 Func2) * + * - Usb Ohci3 Contoller is define at BIT4 + * - 0:disable 1:enable + * (Bus 0 Dev 22 Func0) * + * - Usb Ehci3 Contoller is define at BIT5 + * - 0:disable 1:enable + * (Bus 0 Dev 22 Func2) * + * - Usb Ohci4 Contoller is define at BIT6 + * - 0:disable 1:enable + * (Bus 0 Dev 20 Func5) * + */ + union /**< union - Reserved */ + { /**< USBMODE - USB Controller structure */ +/** SataModeReg - Reserved */ + UINT8 UsbModeReg; +/** SataMode - Reserved */ + USBST UsbMode; + } USBMODE; +/*! + */ + +/**< GecConfig + * @par + * InChip Gbit NIC + * @li <b>1</b> - disable + * @li <b>0</b> - enable + */ + UINT8 GecConfig:1; //8 + +/**< IrConfig + * @par + * Ir Controller setting + * @li <b>00 </b> - disable + * @li <b>01 </b> - Rx and Tx0 + * @li <b>10 </b> - Rx and Tx1 + * @li <b>11 </b> - Rx and both Tx0,Tx1 + */ + UINT8 IrConfig:2; //9:10 + +/** GecDummy - Reserved */ + UINT8 GecDummy:5; //15:11 + + //Azalia Configuration + +/**< AzaliaController - Azalia Controller Configuration + * @par + * Azalia Controller [0-1] + * @li <b>0</b> - Auto : Detect Azalia controller automatically. + * @li <b>1</b> - Diable : Disable Azalia controller. + * @li <b>2</b> - Enable : Enable Azalia controller. + */ + UINT8 AzaliaController:2; //17:16 +/**< AzaliaPinCfg - Azalia Controller SDIN pin Configuration + * @par + * @li <b>0</b> - disable + * @li <b>1</b> - enable + */ + UINT8 AzaliaPinCfg:1; //18 +/**< AzaliaFrontPanel - Azalia Controller Front Panel Configuration + * @par + * Support Front Panel configuration + * @li <b>0</b> - Auto + * @li <b>1</b> - disable + * @li <b>2</b> - enable + */ + UINT8 AzaliaFrontPanel:2; //20:19 +/**< FrontPanelDetected - Force Azalia Controller Front Panel Configuration + * @par + * Force Front Panel configuration + * @li <b>0</b> - Not Detected + * @li <b>1</b> - Detected + */ + UINT8 FrontPanelDetected:1; //21 +/**< AzaliaSnoop - Azalia Controller Snoop feature Configuration + * @par + * Azalia Controller Snoop feature Configuration + * @li <b>0</b> - disable + * @li <b>1</b> - enable + */ + UINT8 AzaliaSnoop:1; //22 +/** AzaliaDummy - Reserved */ + UINT8 AzaliaDummy:1; //23 + + union + { +/**< AzaliaSdinPin - Azalia Controller SDIN pin Configuration + * + * SDIN0 is define at BIT0 & BIT1 + * - 00: GPIO PIN + * - 01: Reserved + * - 10: As a Azalia SDIN pin + * + * SDIN1 is define at BIT2 & BIT3 + * * Config same as SDIN0 + * SDIN2 is define at BIT4 & BIT5 + * * Config same as SDIN0 + * SDIN3 is define at BIT6 & BIT7 + * * Config same as SDIN0 + */ + UINT8 AzaliaSdinPin; + AZALIAPIN AzaliaConfig; + } AZALIACONFIG; + +/** AZOEMTBL - Azalia Controller OEM Codec Table Pointer + * + */ + union + { + PLACEHOLDER PlaceHolder; + CODECTBLLIST* pAzaliaOemCodecTablePtr; //offset 4 bytes (134-137) + } AZOEMTBL; + +/** AZOEMFPTBL - Azalia Controller Front Panel OEM Table Pointer + * + */ + union + { + PLACEHOLDER PlaceHolder; + VOID* pAzaliaOemFpCodecTablePtr; //offset 4 bytes (138-141) + } AZOEMFPTBL; + + //Miscellaneous Configuration //offset 4 bytes (142-145) +/** AnyHT200MhzLink - Reserved */ + UINT32 AnyHT200MhzLink:1; //0 +/**< HpetTimer - South Bridge Hpet Timer Configuration + * @par + * @li <b>0</b> - disable + * @li <b>1</b> - enable + */ + UINT32 HpetTimer:1; //1 +/**< PciClks - PCI Slot Clock Control + * @par + * PCI SLOT 0 define at BIT0 + * - 00: disable + * - 01: enable + * + * PCI SLOT 1 define at BIT1 + * * Config same as PCI SLOT0 + * PCI SLOT 2 define at BIT2 + * * Config same as PCI SLOT0 + * PCI SLOT 3 define at BIT3 + * * Config same as PCI SLOT0 + * PCI SLOT 4 define at BIT4 + * * Config same as PCI SLOT0 + */ + UINT32 PciClks:5; //2:6 +/** MiscReserved1 - Reserved */ + UINT32 MiscReserved1:4; //9:7, Reserved +/** MobilePowerSavings - Debug function Reserved */ + UINT32 MobilePowerSavings:1; //11, 0:Disable, 1:Enable Power saving features especially for Mobile platform +/** MiscDummy1 - Debug function Reserved */ + UINT32 MiscDummy1:1; +/** NativePcieSupport - Debug function Reserved */ + UINT32 NativePcieSupport:1; //13, 0:Enable, 1:Disabled +/** FlashPinConfig - Debug function Reserved */ + UINT32 FlashPinConfig:1; //14, 0:desktop mode 1:mobile mode +/** UsbPhyPowerDown - Debug function Reserved */ + UINT32 UsbPhyPowerDown:1; //15 +/** PcibClkStopOverride - Debug function Reserved */ + UINT32 PcibClkStopOverride:10; //25:16 +/**< HpetMsiDis - South Bridge HPET MSI Configuration + * @par + * @li <b>1</b> - disable + * @li <b>0</b> - enable + */ + UINT32 HpetMsiDis:1; //26 +/**< ResetCpuOnSyncFlood - Rest CPU on Sync Flood + * @par + * @li <b>0</b> - disable + * @li <b>1</b> - enable + */ + UINT32 ResetCpuOnSyncFlood:1; //27 +/**< LdtStpDisable - LdtStp# output disable + * @par + * @li <b>0</b> - LdtStp# output enable + * @li <b>1</b> - LdtStp# output disable + */ + UINT32 LdtStpDisable:1; //28 +/**< MTC1e - Message Triggered C1e + * @par + * @li <b>0</b> - disable + * @li <b>1</b> - enable + */ + UINT32 MTC1e:1; //29 +/** MiscDummy - Reserved */ + UINT32 MiscDummy:2; //31:30 + + //DebugOptions //offset 4 bytes (146-149) +/** PcibAutoClkCtrlLow - Debug function Reserved */ + UINT32 PcibAutoClkCtrlLow:16; +/** PcibAutoClkCtrlHigh - Debug function Reserved */ + UINT32 PcibAutoClkCtrlHigh:16; + +/**< OEMPROGTBL - ACPI MMIO register setting table OEM override + * @par + * OEM table for customer override ACPI MMIO register in their code. + */ + union + { + PLACEHOLDER OemProgrammingTablePtr; //offset 4 bytes (150-153) + VOID *OemProgrammingTablePtr_Ptr; + } OEMPROGTBL; + + //Gpp Configuration //offset 24 bytes total (154-177) + union { + UINT32 PORTCFG32; + SBGPPPORTCONFIG PortCfg; + } PORTCONFIG[MAX_GPP_PORTS]; //offset 16 bytes + + UINT32 GppLinkConfig; // GPP_LINK_CONFIG = PCIE_GPP_Enable[3:0] + // 0000 - Port ABCD -> 4:0:0:0 + // 0001 - N/A + // 0010 - Port ABCD -> 2:2:0:0 + // 0011 - Port ABCD -> 2:1:1:0 + // 0100 - Port ABCD -> 1:1:1:1 + // + UINT32 GppFoundGfxDev:4; //3:0 If port A-D (mapped to bit [3:0]) has GFX EP detected + UINT32 CoreGen2Enable:1; //4 + UINT32 GppFunctionEnable:1; //5 + UINT32 GppUnhidePorts:1; //6 + UINT32 AlinkPhyPllPowerDown:1; //7 + UINT32 GppConfigDummy1:2; //9:8 + UINT32 GppLaneReversal:1; //10 + UINT32 GppPhyPllPowerDown:1; //11 + UINT32 GppCompliance :1; //12 + UINT32 GppPortAspm:8; //20:13 ASPM state for GPP ports, 14:13 for port0, ..., 20:19 for port3 + // 00 - Disabled + // 01 - L0s + // 10 - L1 + // 11 - L0s + L1 + // + UINT32 GppConfigDummy:11; //31:21 + + //TempMMIO //offset 4 bytes (178-181) + UINT32 TempMMIO; + + // DebugOption2 + UINT32 GecPhyStatus:1; + UINT32 GecDebugOptionDummy:7; + UINT32 SBGecPwr:2; + UINT32 SBGecDebugBus:1; + UINT32 DebugOption2Dummy1:1; + UINT32 DebugOption2Dummy2:1; + UINT32 SbPcieOrderRule:1; + UINT32 SbUsbPll:1; + UINT32 AcDcMsg:1; + UINT32 TimerTickTrack:1; + UINT32 ClockInterruptTag:1; + UINT32 OhciTrafficHanding:1; + UINT32 EhciTrafficHanding:1; + UINT32 FusionMsgCMultiCore:1; + UINT32 FusionMsgCStage:1; +/**< UsbRxMode - CG PLL multiplier for USB Rx 1.1 mode + * @par + * @li <b>0</b> - disable + * @li <b>1</b> - enable + */ + UINT32 UsbRxMode:1; + UINT32 DebugOption2Dummy3:9; // + + union + { + PLACEHOLDER DynamicGecRomAddressPtr; //offset 4 bytes (182-185) + VOID *DynamicGecRomAddress_Ptr; + } DYNAMICGECROM; + EC_struct Pecstruct; +} AMDSBCFG; + +/** SMMSERVICESTRUC- Southbridge SMI service structure */ +typedef struct _SMMSERVICESTRUC { +/** enableRegNum - Reserved */ + UINT8 enableRegNum; +/** enableBit - Reserved */ + UINT8 enableBit; +/** statusRegNum - Reserved */ + UINT8 statusRegNum; +/** statusBit - Reserved */ + UINT8 statusBit; +/** *debugMessage- Reserved */ + CHAR8 *debugMessage; +/** serviceRoutine - Reserved */ + SMM_SERVICE_ROUTINE serviceRoutine; +} SMMSERVICESTRUC; + +#ifndef _NB_REG8MASK_ + +/** + * - Byte Register R/W structure + * + */ + typedef struct _Reg8Mask { +/** bRegIndex - Reserved */ + UINT8 bRegIndex; +/** bANDMask - Reserved */ + UINT8 bANDMask; +/** bORMask - Reserved */ + UINT8 bORMask; + } REG8MASK; +#endif + +/** + * - SATA Phy setting structure + * + */ +typedef struct _SATAPHYSETTING { +/** wPhyCoreControl - Reserved */ + UINT16 wPhyCoreControl; +/** dwPhyFineTune - Reserved */ + UINT32 dwPhyFineTune; +} SATAPHYSETTING; + +/** + * _ABTblEntry - AB link register table R/W structure + * + */ +typedef struct _ABTblEntry { + /** regType : AB Register Type (ABCFG, AXCFG and so on) */ + UINT8 regType; + /** regIndex : AB Register Index */ + UINT32 regIndex; + /** regMask : AB Register Mask */ + UINT32 regMask; + /** regData : AB Register Data */ + UINT32 regData; +} ABTBLENTRY; + +/** + * _AcpiRegWrite - ACPI MMIO register R/W structure + * + */ +typedef struct _AcpiRegWrite { + /** MmioBase : Index of Soubridge block (For instence GPIO_BASE:0x01 SMI_BASE:0x02) */ + UINT8 MmioBase; + /** MmioReg : Register index */ + UINT8 MmioReg; + /** DataANDMask : AND Register Data */ + UINT8 DataANDMask; + /** DataOrMask : Or Register Data */ + UINT8 DataOrMask; +} AcpiRegWrite; + +/** + * PCI_ADDRESS - PCI access structure + * + */ +#define PCI_ADDRESS(bus, dev, func, reg) \ +(UINT32) ( (((UINT32)bus) << 24) + (((UINT32)dev) << 19) + (((UINT32)func) << 16) + ((UINT32)reg) ) + +/** + * CIM_STATUS - CIMx module function return code + */ +typedef UINT32 CIM_STATUS; +/** + * CIM_SUCCESS - Executed without error + */ +#define CIM_SUCCESS 0x00000000 +/** + * CIM_ERROR - call error + */ +#define CIM_ERROR 0x80000000 +/** + * CIM_UNSUPPORTED - function does not support + */ +#define CIM_UNSUPPORTED 0x80000001 + +#pragma pack (pop) + +/** + * DISABLED - Define disable in module + */ +#define DISABLED 0 +/** + * ENABLED - Define enable in module + */ +#define ENABLED 1 + +// mov al, code +// out 80h, al +// jmp $ + +/** + * DBG_STOP - define a debug point + */ +#define DBG_STOP __asm _emit 0xEB __asm _emit 0xFE + +/** + * STOP_CODE - define a debug point + * Warning: AL gets destroyed! + */ +#define STOP_CODE (code) __asm __emit 0xB0 __asm __emit code __asm __emit 0xE6 \ + __asm __emit 0x80 __asm _emit 0xEB __asm _emit 0xFE + +#endif // _AMD_SBTYPE_H_
Added: trunk/src/vendorcode/amd/cimx/sb800/SMM.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/SMM.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,76 @@ +/** + * @file + * + * Southbridge SMM service function + * + * Prepare SMM service module for IBV call Southbridge SMI service routine. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: CIMx-SB + * @e sub-project: + * @e $Revision:$ @e $Date:$ + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include "SBPLATFORM.h" + +// +// Declaration of local functions +// + +/** + * Southbridge SMI service module + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +sbSmmService ( + IN AMDSBCFG* pConfig + ) +{ + AMDSBCFG* pTmp; //lx-dummy for /W4 build + pTmp = pConfig; +} + +/** + * softwareSMIservice - Software SMI service + * + * @param[in] VOID Southbridge software SMI service ID. + * + */ +VOID +softwareSMIservice ( + IN VOID + ) +{ +} + + + + +
Added: trunk/src/vendorcode/amd/cimx/sb800/SbModInf.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/SbModInf.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,64 @@ +/** + * @file + * + * Function dispatcher. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: CIMx-SB + * @e sub-project: + * @e $Revision:$ @e $Date:$ + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "SBPLATFORM.h" + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + + +/// module header +VOLATILE AMD_MODULE_HEADER mNbModuleHeader = { + 'DOM$', ///< Standard AMD module signature + CIMX_SB_ID, ///< Chipset ID + CIMX_SB_REVISION, ///< CIMx version + AmdSbDispatcher, ///< Pointer to the module entry + NULL ///< Pointer link to next module header +};
Added: trunk/src/vendorcode/amd/cimx/sb800/USB.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/vendorcode/amd/cimx/sb800/USB.c Sat Jan 1 18:44:07 2011 (r6229) @@ -0,0 +1,421 @@ +/** + * @file + * + * Config Southbridge USB controller + * + * Init USB features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: CIMx-SB + * @e sub-project: + * @e $Revision:$ @e $Date:$ + * + */ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + + +#include "SBPLATFORM.h" + +// +// Declaration of local functions +// + +/** + * EhciInitAfterPciInit - Config USB controller after PCI emulation + * + * @param[in] Value Controller PCI config address (bus# + device# + function#) + * @param[in] pConfig Southbridge configuration structure pointer. + */ +VOID EhciInitAfterPciInit (IN UINT32 Value, IN AMDSBCFG* pConfig); +/** + * OhciInitAfterPciInit - Config USB OHCI controller after PCI emulation + * + * @param[in] Value Controller PCI config address (bus# + device# + function#) + * @param[in] pConfig Southbridge configuration structure pointer. + */ +VOID OhciInitAfterPciInit (IN UINT32 Value, IN AMDSBCFG* pConfig); + +/** + * SetEhciP11Wr - FIXME + * + * @param[in] Value Controller PCI config address (bus# + device# + function#) + * @param[in] pConfig Southbridge configuration structure pointer. + */ +UINT32 SetEhciPllWr (IN UINT32 Value, IN AMDSBCFG* pConfig); + + +/** + * usbInitBeforePciEnum - Config USB controller before PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +usbInitBeforePciEnum ( + IN AMDSBCFG* pConfig + ) +{ + // Disabled All USB controller + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, BIT7, 0); + // Clear PM_IO 0x65[4] UsbResetByPciRstEnable, Set this bit so that usb gets reset whenever there is PCIRST. + // Enable UsbResumeEnable (USB PME) * Default value + // In SB700 USB SleepCtrl set as BIT10+BIT9, but SB800 default is BIT9+BIT8 (6 uframes) + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint16 | S3_SAVE, ~BIT2, BIT2 + BIT7 + BIT8 + BIT9); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, 0, pConfig->USBMODE.UsbModeReg); +} + +/** + * usbInitAfterPciInit - Config USB controller after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +usbInitAfterPciInit ( + IN AMDSBCFG* pConfig + ) +{ + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGED, AccWidthUint8, ~BIT1, BIT1); + + usb1EhciInitAfterPciInit (pConfig); + usb2EhciInitAfterPciInit (pConfig); + usb3EhciInitAfterPciInit (pConfig); + usb1OhciInitAfterPciInit (pConfig); + usb2OhciInitAfterPciInit (pConfig); + usb3OhciInitAfterPciInit (pConfig); + usb4OhciInitAfterPciInit (pConfig); + + if ( pConfig->UsbPhyPowerDown ) { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint8, ~BIT0, BIT0); + } else + { + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint8, ~BIT0, 0); + } + +} + +/** + * usb1EhciInitAfterPciInit - Config USB1 EHCI controller after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +usb1EhciInitAfterPciInit ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 ddDeviceId; + ddDeviceId = (USB1_EHCI_BUS_DEV_FUN << 16); + EhciInitAfterPciInit (ddDeviceId, pConfig); +} + +/** + * usb2EhciInitAfterPciInit - Config USB2 EHCI controller after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +usb2EhciInitAfterPciInit ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 ddDeviceId; + ddDeviceId = (USB2_EHCI_BUS_DEV_FUN << 16); + EhciInitAfterPciInit (ddDeviceId, pConfig); +} + +/** + * usb3EhciInitAfterPciInit - Config USB3 EHCI controller after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +usb3EhciInitAfterPciInit ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 ddDeviceId; + ddDeviceId = (USB3_EHCI_BUS_DEV_FUN << 16); + EhciInitAfterPciInit (ddDeviceId, pConfig); +} + +VOID +EhciInitAfterPciInit ( + IN UINT32 Value, + IN AMDSBCFG* pConfig + ) +{ + UINT32 ddBarAddress; + UINT32 ddVar; + //Get BAR address + ReadPCI ((UINT32) Value + SB_EHCI_REG10, AccWidthUint32, &ddBarAddress); + if ( (ddBarAddress != - 1) && (ddBarAddress != 0) ) { + //Enable Memory access + RWPCI ((UINT32) Value + SB_EHCI_REG04, AccWidthUint8, 0, BIT1); + if (pConfig->BuildParameters.EhciSsid != NULL ) { + RWPCI ((UINT32) Value + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.EhciSsid); + } + //USB Common PHY CAL & Control Register setting + ddVar = 0x00020F00; + WriteMEM (ddBarAddress + SB_EHCI_BAR_REGC0, AccWidthUint32, &ddVar); + // RPR IN AND OUT DATA PACKET FIFO THRESHOLD + // EHCI BAR 0xA4 //IN threshold bits[7:0]=0x40 //OUT threshold bits[23:16]=0x40 + RWMEM (ddBarAddress + SB_EHCI_BAR_REGA4, AccWidthUint32, 0xFF00FF00, 0x00400040); + // RPR EHCI Dynamic Clock Gating Feature + RWMEM (ddBarAddress + SB_EHCI_BAR_REGBC, AccWidthUint32, ~BIT12, 0); + // RPR Enable adding extra flops to PHY rsync path + // Step 1: + // EHCI_BAR 0xB4 [6] = 1 + // EHCI_BAR 0xB4 [7] = 0 + // EHCI_BAR 0xB4 [12] = 0 ("VLoad") + // All other bit field untouched + // Step 2: + // EHCI_BAR 0xB4[12] = 1 + RWMEM (ddBarAddress + SB_EHCI_BAR_REGB4, AccWidthUint32, ~(BIT6 + BIT7 + BIT12), 0x00); + RWMEM (ddBarAddress + SB_EHCI_BAR_REGB4, AccWidthUint32, ~BIT12, BIT12); + //Set EHCI_pci_configx50[6]='1' to disable EHCI MSI support + //RPR recommended setting "EHCI Async Park Mode" + //Set EHCI_pci_configx50[23]='0' to enable "EHCI Async Park Mode support" + //RPR Enabling EHCI Async Stop Enhancement + //Set EHCI_pci_configx50[29]='1' to disableEnabling EHCI Async Stop Enhancement + RWPCI ((UINT32) Value + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(BIT23), BIT29 + BIT23 + BIT8 + BIT6); + // RPR recommended setting "EHCI Advance PHY Power Savings" + // Set EHCI_pci_configx50[31]='1' + // Fix for EHCI controller driver yellow sign issue under device manager + // when used in conjunction with HSET tool driver. EHCI PCI config 0x50[20]=1 + RWPCI ((UINT32) Value + SB_EHCI_REG50 + 2, AccWidthUint16 | S3_SAVE, (UINT16)0xFFFF, BIT15); + // RPR USB Delay A-Link Express L1 State + // RPR PING Response Fix Enable EHCI_PCI_Config x54[1] = 1 + // RPR Empty-list Detection Fix Enable EHCI_PCI_Config x54[3] = 1 + RWPCI ((UINT32) Value + SB_EHCI_REG54, AccWidthUint32 | S3_SAVE, ~BIT0, BIT0); + if ( pConfig->BuildParameters.UsbMsi) { + RWPCI ((UINT32) Value + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~BIT6, 0x00); + } + } +} + +/** + * usb1OhciInitAfterPciInit - Config USB1 OHCI controller after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +usb1OhciInitAfterPciInit ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 ddDeviceId; + ddDeviceId = (USB1_OHCI_BUS_DEV_FUN << 16); + OhciInitAfterPciInit (ddDeviceId, pConfig); +} + +/** + * usb2OhciInitAfterPciInit - Config USB2 OHCI controller after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +usb2OhciInitAfterPciInit ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 ddDeviceId; + ddDeviceId = (USB2_OHCI_BUS_DEV_FUN << 16); + OhciInitAfterPciInit (ddDeviceId, pConfig); +} + +/** + * usb3OhciInitAfterPciInit - Config USB3 OHCI controller after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +usb3OhciInitAfterPciInit ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 ddDeviceId; + ddDeviceId = (USB3_OHCI_BUS_DEV_FUN << 16); + OhciInitAfterPciInit (ddDeviceId, pConfig); +} + +/** + * usb4OhciInitAfterPciInit - Config USB4 OHCI controller after PCI emulation + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +VOID +usb4OhciInitAfterPciInit ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 ddDeviceId; + ddDeviceId = (USB4_OHCI_BUS_DEV_FUN << 16); + OhciInitAfterPciInit (ddDeviceId, pConfig); + if (pConfig->BuildParameters.Ohci4Ssid != NULL ) { + RWPCI ((USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.Ohci4Ssid); + } +} + +VOID +OhciInitAfterPciInit ( + IN UINT32 Value, + IN AMDSBCFG* pConfig + ) +{ + // Disable the MSI capability of USB host controllers + RWPCI ((UINT32) Value + SB_OHCI_REG40 + 1, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); + RWPCI ((UINT32) Value + SB_OHCI_REG50, AccWidthUint8 | S3_SAVE, ~(BIT5 + BIT12), 0x00); + // RPR USB SMI Handshake + RWPCI ((UINT32) Value + SB_OHCI_REG50 + 1, AccWidthUint8 | S3_SAVE, ~BIT4, 0x00); + // SB02186 + RWPCI ((UINT32) Value + SB_OHCI_REG50 + 1, AccWidthUint8 | S3_SAVE, 0xFC, 0x00); + if (Value != (USB4_OHCI_BUS_DEV_FUN << 16)) { + if ( pConfig->BuildParameters.OhciSsid != NULL ) { + RWPCI ((UINT32) Value + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.OhciSsid); + } + } + //RPR recommended setting to, enable fix to cover the corner case S3 wake up issue from some USB 1.1 devices + //OHCI 0_PCI_Config 0x50[30] = 1 + RWPCI ((UINT32) Value + SB_OHCI_REG50 + 3, AccWidthUint8 | S3_SAVE, ~BIT6, BIT6); + if ( pConfig->BuildParameters.UsbMsi) { + RWPCI ((UINT32) Value + SB_OHCI_REG40 + 1, AccWidthUint8 | S3_SAVE, ~BIT0, 0x00); + RWPCI ((UINT32) Value + SB_OHCI_REG50, AccWidthUint8 | S3_SAVE, ~BIT5, BIT5); + } +} + + +UINT32 +SetEhciPllWr ( + IN UINT32 Value, + IN AMDSBCFG* pConfig + ) +{ + UINT32 ddRetureValue; + UINT32 ddBarAddress; + UINT16 dwVar; + UINT16 dwData; + UINT8 portSC; + ddRetureValue = 0; + dwData = 0; + // Memory, and etc. + //_asm { jmp $}; + RWPCI ((UINT32) Value + 0xC4, AccWidthUint8, 0xF0, 0x00); + RWPCI ((UINT32) Value + 0x04, AccWidthUint8, 0xFF, 0x02); + // Get Bar address + ReadPCI ((UINT32) Value + 0x10, AccWidthUint32, &ddBarAddress); + for (portSC = 0x64; portSC < 0x75; portSC += 0x04 ) { + // Get OHCI command registers + ReadMEM (ddBarAddress + portSC, AccWidthUint16, &dwVar); + if ( dwVar & BIT6 ) { + ddRetureValue = ddBarAddress + portSC; + RWMEM (ddBarAddress + portSC, AccWidthUint16, ~BIT6, 0); + for (;;) { + SbStall (5); + ReadMEM (ddBarAddress + portSC, AccWidthUint16, &dwData); + if (dwData == 0x1005) break; + } + dwData = 0; + } + } + return ddRetureValue; +} + +VOID +usbSetPllDuringS3 ( + IN AMDSBCFG* pConfig + ) +{ + UINT32 resumeEhciPortTmp; + UINT32 resumeEhciPort; + resumeEhciPortTmp = 0; + resumeEhciPort = 0; +// UINT32 ddDeviceId; +//if Force Port Resume == 1 +// { +// clear Force Port Resume; +// while (!(PORTSC == 0x1005)){wait 5 us; read PORTSC;} +// } + if (pConfig->USBMODE.UsbModeReg & BIT1) { + resumeEhciPortTmp = SetEhciPllWr (USB1_EHCI_BUS_DEV_FUN << 16, pConfig); + if (resumeEhciPortTmp > 0) resumeEhciPort = resumeEhciPortTmp; + } + if (pConfig->USBMODE.UsbModeReg & BIT3) { + resumeEhciPortTmp = SetEhciPllWr (USB2_EHCI_BUS_DEV_FUN << 16, pConfig); + if (resumeEhciPortTmp > 0) resumeEhciPort = resumeEhciPortTmp; + } + if (pConfig->USBMODE.UsbModeReg & BIT5) { + resumeEhciPortTmp = SetEhciPllWr (USB3_EHCI_BUS_DEV_FUN << 16, pConfig); + if (resumeEhciPortTmp > 0) resumeEhciPort = resumeEhciPortTmp; + } + + RWPCI ((UINT32) (USB1_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, 0); + RWPCI ((UINT32) (USB2_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, 0); + RWPCI ((UINT32) (USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, 0); + RWPCI ((UINT32) (USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, 0); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF3, AccWidthUint8, 0, 0x20); + SbStall (10); + RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF3, AccWidthUint8, 0, 0x00); + RWPCI ((UINT32) (USB1_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, BIT29); + RWPCI ((UINT32) (USB2_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, BIT29); + RWPCI ((UINT32) (USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, BIT29); + RWPCI ((UINT32) (USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, BIT29); + + if (resumeEhciPort > 0) { + RWMEM (resumeEhciPort, AccWidthUint8, ~BIT7, BIT7); + SbStall (4000); + RWMEM (resumeEhciPort, AccWidthUint8, ~BIT6, BIT6); + } + + RWPCI ((UINT32) (USB1_EHCI_BUS_DEV_FUN << 16) + 0xC4, AccWidthUint8, 0xF0, 0x03); + RWPCI ((UINT32) (USB2_EHCI_BUS_DEV_FUN << 16) + 0xC4, AccWidthUint8, 0xF0, 0x03); + RWPCI ((UINT32) (USB3_EHCI_BUS_DEV_FUN << 16) + 0xC4, AccWidthUint8, 0xF0, 0x03); + +} +
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