the following patch was just integrated into master: commit 62f100b02888c2de21d61caf5d850f1184e8be1a Author: Aaron Durbin adurbin@chromium.org Date: Wed Nov 7 12:27:29 2012 -0600
smm: Update rev 0x30101 SMM revision save state
According to both Haswell and the SandyBridge/Ivybridge BWGs the save state area actually starts at 0x7c00 offset from 0x8000. Update the em64t101_smm_state_save_area_t structure and introduce a define for the offset.
Note: I have no idea what eptp is. It's just listed in the haswell BWG. The offsets should not be changed.
Change-Id: I38d1d1469e30628a83f10b188ab2fe53d5a50e5a Signed-off-by: Aaron Durbin adurbin@chromium.org Reviewed-on: http://review.coreboot.org/2515 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Ronald G. Minnich rminnich@gmail.com
Build-Tested: build bot (Jenkins) at Tue Feb 26 01:48:12 2013, giving +1 Reviewed-By: Ronald G. Minnich rminnich@gmail.com at Wed Feb 27 03:03:50 2013, giving +2 See http://review.coreboot.org/2515 for details.
-gerrit