Fun ugliness

[Myles Watson]

Does this make sense?

Since CAR isn't backed by actual RAM, if I do a ram test of any reasonable
size it evicts my stack and I can't continue.

So, when I'm "comfortable" with my RAM setup I have to go blind.  Is there a
way around that?  Anything I can think of would be very implementation
specific.

Thanks,
Myles

[Carl-Daniel Hailfinger]

On 24.06.2009 23:46, Myles Watson wrote:
> Does this make sense?
>
> Since CAR isn't backed by actual RAM, if I do a ram test of any reasonable
> size it evicts my stack and I can't continue.

Correct if the RAM you're testing is marked as cacheable. If that RAM
area is not marked as cacheable, there should be no problem. Then again,
cache aliasing may ruin this approach.
> So, when I'm "comfortable" with my RAM setup I have to go blind.  Is there a
> way around that?

Sure. Most SSE and later multimedia instructions use uncached accesses.
The AMD K8 BKDG explicitly mentions that you have to use cache-avoiding
instructions for RAM accesses during CAR. I think one of the examples is
MOVNTI (SSE2).

Regards,
Carl-Daniel

[Myles Watson]

> On 24.06.2009 23:46, Myles Watson wrote:
> > Does this make sense?
> >
> > Since CAR isn't backed by actual RAM, if I do a ram test of any
>
> reasonable
> > size it evicts my stack and I can't continue.
>
> Correct if the RAM you're testing is marked as cacheable. If that RAM
> area is not marked as cacheable, there should be no problem. Then again,
> cache aliasing may ruin this approach.

Yes.  Because I was accessing my FPGA I marked it as cacheable to change the
size of the reads.  I didn't think about the side effects enough.  I'll just
have to be careful.

movnti is the right idea for writes.

Thanks,
Myles