Hi,
in january, I sent a mail to report that I could not flash a Pm49FL002 chip on my A7M266-D motherboard using flashrom. Since then, I tried to figure out what was going wrong. I discovered that the problem comes from the TBL# and WP# pins of the flash chip that have to be set high to disable write protection respectively on the boot block and on the rest of the memory (I guess all of you already knew that, but I'm a noob, so it's new for me). Flashing the chip using AFLASH, I checked with a voltmeter that the voltage at the WP# pin is jumping from 0V to 3.3V and then 0V again, every time a block is written. Doing the same test while flashing with flashrom, the voltmeter reads 0V all the time. So it seems clear that flashrom is not doing what is needed to set the TBL# and WP# pins high when a write is done. Now, I have no idea how to set these pins high. Are these pins controlled by the AMD-768 chipset ? I searched the documentation provided by AMD but found no mention about these pins. All I found is that a bit in a register (0x40) has to be set to enable LPC ROM write, but flashrom is already doing that, so I suppose it's unrelated to the TBL#/WP# write protection. Can someone tell me how the voltage of pins TBL#/WP# is controlled ?
Pierre
Hi Pierre,
On 16.05.2009 16:47, Pierre Bogossian wrote:
in january, I sent a mail to report that I could not flash a Pm49FL002 chip on my A7M266-D motherboard using flashrom. Since then, I tried to figure out what was going wrong. I discovered that the problem comes from the TBL# and WP# pins of the flash chip that have to be set high to disable write protection respectively on the boot block and on the rest of the memory (I guess all of you already knew that, but I'm a noob, so it's new for me). Flashing the chip using AFLASH, I checked with a voltmeter that the voltage at the WP# pin is jumping from 0V to 3.3V and then 0V again, every time a block is written. Doing the same test while flashing with flashrom, the voltmeter reads 0V all the time. So it seems clear that flashrom is not doing what is needed to set the TBL# and WP# pins high when a write is done.
You hit the problem spot on.
Now, I have no idea how to set these pins high. Are these pins controlled by the AMD-768 chipset ? I searched the documentation provided by AMD but found no mention about these pins. All I found is that a bit in a register (0x40) has to be set to enable LPC ROM write, but flashrom is already doing that, so I suppose it's unrelated to the TBL#/WP# write protection. Can someone tell me how the voltage of pins TBL#/WP# is controlled ?
Let me explain. No chipset has dedicated pins to control TBL#/WP# of a flash chip. That means you will never find any chipset doc mentioning TBL# or WP#. Instead, a GPIO of the chipset or of the SuperI/O is connected to TBL# and WP# each. Unfortunately, every board manufacturer uses another GPIO for this task, so you have to trace the TBL#/WP# lines to the chipset/superio, then look up which GPIO it is. Once that is done, you can tell us the number of the GPIO and which chip it is connected to. Then we can trigger it in flashrom (if we have docs on how to change GPIOs on that chipset/superio).
If that does not work, some people on this list are also capable to extract the necessary info from some BIOS images. It is a very time-consuming task, though.
Regards, Carl-Daniel
Carl-Daniel Hailfinger wrote:
No chipset has dedicated pins to control TBL#/WP# of a flash chip.
I think some do, but it's definately not the norm. Or maybe that was the chipset write regions.
extract the necessary info from some BIOS images
Another option is to run the vendor flasher and enable logging. Sometimes that will reveal the neccessary details.
Uniflash logging can also be helpful.
//Peter
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Carl-Daniel Hailfinger -
Peter Stuge -
Pierre Bogossian