Doing my part to keep the list traffic up, here are patches to fix the licenses on the LX northbridge, 5536 southbridge, and norwich mainboard directory. These are followed up with patches to clean the whitespace and indentation on all LX directories. This should bring everything up to code (no pun intended).
Jordan -- Jordan Crouse Senior Linux Engineer Advanced Micro Devices, Inc. <www.amd.com/embeddedprocessors>
Add missing licenses to several of the files.
Signed-off-by: Jordan Crouse jordan.crouse@amd.com
Index: LinuxBIOSv2/src/mainboard/amd/norwich/auto.c =================================================================== --- LinuxBIOSv2.orig/src/mainboard/amd/norwich/auto.c 2007-05-07 09:45:42.000000000 -0600 +++ LinuxBIOSv2/src/mainboard/amd/norwich/auto.c 2007-05-07 14:28:38.000000000 -0600 @@ -1,8 +1,22 @@ /* -* -* Copyright (C) 2007 Advanced Micro Devices -* -*/ + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */
#define ASSEMBLY 1
Index: LinuxBIOSv2/src/mainboard/amd/norwich/cache_as_ram_auto.c =================================================================== --- LinuxBIOSv2.orig/src/mainboard/amd/norwich/cache_as_ram_auto.c 2007-05-07 09:45:42.000000000 -0600 +++ LinuxBIOSv2/src/mainboard/amd/norwich/cache_as_ram_auto.c 2007-05-07 14:28:38.000000000 -0600 @@ -1,8 +1,22 @@ /* -* -* Copyright (C) 2007 Advanced Micro Devices -* -*/ + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */
#define ASSEMBLY 1
Index: LinuxBIOSv2/src/mainboard/amd/norwich/chip.h =================================================================== --- LinuxBIOSv2.orig/src/mainboard/amd/norwich/chip.h 2007-05-07 09:45:42.000000000 -0600 +++ LinuxBIOSv2/src/mainboard/amd/norwich/chip.h 2007-05-07 14:28:38.000000000 -0600 @@ -1,9 +1,22 @@ /* -* -* Copyright (C) 2007 Advanced Micro Devices -* - -*/ + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */
extern struct chip_operations mainboard_amd_norwich_ops;
-- Jordan Crouse Senior Linux Engineer Advanced Micro Devices, Inc. <www.amd.com/embeddedprocessors>
On Mon, May 07, 2007 at 02:38:43PM -0600, jordan.crouse@amd.com wrote:
Add missing licenses to several of the files.
Signed-off-by: Jordan Crouse jordan.crouse@amd.com
r2639.
Uwe.
Add missing licenses to several of the files.
Signed-off-by: Jordan Crouse jordan.crouse@amd.com
Index: LinuxBIOSv2/src/northbridge/amd/lx/chip.h =================================================================== --- LinuxBIOSv2.orig/src/northbridge/amd/lx/chip.h 2007-05-04 13:31:50.000000000 -0600 +++ LinuxBIOSv2/src/northbridge/amd/lx/chip.h 2007-05-04 13:33:16.000000000 -0600 @@ -1,8 +1,22 @@ /* -* -* Copyright (C) 2007 Advanced Micro Devices -* -*/ + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */
struct northbridge_amd_lx_config { Index: LinuxBIOSv2/src/northbridge/amd/lx/grphinit.c =================================================================== --- LinuxBIOSv2.orig/src/northbridge/amd/lx/grphinit.c 2007-05-04 13:31:50.000000000 -0600 +++ LinuxBIOSv2/src/northbridge/amd/lx/grphinit.c 2007-05-04 13:33:35.000000000 -0600 @@ -1,8 +1,22 @@ /* -* -* Copyright (C) 2007 Advanced Micro Devices -* -*/ + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */
#include <arch/io.h> #include <stdint.h> Index: LinuxBIOSv2/src/northbridge/amd/lx/northbridge.c =================================================================== --- LinuxBIOSv2.orig/src/northbridge/amd/lx/northbridge.c 2007-05-04 13:31:50.000000000 -0600 +++ LinuxBIOSv2/src/northbridge/amd/lx/northbridge.c 2007-05-04 13:38:26.000000000 -0600 @@ -1,8 +1,22 @@ /* -* -* Copyright (C) 2007 Advanced Micro Devices -* -*/ + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */
#include <console/console.h> #include <arch/io.h> Index: LinuxBIOSv2/src/northbridge/amd/lx/northbridge.h =================================================================== --- LinuxBIOSv2.orig/src/northbridge/amd/lx/northbridge.h 2007-05-04 13:31:51.000000000 -0600 +++ LinuxBIOSv2/src/northbridge/amd/lx/northbridge.h 2007-05-04 13:42:09.000000000 -0600 @@ -1,3 +1,23 @@ +/* +* This file is part of the LinuxBIOS project. +* +* Copyright (C) 2007 Advanced Micro Devices +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include <cpu/amd/lxdef.h> #ifndef NORTHBRIDGE_AMD_LX_H #define NORTHBRIDGE_AMD_LX_H
Index: LinuxBIOSv2/src/northbridge/amd/lx/northbridgeinit.c =================================================================== --- LinuxBIOSv2.orig/src/northbridge/amd/lx/northbridgeinit.c 2007-05-04 13:31:51.000000000 -0600 +++ LinuxBIOSv2/src/northbridge/amd/lx/northbridgeinit.c 2007-05-04 13:38:40.000000000 -0600 @@ -1,8 +1,22 @@ /* -* -* Copyright (C) 2007 Advanced Micro Devices -* -*/ + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */
#include <console/console.h> #include <arch/io.h> Index: LinuxBIOSv2/src/northbridge/amd/lx/pll_reset.c =================================================================== --- LinuxBIOSv2.orig/src/northbridge/amd/lx/pll_reset.c 2007-05-04 13:31:51.000000000 -0600 +++ LinuxBIOSv2/src/northbridge/amd/lx/pll_reset.c 2007-05-04 13:41:25.000000000 -0600 @@ -1,8 +1,22 @@ /* -* -* Copyright (C) 2007 Advanced Micro Devices -* -*/ + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */
static void pll_reset(char manualconf) { Index: LinuxBIOSv2/src/northbridge/amd/lx/raminit.h =================================================================== --- LinuxBIOSv2.orig/src/northbridge/amd/lx/raminit.h 2007-05-04 13:31:51.000000000 -0600 +++ LinuxBIOSv2/src/northbridge/amd/lx/raminit.h 2007-05-04 13:41:43.000000000 -0600 @@ -1,3 +1,23 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #ifndef RAMINIT_H #define RAMINIT_H
-- Jordan Crouse Senior Linux Engineer Advanced Micro Devices, Inc. <www.amd.com/embeddedprocessors>
Add missing licenses to several of the files.
Signed-off-by: Jordan Crouse jordan.crouse@amd.com
Index: LinuxBIOSv2/src/southbridge/amd/cs5536/chip.h =================================================================== --- LinuxBIOSv2.orig/src/southbridge/amd/cs5536/chip.h 2007-05-04 13:45:49.000000000 -0600 +++ LinuxBIOSv2/src/southbridge/amd/cs5536/chip.h 2007-05-04 13:46:38.000000000 -0600 @@ -1,8 +1,22 @@ /* -* -* Copyright (C) 2007 Advanced Micro Devices -* -*/ + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */
#ifndef _SOUTHBRIDGE_AMD_CS5536 #define _SOUTHBRIDGE_AMD_CS5536 Index: LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_smbus2.h =================================================================== --- LinuxBIOSv2.orig/src/southbridge/amd/cs5536/cs5536_smbus2.h 2007-05-04 13:45:49.000000000 -0600 +++ LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_smbus2.h 2007-05-04 13:47:10.000000000 -0600 @@ -1,4 +1,23 @@ -//#include <device/smbus_def.h> +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #define SMBUS_ERROR -1 #define SMBUS_WAIT_UNTIL_READY_TIMEOUT -2 #define SMBUS_WAIT_UNTIL_DONE_TIMEOUT -3
-- Jordan Crouse Senior Linux Engineer Advanced Micro Devices, Inc. <www.amd.com/embeddedprocessors>
Fix the indent and whitespace to match LinuxBIOS standards
Signed-off-by: Jordan Crouse jordan.crouse@amd.com
Index: LinuxBIOSv2/src/mainboard/amd/norwich/auto.c =================================================================== --- LinuxBIOSv2.orig/src/mainboard/amd/norwich/auto.c 2007-05-07 14:28:38.000000000 -0600 +++ LinuxBIOSv2/src/mainboard/amd/norwich/auto.c 2007-05-07 14:29:07.000000000 -0600 @@ -42,11 +42,11 @@
static inline int spd_read_byte(unsigned device, unsigned address) { - return smbus_read_byte(device, address); + return smbus_read_byte(device, address); }
#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x00001490 /* manual settings for the PLL */ +#define PLLMSRhi 0x00001490 /* manual settings for the PLL */ #define PLLMSRlo 0x02000030 #define DIMM0 0xA0 #define DIMM1 0xA2 @@ -60,7 +60,7 @@ static void msr_init(void) { /* Setup access to the MC for low memory. Note MC not setup yet. */ - __builtin_wrmsr(CPU_RCONF_DEFAULT, 0x10f3bf00, 0x24fffc02); + __builtin_wrmsr(CPU_RCONF_DEFAULT, 0x10f3bf00, 0x24fffc02);
__builtin_wrmsr(MSR_GLIU0 + 0x20, 0xfff80, 0x20000000); __builtin_wrmsr(MSR_GLIU0 + 0x21, 0x80fffe0, 0x20000000); @@ -76,8 +76,8 @@
static void main(unsigned long bist) { - static const struct mem_controller memctrl [] = { - {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}} + static const struct mem_controller memctrl[] = { + {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} };
SystemPreInit(); @@ -89,8 +89,8 @@ * it is counting on some early MSR setup * for cs5536 */ - /* cs5536_disable_internal_uart disable them for now, set them up later...*/ - cs5536_setup_onchipuart(); /* if debug. real setup done in chipset init via config.lb */ + /* cs5536_disable_internal_uart disable them for now, set them up later... */ + cs5536_setup_onchipuart(); /* if debug. real setup done in chipset init via config.lb */ mb_gpio_init(); uart_init(); console_init(); Index: LinuxBIOSv2/src/mainboard/amd/norwich/cache_as_ram_auto.c =================================================================== --- LinuxBIOSv2.orig/src/mainboard/amd/norwich/cache_as_ram_auto.c 2007-05-07 14:28:38.000000000 -0600 +++ LinuxBIOSv2/src/mainboard/amd/norwich/cache_as_ram_auto.c 2007-05-07 14:29:07.000000000 -0600 @@ -42,11 +42,11 @@
static inline int spd_read_byte(unsigned device, unsigned address) { - return smbus_read_byte(device, address); + return smbus_read_byte(device, address); }
#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x00001490 /* manual settings for the PLL */ +#define PLLMSRhi 0x00001490 /* manual settings for the PLL */ #define PLLMSRlo 0x02000030 #define DIMM0 0xA0 #define DIMM1 0xA2 @@ -62,11 +62,11 @@ msr_t msr; /* Setup access to the cache for under 1MB. */ msr.hi = 0x24fffc02; - msr.lo = 0x1000A000; /* 0-A0000 write back */ + msr.lo = 0x1000A000; /* 0-A0000 write back */ wrmsr(CPU_RCONF_DEFAULT, msr);
- msr.hi = 0x0; /* write back */ - msr.lo = 0x0; + msr.hi = 0x0; /* write back */ + msr.lo = 0x0; wrmsr(CPU_RCONF_A0_BF, msr); wrmsr(CPU_RCONF_C0_DF, msr); wrmsr(CPU_RCONF_E0_FF, msr); @@ -81,11 +81,11 @@ wrmsr(MSR_GLIU0 + 0x21, msr);
msr.hi = 0x20000000; - msr.lo = 0xfff80; + msr.lo = 0xfff80; wrmsr(MSR_GLIU1 + 0x20, msr);
msr.hi = 0x20000000; - msr.lo = 0x80fffe0; + msr.lo = 0x80fffe0; wrmsr(MSR_GLIU1 + 0x21, msr);
} @@ -99,8 +99,8 @@ { POST_CODE(0x01);
- static const struct mem_controller memctrl [] = { - {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}} + static const struct mem_controller memctrl[] = { + {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} };
SystemPreInit(); @@ -112,8 +112,8 @@ * it is counting on some early MSR setup * for cs5536 */ - /* cs5536_disable_internal_uart disable them for now, set them up later...*/ - cs5536_setup_onchipuart(); /* if debug. real setup done in chipset init via config.lb */ + /* cs5536_disable_internal_uart disable them for now, set them up later... */ + cs5536_setup_onchipuart(); /* if debug. real setup done in chipset init via config.lb */ mb_gpio_init(); uart_init(); console_init(); @@ -125,7 +125,7 @@ sdram_initialize(1, memctrl);
/* Check all of memory */ - /*ram_check(0x00000000, 640*1024);*/ + /*ram_check(0x00000000, 640*1024); */
/* Memory is setup. Return to cache_as_ram.inc and continue to boot */ return; Index: LinuxBIOSv2/src/mainboard/amd/norwich/failover.c =================================================================== --- LinuxBIOSv2.orig/src/mainboard/amd/norwich/failover.c 2007-05-07 09:45:41.000000000 -0600 +++ LinuxBIOSv2/src/mainboard/amd/norwich/failover.c 2007-05-07 14:29:07.000000000 -0600 @@ -12,23 +12,20 @@ /* This is the primary cpu how should I boot? */ if (do_normal_boot()) { goto normal_image; - } - else { + } else { goto fallback_image; } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: + normal_image: + asm volatile ("jmp __normal_image": /* outputs */ + :"a" (bist) /* inputs */ + : /* clobbers */ + ); + cpu_reset: + asm volatile ("jmp __cpu_reset": /* outputs */ + :"a" (bist) /* inputs */ + : /* clobbers */ + ); + fallback_image: #endif return bist; } Index: LinuxBIOSv2/src/mainboard/amd/norwich/irq_tables.c =================================================================== --- LinuxBIOSv2.orig/src/mainboard/amd/norwich/irq_tables.c 2007-05-07 09:45:41.000000000 -0600 +++ LinuxBIOSv2/src/mainboard/amd/norwich/irq_tables.c 2007-05-07 14:29:07.000000000 -0600 @@ -30,43 +30,43 @@ #define PIRQD 10
/* Map */ -#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ -#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ -#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ -#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */ +#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ +#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ +#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ +#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
/* Link */ -#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */ -#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */ -#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ -#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */ +#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */ +#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */ +#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ +#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*IRQ_SLOT_COUNT, /* there can be total 6 devices on the bus */ + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * IRQ_SLOT_COUNT, /* there can be total 6 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x0F<<3)|0x0, /* Where the interrupt router lies (dev) */ + (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */ 0x100B, /* Vendor */ 0x002B, /* Device */ - 0, /* Crap (miniport) */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + 0, /* Crap (miniport) */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ + 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { - /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */ - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x01<<3)|0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ - {0x00,(0x0F<<3)|0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ - {0x00,(0x0D<<3)|0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x1, 0x0}, /* slot1 */ - {0x00,(0x0E<<3)|0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x2, 0x0}, /* slot2 */ - {0x00,(0x0B<<3)|0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x3, 0x0}, /* slot3 */ - {0x00,(0x0C<<3)|0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0}, /* slot4 */ - } + /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ + {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ + {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x1, 0x0}, /* slot1 */ + {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x2, 0x0}, /* slot2 */ + {0x00, (0x0B << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x3, 0x0}, /* slot3 */ + {0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0}, /* slot4 */ + } };
- -unsigned long write_pirq_routing_table(unsigned long addr){ +unsigned long write_pirq_routing_table(unsigned long addr) +{ int i, j, k, num_entries; unsigned char pirq[4]; uint16_t chipset_irq_map; @@ -78,24 +78,26 @@ /* Set up chipset IRQ steering */ pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C; chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA); - printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr, chipset_irq_map); + printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr, + chipset_irq_map); outl(pciAddr & ~3, 0xCF8); outl(chipset_irq_map, 0xCFC);
pirq_tbl = (struct irq_routing_table *)(addr); - num_entries = (pirq_tbl->size - 32)/16; + num_entries = (pirq_tbl->size - 32) / 16;
/* Set PCI IRQs */ - for (i=0; i < num_entries; i++){ - printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i, pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot); - for (j = 0; j < 4; j++){ - printk_debug("INT: %c bitmap: %x ", 'A'+j, pirq_tbl->slots[i].irq[j].bitmap); - for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++); /* finds lsb in bitmap to IRQ# */ + for (i = 0; i < num_entries; i++) { + printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i, + pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot); + for (j = 0; j < 4; j++) { + printk_debug("INT: %c bitmap: %x ", 'A' + j, + pirq_tbl->slots[i].irq[j].bitmap); + for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++) ; /* finds lsb in bitmap to IRQ# */ pirq[j] = k; printk_debug("PIRQ: %d\n", k); } - pci_assign_irqs(pirq_tbl->slots[i].bus, - pirq_tbl->slots[i].devfn >> 3, pirq); /* bus, device, slots IRQs for {A,B,C,D} */ + pci_assign_irqs(pirq_tbl->slots[i].bus, pirq_tbl->slots[i].devfn >> 3, pirq); /* bus, device, slots IRQs for {A,B,C,D} */ }
/* put the PIR table in memory and checksum */ Index: LinuxBIOSv2/src/mainboard/amd/norwich/mainboard.c =================================================================== --- LinuxBIOSv2.orig/src/mainboard/amd/norwich/mainboard.c 2007-05-07 09:45:41.000000000 -0600 +++ LinuxBIOSv2/src/mainboard/amd/norwich/mainboard.c 2007-05-07 14:29:07.000000000 -0600 @@ -27,143 +27,177 @@ #include "chip.h"
/* Print the platform configuration - do before PCI init or it will not work right */ -void print_conf(void) { +void print_conf(void) +{ #if DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR int i; unsigned long iol; msr_t msr;
- int cpu_msr_defs[] = { CPU_BC_L2_CONF, CPU_IM_CONFIG, - CPU_DM_CONFIG0, CPU_RCONF_DEFAULT, - CPU_RCONF_BYPASS, CPU_RCONF_A0_BF, CPU_RCONF_C0_DF, CPU_RCONF_E0_FF, - CPU_RCONF_SMM, CPU_RCONF_DMM, GLCP_DELAY_CONTROLS, GL_END - }; - - int gliu0_msr_defs[] = {MSR_GLIU0_BASE1, MSR_GLIU0_BASE2, MSR_GLIU0_BASE4, MSR_GLIU0_BASE5, MSR_GLIU0_BASE6, - GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, MSR_GLIU0_SYSMEM, - GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, GLIU0_P2D_RO_2, MSR_GLIU0_SHADOW, - GLIU0_IOD_BM_0, GLIU0_IOD_BM_1, GLIU0_IOD_BM_2, - GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2, GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5, - GLIU0_GLD_MSR_COH, GL_END - }; - - int gliu1_msr_defs[] = {MSR_GLIU1_BASE1, MSR_GLIU1_BASE2, MSR_GLIU1_BASE3, MSR_GLIU1_BASE4, MSR_GLIU1_BASE5, MSR_GLIU1_BASE6, - MSR_GLIU1_BASE7, MSR_GLIU1_BASE8, MSR_GLIU1_BASE9, MSR_GLIU1_BASE10, - GLIU1_P2D_R_0, GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3, MSR_GLIU1_SHADOW, - GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2, - GLIU1_IOD_SC_0, GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3, - GLIU1_GLD_MSR_COH, GL_END - }; - - int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3, CPU_RCONF4, - CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END - }; - - int cs5536_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, MDD_LEG_IO, MDD_PIN_OPT, - MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH, MDD_IRQM_PRIM, GL_END - }; - - int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF, GLPCI_C0_DF, GLPCI_E0_FF, - GLPCI_RC0, GLPCI_RC1, GLPCI_RC2, GLPCI_RC3, GLPCI_ExtMSR, GLPCI_SPARE, - GL_END - }; - - int dma_msr[] = { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2, MDD_DMA_SHAD3, MDD_DMA_SHAD4, - MDD_DMA_SHAD5, MDD_DMA_SHAD6, MDD_DMA_SHAD7, MDD_DMA_SHAD8, - MDD_DMA_SHAD9, GL_END - }; - + int cpu_msr_defs[] = { CPU_BC_L2_CONF, CPU_IM_CONFIG, + CPU_DM_CONFIG0, CPU_RCONF_DEFAULT, + CPU_RCONF_BYPASS, CPU_RCONF_A0_BF, CPU_RCONF_C0_DF, + CPU_RCONF_E0_FF, + CPU_RCONF_SMM, CPU_RCONF_DMM, GLCP_DELAY_CONTROLS, GL_END + }; + + int gliu0_msr_defs[] = + { MSR_GLIU0_BASE1, MSR_GLIU0_BASE2, MSR_GLIU0_BASE4, + MSR_GLIU0_BASE5, MSR_GLIU0_BASE6, + GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, MSR_GLIU0_SYSMEM, + GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, GLIU0_P2D_RO_2, + MSR_GLIU0_SHADOW, + GLIU0_IOD_BM_0, GLIU0_IOD_BM_1, GLIU0_IOD_BM_2, + GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2, GLIU0_IOD_SC_3, + GLIU0_IOD_SC_4, GLIU0_IOD_SC_5, + GLIU0_GLD_MSR_COH, GL_END + }; + + int gliu1_msr_defs[] = + { MSR_GLIU1_BASE1, MSR_GLIU1_BASE2, MSR_GLIU1_BASE3, + MSR_GLIU1_BASE4, MSR_GLIU1_BASE5, MSR_GLIU1_BASE6, + MSR_GLIU1_BASE7, MSR_GLIU1_BASE8, MSR_GLIU1_BASE9, + MSR_GLIU1_BASE10, + GLIU1_P2D_R_0, GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3, + MSR_GLIU1_SHADOW, + GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2, + GLIU1_IOD_SC_0, GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3, + GLIU1_GLD_MSR_COH, GL_END + }; + + int rconf_msr[] = + { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3, CPU_RCONF4, + CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END + }; + + int cs5536_msr[] = + { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, MDD_LEG_IO, + MDD_PIN_OPT, + MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH, MDD_IRQM_PRIM, GL_END + }; + + int pci_msr[] = + { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF, GLPCI_C0_DF, + GLPCI_E0_FF, + GLPCI_RC0, GLPCI_RC1, GLPCI_RC2, GLPCI_RC3, GLPCI_ExtMSR, + GLPCI_SPARE, + GL_END + }; + + int dma_msr[] = + { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2, MDD_DMA_SHAD3, + MDD_DMA_SHAD4, + MDD_DMA_SHAD5, MDD_DMA_SHAD6, MDD_DMA_SHAD7, MDD_DMA_SHAD8, + MDD_DMA_SHAD9, GL_END + };
printk_debug("---------- CPU ------------\n");
- for(i = 0; cpu_msr_defs[i] != GL_END; i++) { + for (i = 0; cpu_msr_defs[i] != GL_END; i++) { msr = rdmsr(cpu_msr_defs[i]); - printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cpu_msr_defs[i], msr.hi, msr.lo); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", + cpu_msr_defs[i], msr.hi, msr.lo); }
printk_debug("---------- GLIU 0 ------------\n");
- for(i = 0; gliu0_msr_defs[i] != GL_END; i++) { + for (i = 0; gliu0_msr_defs[i] != GL_END; i++) { msr = rdmsr(gliu0_msr_defs[i]); - printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", gliu0_msr_defs[i], msr.hi, msr.lo); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", + gliu0_msr_defs[i], msr.hi, msr.lo); }
printk_debug("---------- GLIU 1 ------------\n");
- for(i = 0; gliu1_msr_defs[i] != GL_END; i++) { + for (i = 0; gliu1_msr_defs[i] != GL_END; i++) { msr = rdmsr(gliu1_msr_defs[i]); - printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", gliu1_msr_defs[i], msr.hi, msr.lo); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", + gliu1_msr_defs[i], msr.hi, msr.lo); }
printk_debug("---------- RCONF ------------\n");
- for(i = 0; rconf_msr[i] != GL_END; i++) { + for (i = 0; rconf_msr[i] != GL_END; i++) { msr = rdmsr(rconf_msr[i]); - printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i], msr.hi, msr.lo); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i], + msr.hi, msr.lo); }
printk_debug("---------- VARIA ------------\n"); msr = rdmsr(0x51300010); - printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi, msr.lo); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi, + msr.lo);
msr = rdmsr(0x51400015); - printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi, msr.lo); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi, + msr.lo);
printk_debug("---------- DIVIL IRQ ------------\n"); msr = rdmsr(MDD_IRQM_YLOW); - printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi, msr.lo); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi, + msr.lo); msr = rdmsr(MDD_IRQM_YHIGH); - printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH, msr.hi, msr.lo); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH, + msr.hi, msr.lo); msr = rdmsr(MDD_IRQM_ZLOW); - printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi, msr.lo); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi, + msr.lo); msr = rdmsr(MDD_IRQM_ZHIGH); - printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH, msr.hi, msr.lo); - + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH, + msr.hi, msr.lo);
printk_debug("---------- PCI ------------\n");
- for(i = 0; pci_msr[i] != GL_END; i++) { + for (i = 0; pci_msr[i] != GL_END; i++) { msr = rdmsr(pci_msr[i]); - printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i], msr.hi, msr.lo); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i], + msr.hi, msr.lo); }
printk_debug("---------- LPC/UART DMA ------------\n");
- for(i = 0; dma_msr[i] != GL_END; i++) { + for (i = 0; dma_msr[i] != GL_END; i++) { msr = rdmsr(dma_msr[i]); - printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i], msr.hi, msr.lo); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i], + msr.hi, msr.lo); }
printk_debug("---------- CS5536 ------------\n");
- for(i = 0; cs5536_msr[i] != GL_END; i++) { + for (i = 0; cs5536_msr[i] != GL_END; i++) { msr = rdmsr(cs5536_msr[i]); - printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i], msr.hi, msr.lo); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i], + msr.hi, msr.lo); }
iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE); - printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol); + printk_debug("IOR 0x%08X is now 0x%08X\n", + GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol); iol = inl(GPIOL_EVENTS_ENABLE); - printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol); + printk_debug("IOR 0x%08X is now 0x%08X\n", + GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol); iol = inl(GPIOL_INPUT_INVERT_ENABLE); - printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol); + printk_debug("IOR 0x%08X is now 0x%08X\n", + GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol); iol = inl(GPIO_MAPPER_X); - printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIO_MAPPER_X, iol); -#endif //DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR + printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIO_MAPPER_X, + iol); +#endif //DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR }
-static void init(struct device *dev) { +static void init(struct device *dev) +{ printk_debug("Norwich ENTER %s\n", __FUNCTION__); printk_debug("Norwich EXIT %s\n", __FUNCTION__); }
static void enable_dev(struct device *dev) { - dev->ops->init = init; + dev->ops->init = init; }
struct chip_operations mainboard_amd_norwich_ops = { CHIP_NAME("AMD Norwich Mainboard") - .enable_dev = enable_dev, + .enable_dev = enable_dev,
};
-- Jordan Crouse Senior Linux Engineer Advanced Micro Devices, Inc. <www.amd.com/embeddedprocessors>
Fix the indent and whitespace to match LinuxBIOS standards
Signed-off-by: Jordan Crouse jordan.crouse@amd.com
Index: LinuxBIOSv2/src/northbridge/amd/lx/chip.h =================================================================== --- LinuxBIOSv2.orig/src/northbridge/amd/lx/chip.h 2007-05-04 13:44:14.000000000 -0600 +++ LinuxBIOSv2/src/northbridge/amd/lx/chip.h 2007-05-04 13:44:16.000000000 -0600 @@ -18,8 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-struct northbridge_amd_lx_config -{ +struct northbridge_amd_lx_config {
};
Index: LinuxBIOSv2/src/northbridge/amd/lx/grphinit.c =================================================================== --- LinuxBIOSv2.orig/src/northbridge/amd/lx/grphinit.c 2007-05-04 13:44:14.000000000 -0600 +++ LinuxBIOSv2/src/northbridge/amd/lx/grphinit.c 2007-05-04 13:44:16.000000000 -0600 @@ -23,42 +23,41 @@ #include <cpu/amd/vr.h> #include <console/console.h>
- /* - * This function mirrors the Graphics_Init routine in GeodeROM. - */ + * This function mirrors the Graphics_Init routine in GeodeROM. + */ void graphics_init(void) { uint16_t wClassIndex, wData, res; - + /* SoftVG initialization */ printk_debug("Graphics init...\n");
/* Call SoftVG with the main configuration parameters. */ /* NOTE: SoftVG expects the memory size to be given in 2MB blocks */ - - wClassIndex = (VRC_VG << 8) + VG_CONFIG; - + + wClassIndex = (VRC_VG << 8) + VG_CONFIG; + /* - * Graphics Driver Enabled (13) 0, NO (lets BIOS controls the GP) - * External Monochrome Card Support(12) 0, NO - * Controller Priority Select(11) 1, Primary - * Display Select(10:8) 0x0, CRT - * Graphics Memory Size(7:1) CONFIG_VIDEO_MB >> 1, - * defined in mainboard/../Options.lb - * PLL Reference Clock Bypass(0) 0, Default + * Graphics Driver Enabled (13) 0, NO (lets BIOS controls the GP) + * External Monochrome Card Support(12) 0, NO + * Controller Priority Select(11) 1, Primary + * Display Select(10:8) 0x0, CRT + * Graphics Memory Size(7:1) CONFIG_VIDEO_MB >> 1, + * defined in mainboard/../Options.lb + * PLL Reference Clock Bypass(0) 0, Default */
/* Video RAM has to be given in 2MB chunks * the value is read @ 7:1 (value in 7:0 looks like /2) * so we can add the real value in megabytes */ - - wData = VG_CFG_DRIVER | VG_CFG_PRIORITY | VG_CFG_DSCRT | (CONFIG_VIDEO_MB & VG_MEM_MASK); + + wData = + VG_CFG_DRIVER | VG_CFG_PRIORITY | VG_CFG_DSCRT | (CONFIG_VIDEO_MB & + VG_MEM_MASK); vrWrite(wClassIndex, wData); - + res = vrRead(wClassIndex); printk_debug("VRC_VG value: 0x%04x\n", res); } - - Index: LinuxBIOSv2/src/northbridge/amd/lx/northbridge.c =================================================================== --- LinuxBIOSv2.orig/src/northbridge/amd/lx/northbridge.c 2007-05-04 13:44:14.000000000 -0600 +++ LinuxBIOSv2/src/northbridge/amd/lx/northbridge.c 2007-05-04 13:44:16.000000000 -0600 @@ -35,12 +35,11 @@ #include "chip.h" #include "northbridge.h"
- /* here is programming for the various MSRs.*/ #define IM_QWAIT 0x100000
-#define DMCF_WRITE_SERIALIZE_REQUEST (2<<12) /* 2 outstanding */ /* in high */ -#define DMCF_SERIAL_LOAD_MISSES (2) /* enabled */ +#define DMCF_WRITE_SERIALIZE_REQUEST (2<<12) /* 2 outstanding */ /* in high */ +#define DMCF_SERIAL_LOAD_MISSES (2) /* enabled */
/* these are the 8-bit attributes for controlling RCONF registers */ #define CACHE_DISABLE (1<<0) @@ -87,33 +86,36 @@ struct msr_defaults { int msr_no; msr_t msr; -} msr_defaults [] = { - {0x1700, {.hi = 0, .lo = IM_QWAIT}}, - {0x1800, {.hi = DMCF_WRITE_SERIALIZE_REQUEST, .lo = DMCF_SERIAL_LOAD_MISSES}}, - /* 1808 will be done down below, so we have to do 180a->1817 (well, 1813 really) */ - /* for 180a, for now, we assume VSM will configure it */ - /* 180b is left at reset value,a0000-bffff is non-cacheable */ - /* 180c, c0000-dffff is set to write serialize and non-cachable */ - /* oops, 180c will be set by cpu bug handling in cpubug.c */ - //{0x180c, {.hi = MSR_WS_CD_DEFAULT, .lo = MSR_WS_CD_DEFAULT}}, - /* 180d is left at default, e0000-fffff is non-cached */ - - /* we will assume 180e, the ssm region configuration, is left at default or set by VSM */ - /* we will not set 0x180f, the DMM,yet */ - //{0x1810, {.hi=0xee7ff000, .lo=RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}}, - //{0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}}, - //{0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}}, - //{0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}}, - /* now for GLPCI routing */ - /* GLIU0 */ - P2D_BM(MSR_GLIU0_BASE1, 0x1, 0x0, 0x0, 0xfff80), - P2D_BM(MSR_GLIU0_BASE2, 0x1, 0x0, 0x80000, 0xfffe0), - P2D_SC(MSR_GLIU0_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000), - /* GLIU1 */ - P2D_BM(MSR_GLIU1_BASE1, 0x1, 0x0, 0x0, 0xfff80), - P2D_BM(MSR_GLIU1_BASE2, 0x1, 0x0, 0x80000, 0xfffe0), - P2D_SC(MSR_GLIU1_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000), - {0} +} msr_defaults[] = { + { + 0x1700, { + .hi = 0,.lo = IM_QWAIT}}, { + 0x1800, { + .hi = DMCF_WRITE_SERIALIZE_REQUEST,.lo = + DMCF_SERIAL_LOAD_MISSES}}, + /* 1808 will be done down below, so we have to do 180a->1817 (well, 1813 really) */ + /* for 180a, for now, we assume VSM will configure it */ + /* 180b is left at reset value,a0000-bffff is non-cacheable */ + /* 180c, c0000-dffff is set to write serialize and non-cachable */ + /* oops, 180c will be set by cpu bug handling in cpubug.c */ + //{0x180c, {.hi = MSR_WS_CD_DEFAULT, .lo = MSR_WS_CD_DEFAULT}}, + /* 180d is left at default, e0000-fffff is non-cached */ + /* we will assume 180e, the ssm region configuration, is left at default or set by VSM */ + /* we will not set 0x180f, the DMM,yet */ + //{0x1810, {.hi=0xee7ff000, .lo=RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}}, + //{0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}}, + //{0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}}, + //{0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}}, + /* now for GLPCI routing */ + /* GLIU0 */ + P2D_BM(MSR_GLIU0_BASE1, 0x1, 0x0, 0x0, 0xfff80), + P2D_BM(MSR_GLIU0_BASE2, 0x1, 0x0, 0x80000, 0xfffe0), + P2D_SC(MSR_GLIU0_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000), + /* GLIU1 */ + P2D_BM(MSR_GLIU1_BASE1, 0x1, 0x0, 0x0, 0xfff80), + P2D_BM(MSR_GLIU1_BASE2, 0x1, 0x0, 0x80000, 0xfffe0), + P2D_SC(MSR_GLIU1_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000), { + 0} };
/* todo: add a resource record. We don't do this here because this may be called when @@ -131,14 +133,14 @@ /* dimm 0 */ dimm = msr.hi; /* installed? */ - if ((dimm & 7) != 7){ + if ((dimm & 7) != 7) { sizem = 4 << ((dimm >> 12) & 0x0F); }
- /* dimm 1*/ + /* dimm 1 */ dimm = msr.hi >> 16; /* installed? */ - if ((dimm & 7) != 7){ + if ((dimm & 7) != 7) { sizem += 4 << ((dimm >> 12) & 0x0F); }
@@ -146,27 +148,24 @@ return sizem; }
- - static void enable_shadow(device_t dev) { }
-static void northbridge_init(device_t dev) +static void northbridge_init(device_t dev) { //msr_t msr;
printk_spew(">> Entering northbridge.c: %s\n", __FUNCTION__); - + enable_shadow(dev); /* * Swiss cheese */ //msr = rdmsr(MSR_GLIU0_SHADOW); - + //msr.hi |= 0x3; //msr.lo |= 0x30000; -
//printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU0_SHADOW, msr.hi, msr.lo); //printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU1_SHADOW, msr.hi, msr.lo); @@ -180,19 +179,20 @@
last = &dev->resource[dev->resources];
- for(resource = &dev->resource[0]; resource < last; resource++) - { + for (resource = &dev->resource[0]; resource < last; resource++) {
// andrei: do not change the base address, it will make the VSA virtual registers unusable //pci_set_resource(dev, resource); // FIXME: static allocation may conflict with dynamic mappings! }
- for(link = 0; link < dev->links; link++) { + for (link = 0; link < dev->links; link++) { struct bus *bus; bus = &dev->link[link]; if (bus->children) { - printk_debug("my_dev_set_resources: assign_resources %d\n", bus); + printk_debug + ("my_dev_set_resources: assign_resources %d\n", + bus); assign_resources(bus); } } @@ -210,18 +210,18 @@ if (line) { pci_write_config8(dev, PCI_INTERRUPT_LINE, 0); } - + /* set the cache line size, so far 64 bytes is good for everyone */ pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2); }
static struct device_operations northbridge_operations = { - .read_resources = pci_dev_read_resources, - .set_resources = northbridge_set_resources, + .read_resources = pci_dev_read_resources, + .set_resources = northbridge_set_resources, .enable_resources = pci_dev_enable_resources, - .init = northbridge_init, - .enable = 0, - .ops_pci = 0, + .init = northbridge_init, + .enable = 0, + .ops_pci = 0, };
static struct pci_driver northbridge_driver __pci_driver = { @@ -230,35 +230,37 @@ .device = PCI_DEVICE_ID_AMD_LXBRIDGE, };
- static void pci_domain_read_resources(device_t dev) { - struct resource *resource; + struct resource *resource; printk_spew(">> Entering northbridge.c: %s\n", __FUNCTION__);
- /* Initialize the system wide io space constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0)); - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0)); - resource->limit = 0xffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + /* Initialize the system wide io space constraints */ + resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + resource->limit = 0xffffUL; + resource->flags = + IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + + /* Initialize the system wide memory resources constraints */ + resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + resource->limit = 0xffffffffULL; + resource->flags = + IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; }
static void ram_resource(device_t dev, unsigned long index, - unsigned long basek, unsigned long sizek) + unsigned long basek, unsigned long sizek) { - struct resource *resource; + struct resource *resource; + + if (!sizek) + return;
- if (!sizek) return; - - resource = new_resource(dev, index); - resource->base = ((resource_t)basek) << 10; - resource->size = ((resource_t)sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + resource = new_resource(dev, index); + resource->base = ((resource_t) basek) << 10; + resource->size = ((resource_t) sizek) << 10; + resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; }
static void pci_domain_set_resources(device_t dev) @@ -269,12 +271,11 @@ printk_spew(">> Entering northbridge.c: %s\n", __FUNCTION__);
mc_dev = dev->link[0].children; - if (mc_dev) - { + if (mc_dev) { /* Report the memory regions */ idx = 10; ram_resource(dev, idx++, 0, 640); - ram_resource(dev, idx++, 1024, (get_systop()- 0x100000)/1024 ); // Systop - 1 MB -> KB + ram_resource(dev, idx++, 1024, (get_systop() - 0x100000) / 1024); // Systop - 1 MB -> KB }
assign_resources(&dev->link[0]); @@ -295,8 +296,8 @@ printk_debug("Before VSA:\n"); // print_conf();
- do_vsmbios(); // do the magic stuff here, so prepare your tambourine ;) - + do_vsmbios(); // do the magic stuff here, so prepare your tambourine ;) + printk_debug("After VSA:\n"); // print_conf();
@@ -308,23 +309,23 @@ { printk_spew(">> Entering northbridge.c: %s\n", __FUNCTION__);
- max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); - return max; + max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); + return max; }
static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .enable_resources = enable_childrens_resources, - .scan_bus = pci_domain_scan_bus, - .enable = pci_domain_enable, -}; + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = enable_childrens_resources, + .scan_bus = pci_domain_scan_bus, + .enable = pci_domain_enable, +};
static void cpu_bus_init(device_t dev) { printk_spew(">> Entering northbridge.c: %s\n", __FUNCTION__);
- initialize_cpus(&dev->link[0]); + initialize_cpus(&dev->link[0]); }
static void cpu_bus_noop(device_t dev) @@ -332,26 +333,26 @@ }
static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_noop, - .set_resources = cpu_bus_noop, - .enable_resources = cpu_bus_noop, - .init = cpu_bus_init, - .scan_bus = 0, + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = 0, };
static void enable_dev(struct device *dev) { - printk_spew(">> Entering northbridge.c: %s with path %d\n", - __FUNCTION__, dev->path.type); + printk_spew(">> Entering northbridge.c: %s with path %d\n", + __FUNCTION__, dev->path.type);
- /* Set the operations if it is a special bus type */ + /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) dev->ops = &pci_domain_ops; else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) - dev->ops = &cpu_bus_ops; + dev->ops = &cpu_bus_ops; }
struct chip_operations northbridge_amd_lx_ops = { CHIP_NAME("AMD LX Northbridge") - .enable_dev = enable_dev, + .enable_dev = enable_dev, }; Index: LinuxBIOSv2/src/northbridge/amd/lx/northbridgeinit.c =================================================================== --- LinuxBIOSv2.orig/src/northbridge/amd/lx/northbridgeinit.c 2007-05-04 13:44:14.000000000 -0600 +++ LinuxBIOSv2/src/northbridge/amd/lx/northbridgeinit.c 2007-05-04 13:45:06.000000000 -0600 @@ -33,7 +33,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/cache.h>
- struct gliutable { unsigned long desc_name; unsigned short desc_type; @@ -41,85 +40,85 @@ };
struct gliutable gliu0table[] = { - {.desc_name=MSR_GLIU0_BASE1, .desc_type= BM,.hi= MSR_MC + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC*/ - {.desc_name=MSR_GLIU0_BASE2, .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc*/ - {.desc_name=MSR_GLIU0_SHADOW, .desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo*/ - {.desc_name=MSR_GLIU0_SYSMEM, .desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly.*/ - {.desc_name=MSR_GLIU0_SMM, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly.*/ - {.desc_name=GLIU0_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU}, - {.desc_name=GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0}, + {.desc_name = MSR_GLIU0_BASE1,.desc_type = BM,.hi = MSR_MC + 0x0,.lo = 0x0FFF80}, /* 0-7FFFF to MC */ + {.desc_name = MSR_GLIU0_BASE2,.desc_type = BM,.hi = MSR_MC + 0x0,.lo = (0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc */ + {.desc_name = MSR_GLIU0_SHADOW,.desc_type = SC_SHADOW,.hi = MSR_MC + 0x0,.lo = 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */ + {.desc_name = MSR_GLIU0_SYSMEM,.desc_type = R_SYSMEM,.hi = MSR_MC,.lo = 0x0}, /* Catch and fix dynamicly. */ + {.desc_name = MSR_GLIU0_SMM,.desc_type = BMO_SMM,.hi = MSR_MC,.lo = 0x0}, /* Catch and fix dynamicly. */ + {.desc_name = GLIU0_GLD_MSR_COH,.desc_type = OTHER,.hi = 0x0,.lo = + GL0_CPU}, + {.desc_name = GL_END,.desc_type = GL_END,.hi = 0x0,.lo = 0x0}, };
- struct gliutable gliu1table[] = { - {.desc_name=MSR_GLIU1_BASE1,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC*/ - {.desc_name=MSR_GLIU1_BASE2,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) +0x0FFFE0}, /* 80000-9ffff to Mc*/ - {.desc_name=MSR_GLIU1_SHADOW,.desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode)*/ - {.desc_name=MSR_GLIU1_SYSMEM,.desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly.*/ - {.desc_name=MSR_GLIU1_SMM,.desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly.*/ - {.desc_name=GLIU1_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0}, - {.desc_name=MSR_GLIU1_FPU_TRAP,.desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0*/ - {.desc_name=GL_END,.desc_type= GL_END,.hi= 0x0,.lo= 0x0}, + {.desc_name = MSR_GLIU1_BASE1,.desc_type = BM,.hi = MSR_GL0 + 0x0,.lo = 0x0FFF80}, /* 0-7FFFF to MC */ + {.desc_name = MSR_GLIU1_BASE2,.desc_type = BM,.hi = MSR_GL0 + 0x0,.lo = (0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc */ + {.desc_name = MSR_GLIU1_SHADOW,.desc_type = SC_SHADOW,.hi = MSR_GL0 + 0x0,.lo = 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) */ + {.desc_name = MSR_GLIU1_SYSMEM,.desc_type = R_SYSMEM,.hi = MSR_GL0,.lo = 0x0}, /* Catch and fix dynamicly. */ + {.desc_name = MSR_GLIU1_SMM,.desc_type = BM_SMM,.hi = MSR_GL0,.lo = 0x0}, /* Catch and fix dynamicly. */ + {.desc_name = GLIU1_GLD_MSR_COH,.desc_type = OTHER,.hi = 0x0,.lo = + GL1_GLIU0}, + {.desc_name = MSR_GLIU1_FPU_TRAP,.desc_type = SCIO,.hi = (GL1_GLCP << 29) + 0x0,.lo = 0x033000F0}, /* FooGlue FPU 0xF0 */ + {.desc_name = GL_END,.desc_type = GL_END,.hi = 0x0,.lo = 0x0}, };
-struct gliutable *gliutables[] = {gliu0table, gliu1table, 0}; +struct gliutable *gliutables[] = { gliu0table, gliu1table, 0 };
struct msrinit { unsigned long msrnum; msr_t msr; };
-struct msrinit ClockGatingDefault [] = { - {GLIU0_GLD_MSR_PM, {.hi=0x00,.lo=0x0005}}, - {MC_GLD_MSR_PM, {.hi=0x00,.lo=0x0001}}, - {VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}}, - {GP_GLD_MSR_PM, {.hi=0x00,.lo=0x0001}}, - {DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0555}}, - {GLIU1_GLD_MSR_PM, {.hi=0x00,.lo=0x0005}}, - {GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0014}}, - {GLPCI_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}}, - {VIP_GLD_MSR_PM, {.hi=0x00,.lo=0x0005}}, - {AES_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}}, - {CPU_BC_PMODE_MSR, {.hi=0x00,.lo=0x70303}}, - {0xffffffff, {0xffffffff, 0xffffffff}}, +struct msrinit ClockGatingDefault[] = { + {GLIU0_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}}, + {MC_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0001}}, + {VG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}}, + {GP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0001}}, + {DF_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0555}}, + {GLIU1_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}}, + {GLCP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0014}}, + {GLPCI_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}}, + {VIP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}}, + {AES_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}}, + {CPU_BC_PMODE_MSR, {.hi = 0x00,.lo = 0x70303}}, + {0xffffffff, {0xffffffff, 0xffffffff}}, };
/* */ /* SET GeodeLink PRIORITY*/ /* */ -struct msrinit GeodeLinkPriorityTable [] = { - {CPU_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0220}}, - {DF_GLD_MSR_MASTER_CONF, {.hi=0x00,.lo=0x0000}}, - {VG_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0720}}, - {GP_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0010}}, - {GLPCI_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0017}}, - {GLCP_GLD_MSR_CONF, {.hi=0x00,.lo=0x0001}}, - {VIP_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0622}}, - {AES_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0013}}, - {0x0FFFFFFFF, {0x0FFFFFFFF, 0x0FFFFFFFF}}, /* END*/ +struct msrinit GeodeLinkPriorityTable[] = { + {CPU_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0220}}, + {DF_GLD_MSR_MASTER_CONF, {.hi = 0x00,.lo = 0x0000}}, + {VG_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0720}}, + {GP_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0010}}, + {GLPCI_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0017}}, + {GLCP_GLD_MSR_CONF, {.hi = 0x00,.lo = 0x0001}}, + {VIP_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0622}}, + {AES_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0013}}, + {0x0FFFFFFFF, {0x0FFFFFFFF, 0x0FFFFFFFF}}, /* END */ };
extern int sizeram(void);
-static void -writeglmsr(struct gliutable *gl){ +static void writeglmsr(struct gliutable *gl) +{ msr_t msr;
msr.lo = gl->lo; msr.hi = gl->hi; wrmsr(gl->desc_name, msr); // MSR - see table above - printk_debug("%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo); // GX3 + printk_debug("%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo); // GX3 }
-static void -ShadowInit(struct gliutable *gl) +static void ShadowInit(struct gliutable *gl) { msr_t msr;
msr = rdmsr(gl->desc_name);
if (msr.lo == 0) { - writeglmsr(gl); + writeglmsr(gl); } }
@@ -129,8 +128,8 @@ msr_t msr; int sizembytes, sizebytes;
- /* - * Figure out how much RAM is in the machine and alocate all to the + /* + * Figure out how much RAM is in the machine and alocate all to the * system. We will adjust for SMM now and Frame Buffer later. */ sizembytes = sizeram(); @@ -141,25 +140,26 @@ printk_debug("usable RAM: %d bytes\n", sizebytes);
/* 20 bit address The bottom 12 bits go into bits 20-31 in msr.lo - The top 8 bits go into 0-7 of msr.hi. */ + The top 8 bits go into 0-7 of msr.hi. */ sizebytes--; msr.hi = (gl->hi & 0xFFFFFF00) | (sizebytes >> 24); - sizebytes <<= 8; /* move bits 23:12 in bits 31:20. */ + sizebytes <<= 8; /* move bits 23:12 in bits 31:20. */ sizebytes &= 0xfff00000; - sizebytes |= 0x100; /* start at 1MB */ + sizebytes |= 0x100; /* start at 1MB */ msr.lo = sizebytes;
wrmsr(gl->desc_name, msr); // MSR - see table above printk_debug("%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, - gl->desc_name, msr.hi, msr.lo); + gl->desc_name, msr.hi, msr.lo); }
-static void SMMGL0Init(struct gliutable *gl) { +static void SMMGL0Init(struct gliutable *gl) +{ msr_t msr; - int sizebytes = sizeram()<<20; + int sizebytes = sizeram() << 20; long offset;
- sizebytes -= (SMM_SIZE*1024); + sizebytes -= (SMM_SIZE * 1024);
printk_debug("%s: %d bytes\n", __FUNCTION__, sizebytes);
@@ -169,51 +169,55 @@ printk_debug("%s: offset is 0x%08x\n", __FUNCTION__, SMM_OFFSET);
msr.hi = offset << 8 | gl->hi; - msr.hi |= SMM_OFFSET>>24; + msr.hi |= SMM_OFFSET >> 24;
msr.lo = SMM_OFFSET << 8; - msr.lo |= ((~(SMM_SIZE*1024)+1)>>12)&0xfffff; - + msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff; + wrmsr(gl->desc_name, msr); // MSR - See table above - printk_debug("%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo); + printk_debug("%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, + gl->desc_name, msr.hi, msr.lo); }
-static void SMMGL1Init(struct gliutable *gl) { +static void SMMGL1Init(struct gliutable *gl) +{ msr_t msr; - printk_debug("%s:\n", __FUNCTION__ ); + printk_debug("%s:\n", __FUNCTION__);
msr.hi = gl->hi; /* I don't think this is needed */ msr.hi &= 0xffffff00; msr.hi |= (SMM_OFFSET >> 24); msr.lo = (SMM_OFFSET << 8) & 0xFFF00000; - msr.lo |= ((~(SMM_SIZE*1024)+1)>>12)&0xfffff; - + msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff; + wrmsr(gl->desc_name, msr); // MSR - See table above - printk_debug("%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo); + printk_debug("%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, + gl->desc_name, msr.hi, msr.lo); }
-static void GLIUInit(struct gliutable *gl){ +static void GLIUInit(struct gliutable *gl) +{
- while (gl->desc_type != GL_END){ - switch(gl->desc_type){ - default: + while (gl->desc_type != GL_END) { + switch (gl->desc_type) { + default: /* For Unknown types: Write then read MSR */ writeglmsr(gl); - case SC_SHADOW: /* Check for a Shadow entry*/ + case SC_SHADOW: /* Check for a Shadow entry */ ShadowInit(gl); break; - - case R_SYSMEM: /* check for a SYSMEM entry*/ + + case R_SYSMEM: /* check for a SYSMEM entry */ SysmemInit(gl); break; - - case BMO_SMM : /* check for a SMM entry*/ + + case BMO_SMM: /* check for a SMM entry */ SMMGL0Init(gl); break; - - case BM_SMM : /* check for a SMM entry*/ - SMMGL1Init(gl); + + case BM_SMM: /* check for a SMM entry */ + SMMGL1Init(gl); break; } gl++; @@ -221,23 +225,24 @@
}
- /* ***************************************************************************/ - /* **/ - /* * GLPCIInit*/ - /* **/ - /* * Set up GLPCI settings for reads/write into memory*/ - /* * R0: 0-640KB,*/ - /* * R1: 1MB - Top of System Memory*/ - /* * R2: SMM Memory*/ - /* * R3: Framebuffer? - not set up yet*/ - /* * R4: ??*/ - /* **/ - /* * Entry:*/ - /* * Exit:*/ - /* * Modified:*/ - /* **/ - /* ***************************************************************************/ -static void GLPCIInit(void){ + /* ************************************************************************** */ + /* * */ + /* * GLPCIInit */ + /* * */ + /* * Set up GLPCI settings for reads/write into memory */ + /* * R0: 0-640KB, */ + /* * R1: 1MB - Top of System Memory */ + /* * R2: SMM Memory */ + /* * R3: Framebuffer? - not set up yet */ + /* * R4: ?? */ + /* * */ + /* * Entry: */ + /* * Exit: */ + /* * Modified: */ + /* * */ + /* ************************************************************************** */ +static void GLPCIInit(void) +{ struct gliutable *gl = 0; int i; msr_t msr; @@ -245,19 +250,21 @@ int nic_grants_control, enable_bus_parking;
/* */ - /* R0 - GLPCI settings for Conventional Memory space.*/ + /* R0 - GLPCI settings for Conventional Memory space. */ /* */ - msr.hi = (0x09F000 >> 12) << GLPCI_RC_UPPER_TOP_SHIFT; /* 640 */ - msr.lo = 0; /* 0*/ - msr.lo |= GLPCI_RC_LOWER_EN_SET+ GLPCI_RC_LOWER_PF_SET + GLPCI_RC_LOWER_WC_SET; + msr.hi = (0x09F000 >> 12) << GLPCI_RC_UPPER_TOP_SHIFT; /* 640 */ + msr.lo = 0; /* 0 */ + msr.lo |= + GLPCI_RC_LOWER_EN_SET + GLPCI_RC_LOWER_PF_SET + + GLPCI_RC_LOWER_WC_SET; msrnum = GLPCI_RC0; wrmsr(msrnum, msr);
/* */ - /* R1 - GLPCI settings for SysMem space.*/ + /* R1 - GLPCI settings for SysMem space. */ /* */ - /* Get systop from GLIU0 SYSTOP Descriptor*/ - for(i = 0; gliu0table[i].desc_name != GL_END; i++) { + /* Get systop from GLIU0 SYSTOP Descriptor */ + for (i = 0; gliu0table[i].desc_name != GL_END; i++) { if (gliu0table[i].desc_type == R_SYSMEM) { gl = &gliu0table[i]; break; @@ -268,8 +275,8 @@ msrnum = gl->desc_name; msr = rdmsr(msrnum); /* example R_SYSMEM value: 20:00:00:0f:fb:f0:01:00 - * translates to a base of 0x00100000 and top of 0xffbf0000 - * base of 1M and top of around 256M + * translates to a base of 0x00100000 and top of 0xffbf0000 + * base of 1M and top of around 256M */ /* we have to create a page-aligned (4KB page) address for base and top */ /* So we need a high page aligned addresss (pah) and low page aligned address (pal) @@ -280,28 +287,34 @@ pah <<= 12;
pal = msr.lo << 12; - msr.hi = pah; - msr.lo = pal; - msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET | GLPCI_RC_LOWER_WC_SET; - printk_debug("GLPCI R1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi); + msr.hi = pah; + msr.lo = pal; + msr.lo |= + GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET | + GLPCI_RC_LOWER_WC_SET; + printk_debug("GLPCI R1: system msr.lo 0x%08x msr.hi 0x%08x\n", + msr.lo, msr.hi); msrnum = GLPCI_RC1; wrmsr(msrnum, msr); }
/* */ - /* R2 - GLPCI settings for SMM space */ + /* R2 - GLPCI settings for SMM space */ /* */ - msr.hi = ((SMM_OFFSET+(SMM_SIZE*1024-1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT; - msr.lo = (SMM_OFFSET >> 12) << GLPCI_RC_LOWER_BASE_SHIFT; + msr.hi = + ((SMM_OFFSET + + (SMM_SIZE * 1024 - 1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT; + msr.lo = (SMM_OFFSET >> 12) << GLPCI_RC_LOWER_BASE_SHIFT; msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET; - printk_debug("GLPCI R2: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi); + printk_debug("GLPCI R2: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, + msr.hi); msrnum = GLPCI_RC2; wrmsr(msrnum, msr);
/* this is done elsewhere already, but it does no harm to do it more than once */ - /* write serialize memory hole to PCI. Need to to unWS when something is shadowed regardless of cachablility.*/ - msr.lo = 0x021212121; /* cache disabled and write serialized */ - msr.hi = 0x021212121; /* cache disabled and write serialized */ + /* write serialize memory hole to PCI. Need to to unWS when something is shadowed regardless of cachablility. */ + msr.lo = 0x021212121; /* cache disabled and write serialized */ + msr.hi = 0x021212121; /* cache disabled and write serialized */
msrnum = CPU_RCONF_A0_BF; wrmsr(msrnum, msr); @@ -312,181 +325,186 @@ msrnum = CPU_RCONF_E0_FF; wrmsr(msrnum, msr);
- /* Set Non-Cacheable Read Only for NorthBound Transactions to Memory. The Enable bit is handled in the Shadow setup.*/ + /* Set Non-Cacheable Read Only for NorthBound Transactions to Memory. The Enable bit is handled in the Shadow setup. */ msrnum = GLPCI_A0_BF; - msr.hi = 0x35353535; - msr.lo = 0x35353535; + msr.hi = 0x35353535; + msr.lo = 0x35353535; wrmsr(msrnum, msr);
msrnum = GLPCI_C0_DF; - msr.hi = 0x35353535; - msr.lo = 0x35353535; + msr.hi = 0x35353535; + msr.lo = 0x35353535; wrmsr(msrnum, msr);
msrnum = GLPCI_E0_FF; - msr.hi = 0x35353535; - msr.lo = 0x35353535; + msr.hi = 0x35353535; + msr.lo = 0x35353535; wrmsr(msrnum, msr);
- /* Set WSREQ*/ + /* Set WSREQ */ msrnum = CPU_DM_CONFIG0; msr = rdmsr(msrnum); - msr.hi &= ~ (7 << DM_CONFIG0_UPPER_WSREQ_SHIFT); + msr.hi &= ~(7 << DM_CONFIG0_UPPER_WSREQ_SHIFT); msr.hi |= 2 << DM_CONFIG0_UPPER_WSREQ_SHIFT; /* reduce to 1 for safe mode */ wrmsr(msrnum, msr);
/* we are ignoring the 5530 case for now, and perhaps forever. */
/* */ - /* 553x NB Init*/ - /* */ + /* 553x NB Init */ + /* */
/* Arbiter setup */ - enable_preempt = GLPCI_ARB_LOWER_PRE0_SET | GLPCI_ARB_LOWER_PRE1_SET | GLPCI_ARB_LOWER_PRE2_SET | GLPCI_ARB_LOWER_CPRE_SET; + enable_preempt = + GLPCI_ARB_LOWER_PRE0_SET | GLPCI_ARB_LOWER_PRE1_SET | + GLPCI_ARB_LOWER_PRE2_SET | GLPCI_ARB_LOWER_CPRE_SET; enable_cpu_override = GLPCI_ARB_LOWER_COV_SET; enable_bus_parking = GLPCI_ARB_LOWER_PARK_SET; - nic_grants_control = (0x4 << GLPCI_ARB_UPPER_R2_SHIFT) | (0x3 << GLPCI_ARB_UPPER_H2_SHIFT ); + nic_grants_control = + (0x4 << GLPCI_ARB_UPPER_R2_SHIFT) | (0x3 << + GLPCI_ARB_UPPER_H2_SHIFT);
msrnum = GLPCI_ARB; msr = rdmsr(msrnum);
- msr.hi |= nic_grants_control; - msr.lo |= enable_cpu_override | enable_preempt | enable_bus_parking; + msr.hi |= nic_grants_control; + msr.lo |= enable_cpu_override | enable_preempt | enable_bus_parking; wrmsr(msrnum, msr);
msrnum = GLPCI_CTRL; msr = rdmsr(msrnum);
- msr.lo |= GLPCI_CTRL_LOWER_ME_SET | GLPCI_CTRL_LOWER_OWC_SET | GLPCI_CTRL_LOWER_PCD_SET; /* (Out will be disabled in CPUBUG649 for < 2.0 parts .)*/ - msr.lo |= GLPCI_CTRL_LOWER_LDE_SET; + msr.lo |= GLPCI_CTRL_LOWER_ME_SET | GLPCI_CTRL_LOWER_OWC_SET | GLPCI_CTRL_LOWER_PCD_SET; /* (Out will be disabled in CPUBUG649 for < 2.0 parts .) */ + msr.lo |= GLPCI_CTRL_LOWER_LDE_SET;
- msr.lo &= ~ (0x03 << GLPCI_CTRL_LOWER_IRFC_SHIFT); - msr.lo |= 0x02 << GLPCI_CTRL_LOWER_IRFC_SHIFT; + msr.lo &= ~(0x03 << GLPCI_CTRL_LOWER_IRFC_SHIFT); + msr.lo |= 0x02 << GLPCI_CTRL_LOWER_IRFC_SHIFT;
- msr.lo &= ~ (0x07 << GLPCI_CTRL_LOWER_IRFT_SHIFT); - msr.lo |= 0x06 << GLPCI_CTRL_LOWER_IRFT_SHIFT; - - msr.hi &= ~ (0x0f << GLPCI_CTRL_UPPER_FTH_SHIFT); - msr.hi |= 0x0F << GLPCI_CTRL_UPPER_FTH_SHIFT; - - msr.hi &= ~ (0x0f << GLPCI_CTRL_UPPER_RTH_SHIFT); - msr.hi |= 0x0F << GLPCI_CTRL_UPPER_RTH_SHIFT; - - msr.hi &= ~ (0x0f << GLPCI_CTRL_UPPER_SBRTH_SHIFT); - msr.hi |= 0x0F << GLPCI_CTRL_UPPER_SBRTH_SHIFT; - - msr.hi &= ~ (0x03 << GLPCI_CTRL_UPPER_WTO_SHIFT); - msr.hi |= 0x06 << GLPCI_CTRL_UPPER_WTO_SHIFT; - - msr.hi &= ~ (0x03 << GLPCI_CTRL_UPPER_ILTO_SHIFT); - msr.hi |= 0x00 << GLPCI_CTRL_UPPER_ILTO_SHIFT; - wrmsr(msrnum, msr); + msr.lo &= ~(0x07 << GLPCI_CTRL_LOWER_IRFT_SHIFT); + msr.lo |= 0x06 << GLPCI_CTRL_LOWER_IRFT_SHIFT;
+ msr.hi &= ~(0x0f << GLPCI_CTRL_UPPER_FTH_SHIFT); + msr.hi |= 0x0F << GLPCI_CTRL_UPPER_FTH_SHIFT; + + msr.hi &= ~(0x0f << GLPCI_CTRL_UPPER_RTH_SHIFT); + msr.hi |= 0x0F << GLPCI_CTRL_UPPER_RTH_SHIFT; + + msr.hi &= ~(0x0f << GLPCI_CTRL_UPPER_SBRTH_SHIFT); + msr.hi |= 0x0F << GLPCI_CTRL_UPPER_SBRTH_SHIFT; + + msr.hi &= ~(0x03 << GLPCI_CTRL_UPPER_WTO_SHIFT); + msr.hi |= 0x06 << GLPCI_CTRL_UPPER_WTO_SHIFT; + + msr.hi &= ~(0x03 << GLPCI_CTRL_UPPER_ILTO_SHIFT); + msr.hi |= 0x00 << GLPCI_CTRL_UPPER_ILTO_SHIFT; + wrmsr(msrnum, msr);
/* Set GLPCI Latency Timer */ msrnum = GLPCI_CTRL; msr = rdmsr(msrnum); - msr.hi |= 0x1F << GLPCI_CTRL_UPPER_LAT_SHIFT; /* Change once 1.x is gone */ + msr.hi |= 0x1F << GLPCI_CTRL_UPPER_LAT_SHIFT; /* Change once 1.x is gone */ wrmsr(msrnum, msr);
- /* GLPCI_SPARE*/ + /* GLPCI_SPARE */ msrnum = GLPCI_SPARE; msr = rdmsr(msrnum); - msr.lo &= ~ 0x7; - msr.lo |= GLPCI_SPARE_LOWER_AILTO_SET | GLPCI_SPARE_LOWER_PPD_SET | GLPCI_SPARE_LOWER_PPC_SET | GLPCI_SPARE_LOWER_MPC_SET | GLPCI_SPARE_LOWER_NSE_SET | GLPCI_SPARE_LOWER_SUPO_SET; + msr.lo &= ~0x7; + msr.lo |= + GLPCI_SPARE_LOWER_AILTO_SET | GLPCI_SPARE_LOWER_PPD_SET | + GLPCI_SPARE_LOWER_PPC_SET | GLPCI_SPARE_LOWER_MPC_SET | + GLPCI_SPARE_LOWER_NSE_SET | GLPCI_SPARE_LOWER_SUPO_SET; wrmsr(msrnum, msr); }
- - - /* ***************************************************************************/ - /* **/ - /* * ClockGatingInit*/ - /* **/ - /* * Enable Clock Gating.*/ - /* **/ - /* * Entry:*/ - /* * Exit:*/ - /* * Modified:*/ - /* **/ - /* ***************************************************************************/ -static void ClockGatingInit (void){ + /* ************************************************************************** */ + /* * */ + /* * ClockGatingInit */ + /* * */ + /* * Enable Clock Gating. */ + /* * */ + /* * Entry: */ + /* * Exit: */ + /* * Modified: */ + /* * */ + /* ************************************************************************** */ +static void ClockGatingInit(void) +{ msr_t msr; struct msrinit *gating = ClockGatingDefault; int i;
- for(i = 0; gating->msrnum != 0xffffffff; i++) { + for (i = 0; gating->msrnum != 0xffffffff; i++) { msr = rdmsr(gating->msrnum); msr.hi |= gating->msr.hi; msr.lo |= gating->msr.lo; - /* printk_debug("%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __FUNCTION__, - gating->msrnum, msr.hi, msr.lo); */ // GX3 + /* printk_debug("%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __FUNCTION__, + gating->msrnum, msr.hi, msr.lo); */// GX3 wrmsr(gating->msrnum, msr); // MSR - See the table above - gating +=1; + gating += 1; }
}
-static void GeodeLinkPriority(void){ +static void GeodeLinkPriority(void) +{ msr_t msr; struct msrinit *prio = GeodeLinkPriorityTable; int i;
- for(i = 0; prio->msrnum != 0xffffffff; i++) { + for (i = 0; prio->msrnum != 0xffffffff; i++) { msr = rdmsr(prio->msrnum); msr.hi |= prio->msr.hi; msr.lo &= ~0xfff; msr.lo |= prio->msr.lo; - /* printk_debug("%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __FUNCTION__, - prio->msrnum, msr.hi, msr.lo); */ // GX3 + /* printk_debug("%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __FUNCTION__, + prio->msrnum, msr.hi, msr.lo); */// GX3 wrmsr(prio->msrnum, msr); // MSR - See the table above - prio +=1; + prio += 1; } }
- - /* * Get the GLIU0 shadow register settings * If the setShadow function is used then all shadow descriptors * will stay sync'ed. */ -static uint64_t getShadow(void){ +static uint64_t getShadow(void) +{ msr_t msr;
msr = rdmsr(MSR_GLIU0_SHADOW); - return ( ( (uint64_t) msr.hi ) << 32 ) | msr.lo; + return (((uint64_t) msr.hi) << 32) | msr.lo; }
- /* * Set the cache RConf registers for the memory hole. * Keeps all cache shadow descriptors sync'ed. * This is part of the PCI lockup solution * Entry: EDX:EAX is the shadow settings */ -static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo){ +static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo) +{
// ok this is whacky bit translation time. int bit; uint8_t shadowByte; - msr_t msr = {0, 0}; + msr_t msr = { 0, 0 }; shadowByte = (uint8_t) (shadowLo >> 16);
// load up D000 settings in edx. for (bit = 8; (bit > 4); bit--) { msr.hi <<= 8; - msr.hi |= 1; // cache disable PCI/Shadow memory + msr.hi |= 1; // cache disable PCI/Shadow memory if (shadowByte && (1 << bit)) - msr.hi |= 0x20; // write serialize PCI memory + msr.hi |= 0x20; // write serialize PCI memory }
// load up C000 settings in eax. - for ( ; bit; bit--) { + for (; bit; bit--) { msr.lo <<= 8; - msr.lo |= 1; // cache disable PCI/Shadow memory + msr.lo |= 1; // cache disable PCI/Shadow memory if (shadowByte && (1 << bit)) - msr.lo |= 0x20; // write serialize PCI memory + msr.lo |= 0x20; // write serialize PCI memory }
wrmsr(CPU_RCONF_C0_DF, msr); @@ -496,23 +514,22 @@ // load up F000 settings in edx. for (bit = 8; (bit > 4); bit--) { msr.hi <<= 8; - msr.hi |= 1; // cache disable PCI/Shadow memory + msr.hi |= 1; // cache disable PCI/Shadow memory if (shadowByte && (1 << bit)) - msr.hi |= 0x20; // write serialize PCI memory + msr.hi |= 0x20; // write serialize PCI memory }
// load up E000 settings in eax. - for ( ; bit; bit--) { + for (; bit; bit--) { msr.lo <<= 8; - msr.lo |= 1; // cache disable PCI/Shadow memory + msr.lo |= 1; // cache disable PCI/Shadow memory if (shadowByte && (1 << bit)) - msr.lo |= 0x20; // write serialize PCI memory + msr.lo |= 0x20; // write serialize PCI memory }
wrmsr(CPU_RCONF_E0_FF, msr); }
- /* * Set the GLPCI registers for the memory hole. * Keeps all cache shadow descriptors sync'ed. @@ -521,15 +538,14 @@ static void setShadowGLPCI(uint32_t shadowHi, uint32_t shadowLo) { msr_t msr; - + // Set the Enable Register. msr = rdmsr(GLPCI_REN); msr.lo &= 0xFFFF00FF; - msr.lo |= ( (shadowLo & 0xFFFF0000) >> 8); + msr.lo |= ((shadowLo & 0xFFFF0000) >> 8); wrmsr(GLPCI_REN, msr); }
- /* * Set the GLIU SC register settings. Scans descriptor tables for SC_SHADOW. * Keeps all shadow descriptors sync'ed. @@ -539,7 +555,7 @@ { int i; msr_t msr; - struct gliutable* pTable; + struct gliutable *pTable; uint32_t shadowLo, shadowHi;
shadowLo = (uint32_t) shadowSettings; @@ -548,21 +564,25 @@ setShadowRCONF(shadowHi, shadowLo); setShadowGLPCI(shadowHi, shadowLo);
- for(i = 0; gliutables[i]; i++) { - for (pTable = gliutables[i]; pTable->desc_type != GL_END; pTable++) { + for (i = 0; gliutables[i]; i++) { + for (pTable = gliutables[i]; pTable->desc_type != GL_END; + pTable++) { if (pTable->desc_type == SC_SHADOW) {
msr = rdmsr(pTable->desc_name); msr.lo = (uint32_t) shadowSettings; - msr.hi &= 0xFFFF0000; // maintain PDID in upper EDX - msr.hi |= ((uint32_t) (shadowSettings >> 32)) & 0x0000FFFF; + msr.hi &= 0xFFFF0000; // maintain PDID in upper EDX + msr.hi |= + ((uint32_t) (shadowSettings >> 32)) & + 0x0000FFFF; wrmsr(pTable->desc_name, msr); // MSR - See the table above } } } }
-static void rom_shadow_settings(void){ +static void rom_shadow_settings(void) +{
uint64_t shadowSettings = getShadow(); shadowSettings &= (uint64_t) 0xFFFF00000000FFFFULL; // Disable read & writes @@ -571,8 +591,6 @@ setShadow(shadowSettings); }
- - /*************************************************************************** * * L1Init @@ -583,7 +601,7 @@ * ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of rom chipselect area * DEVRC(35:28) = 39h ; cache disabled in PCI memory + WS bit on + Write Combine + write burst. * SYSTOP(27:8) = top of system memory - * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough + * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough * ***************************************************************************/ #define SYSMEM_RCONF_WRITETHROUGH 8 @@ -599,27 +617,26 @@ uint8_t SysMemCacheProp;
/* Locate SYSMEM entry in GLIU0table */ - for(i = 0; gliu0table[i].desc_name != GL_END; i++) { + for (i = 0; gliu0table[i].desc_name != GL_END; i++) { if (gliu0table[i].desc_type == R_SYSMEM) { gl = &gliu0table[i]; break; } } if (gl == 0) { - post_code(0xCE); /* POST_RCONFInitError */ - while (1); + post_code(0xCE); /* POST_RCONFInitError */ + while (1) ; } - -// sysdescfound: +// sysdescfound: msr = rdmsr(gl->desc_name);
- /* 20 bit address - The bottom 12 bits go into bits 20-31 in eax, the - * top 8 bits go into 0-7 of edx. + /* 20 bit address - The bottom 12 bits go into bits 20-31 in eax, the + * top 8 bits go into 0-7 of edx. */ msr.lo = (msr.lo & 0xFFFFFF00) | (msr.hi & 0xFF); msr.lo = ((msr.lo << 12) | (msr.lo >> 20)) & 0x000FFFFF; msr.lo <<= RCONF_DEFAULT_LOWER_SYSTOP_SHIFT; // 8 - + // Set Default SYSMEM region properties msr.lo &= ~SYSMEM_RCONF_WRITETHROUGH; // NOT writethrough == writeback 8 (or ~8)
@@ -628,27 +645,32 @@ msr.lo |= (DEVRC_RCONF_DEFAULT << 28);
// Set the ROMBASE. This is usually FFFC0000h - msr.hi |= (ROMBASE_RCONF_DEFAULT >> 12) << RCONF_DEFAULT_UPPER_ROMBASE_SHIFT; + msr.hi |= + (ROMBASE_RCONF_DEFAULT >> 12) << RCONF_DEFAULT_UPPER_ROMBASE_SHIFT;
// Set ROMBASE cache properties. msr.hi |= ((ROMRC_RCONF_DEFAULT >> 8) | (ROMRC_RCONF_DEFAULT << 24)); - + // now program RCONF_DEFAULT wrmsr(CPU_RCONF_DEFAULT, msr); - printk_debug("CPU_RCONF_DEFAULT (1808): 0x%08X:0x%08X\n",msr.hi,msr.lo); + printk_debug("CPU_RCONF_DEFAULT (1808): 0x%08X:0x%08X\n", msr.hi, + msr.lo);
// RCONF_BYPASS: Cache tablewalk properties and SMM/DMM header access properties. // Set to match system memory cache properties. msr = rdmsr(CPU_RCONF_DEFAULT); SysMemCacheProp = (uint8_t) (msr.lo & 0xFF); msr = rdmsr(CPU_RCONF_BYPASS); - msr.lo = (msr.lo & 0xFFFF0000) | (SysMemCacheProp << 8) | SysMemCacheProp; + msr.lo = + (msr.lo & 0xFFFF0000) | (SysMemCacheProp << 8) | SysMemCacheProp; wrmsr(CPU_RCONF_BYPASS, msr); - - printk_debug("CPU_RCONF_BYPASS (180A): 0x%08x : 0x%08x\n", msr.hi, msr.lo); + + printk_debug("CPU_RCONF_BYPASS (180A): 0x%08x : 0x%08x\n", msr.hi, + msr.lo); }
-static void enable_L2_cache(void) { +static void enable_L2_cache(void) +{ msr_t msr;
/* Instruction Memory Configuration register @@ -695,13 +717,14 @@ wbinvd(); }
-uint32_t get_systop(void) { +uint32_t get_systop(void) +{ struct gliutable *gl = 0; uint32_t systop; msr_t msr; int i;
- for(i = 0; gliu0table[i].desc_name != GL_END; i++) { + for (i = 0; gliu0table[i].desc_name != GL_END; i++) { if (gliu0table[i].desc_type == R_SYSMEM) { gl = &gliu0table[i]; break; @@ -710,9 +733,10 @@ if (gl) { msr = rdmsr(gl->desc_name); systop = ((msr.hi & 0xFF) << 24) | ((msr.lo & 0xFFF00000) >> 8); - systop += 0x1000; /* 4K */ - }else{ - systop = ((sizeram() - CONFIG_VIDEO_MB) * 1024) - SMM_SIZE - 1024; + systop += 0x1000; /* 4K */ + } else { + systop = + ((sizeram() - CONFIG_VIDEO_MB) * 1024) - SMM_SIZE - 1024; } return systop; } @@ -729,12 +753,12 @@ int i; printk_debug("Enter %s\n", __FUNCTION__);
- for(i = 0; gliutables[i]; i++) + for (i = 0; gliutables[i]; i++) GLIUInit(gliutables[i]);
- /* Now that the descriptor to memory is set up.*/ - /* The memory controller needs one read to synch its lines before it can be used.*/ - i = *(int *) 0; + /* Now that the descriptor to memory is set up. */ + /* The memory controller needs one read to synch its lines before it can be used. */ + i = *(int *)0;
GeodeLinkPriority();
@@ -749,4 +773,3 @@ __asm__ __volatile__("FINIT\n"); printk_debug("Exit %s\n", __FUNCTION__); } - Index: LinuxBIOSv2/src/northbridge/amd/lx/pll_reset.c =================================================================== --- LinuxBIOSv2.orig/src/northbridge/amd/lx/pll_reset.c 2007-05-04 13:44:14.000000000 -0600 +++ LinuxBIOSv2/src/northbridge/amd/lx/pll_reset.c 2007-05-04 13:44:16.000000000 -0600 @@ -22,43 +22,47 @@ { msr_t msrGlcpSysRstpll;
- msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL); - + msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL); + print_debug("_MSR GLCP_SYS_RSTPLL ("); - print_debug_hex32(GLCP_SYS_RSTPLL); - print_debug(") value is: "); - print_debug_hex32(msrGlcpSysRstpll.hi); - print_debug(":"); - print_debug_hex32(msrGlcpSysRstpll.lo); - print_debug("\r\n"); + print_debug_hex32(GLCP_SYS_RSTPLL); + print_debug(") value is: "); + print_debug_hex32(msrGlcpSysRstpll.hi); + print_debug(":"); + print_debug_hex32(msrGlcpSysRstpll.lo); + print_debug("\r\n"); POST_CODE(POST_PLL_INIT); - - if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))){ + + if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) { print_debug("Configuring PLL\n"); - if(manualconf){ + if (manualconf) { POST_CODE(POST_PLL_MANUAL); /* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2) */ - msrGlcpSysRstpll.hi = PLLMSRhi; + msrGlcpSysRstpll.hi = PLLMSRhi;
/* Hold Count - how long we will sit in reset */ - msrGlcpSysRstpll.lo = PLLMSRlo; - } - else{ - /*automatic configuration (straps)*/ + msrGlcpSysRstpll.lo = PLLMSRlo; + } else { + /*automatic configuration (straps) */ POST_CODE(POST_PLL_STRAP); - msrGlcpSysRstpll.lo &= ~(0xFF << RSTPPL_LOWER_HOLD_COUNT_SHIFT); - msrGlcpSysRstpll.lo |= (0xDE << RSTPPL_LOWER_HOLD_COUNT_SHIFT); - msrGlcpSysRstpll.lo &= ~(RSTPPL_LOWER_COREBYPASS_SET | RSTPPL_LOWER_MBBYPASS_SET); - msrGlcpSysRstpll.lo |= RSTPPL_LOWER_COREPD_SET | RSTPPL_LOWER_CLPD_SET; + msrGlcpSysRstpll.lo &= + ~(0xFF << RSTPPL_LOWER_HOLD_COUNT_SHIFT); + msrGlcpSysRstpll.lo |= + (0xDE << RSTPPL_LOWER_HOLD_COUNT_SHIFT); + msrGlcpSysRstpll.lo &= + ~(RSTPPL_LOWER_COREBYPASS_SET | + RSTPPL_LOWER_MBBYPASS_SET); + msrGlcpSysRstpll.lo |= + RSTPPL_LOWER_COREPD_SET | RSTPPL_LOWER_CLPD_SET; } - /* Use SWFLAGS to remember: "we've already been here" */ + /* Use SWFLAGS to remember: "we've already been here" */ msrGlcpSysRstpll.lo |= (1 << RSTPLL_LOWER_SWFLAGS_SHIFT);
- /* "reset the chip" value */ + /* "reset the chip" value */ msrGlcpSysRstpll.lo |= RSTPPL_LOWER_CHIP_RESET_SET; wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
- /* You should never get here..... The chip has reset.*/ + /* You should never get here..... The chip has reset. */ print_debug("CONFIGURING PLL FAILURE\n"); POST_CODE(POST_PLL_RESET_FAIL); __asm__ __volatile__("hlt\n"); @@ -68,37 +72,42 @@ return; }
-static unsigned int CPUSpeed(void){ +static unsigned int CPUSpeed(void) +{ unsigned int speed; msr_t msr;
msr = rdmsr(GLCP_SYS_RSTPLL); - speed = ((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F)+1)*333)/10; - if((((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F)+1)*333)%10) > 5){ + speed = + ((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + 1) * 333) / 10; + if ((((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + + 1) * 333) % 10) > 5) { ++speed; } - return(speed); + return (speed); } -static unsigned int GeodeLinkSpeed(void){ +static unsigned int GeodeLinkSpeed(void) +{ unsigned int speed; msr_t msr;
msr = rdmsr(GLCP_SYS_RSTPLL); - speed = ((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F)+1)*333)/10; - if((((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F)+1)*333)%10) > 5){ + speed = + ((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) / 10; + if ((((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + + 1) * 333) % 10) > 5) { ++speed; } - return(speed); + return (speed); } -static unsigned int PCISpeed(void){ +static unsigned int PCISpeed(void) +{ msr_t msr;
msr = rdmsr(GLCP_SYS_RSTPLL); - if (msr.hi & (1 << RSTPPL_LOWER_PCISPEED_SHIFT)){ - return(66); - } - else{ - return(33); + if (msr.hi & (1 << RSTPPL_LOWER_PCISPEED_SHIFT)) { + return (66); + } else { + return (33); } } - Index: LinuxBIOSv2/src/northbridge/amd/lx/raminit.c =================================================================== --- LinuxBIOSv2.orig/src/northbridge/amd/lx/raminit.c 2007-05-04 13:44:14.000000000 -0600 +++ LinuxBIOSv2/src/northbridge/amd/lx/raminit.c 2007-05-04 13:44:16.000000000 -0600 @@ -22,9 +22,12 @@ #include <spd.h> #include "southbridge/amd/cs5536/cs5536.h"
-static const unsigned char NumColAddr[] = {0x00,0x10,0x11,0x00,0x00,0x00,0x00,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F}; +static const unsigned char NumColAddr[] = + { 0x00, 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x07, 0x08, 0x09, 0x0A, 0x0B, +0x0C, 0x0D, 0x0E, 0x0F };
-static void auto_size_dimm(unsigned int dimm){ +static void auto_size_dimm(unsigned int dimm) +{ uint32_t dimm_setting; uint16_t dimm_size; uint8_t spd_byte; @@ -33,60 +36,58 @@ dimm_setting = 0;
/* Check that we have a dimm */ - if (spd_read_byte(dimm, SPD_MEMORY_TYPE) == 0xFF){ + if (spd_read_byte(dimm, SPD_MEMORY_TYPE) == 0xFF) { return; -} + }
/* Field: Module Banks per DIMM */ /* EEPROM byte usage: (5) Number of DIMM Banks */ spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS); - if ((MIN_MOD_BANKS > spd_byte) && (spd_byte > MAX_MOD_BANKS)){ + if ((MIN_MOD_BANKS > spd_byte) && (spd_byte > MAX_MOD_BANKS)) { print_debug("Number of module banks not compatible\r\n"); POST_CODE(ERROR_BANK_SET); __asm__ __volatile__("hlt\n"); } dimm_setting |= (spd_byte >> 1) << CF07_UPPER_D0_MB_SHIFT;
- /* Field: Banks per SDRAM device */ /* EEPROM byte usage: (17) Number of Banks on SDRAM Device */ spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM); - if ((MIN_DEV_BANKS > spd_byte) && (spd_byte > MAX_DEV_BANKS)){ + if ((MIN_DEV_BANKS > spd_byte) && (spd_byte > MAX_DEV_BANKS)) { print_debug("Number of device banks not compatible\r\n"); POST_CODE(ERROR_BANK_SET); __asm__ __volatile__("hlt\n"); } dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT;
- /*; Field: DIMM size - *; EEPROM byte usage: (3) Number or Row Addresses - *; (4) Number of Column Addresses - *; (5) Number of DIMM Banks - *; (31) Module Bank Density - *; Size = Module Density * Module Banks + *; EEPROM byte usage: (3) Number or Row Addresses + *; (4) Number of Column Addresses + *; (5) Number of DIMM Banks + *; (31) Module Bank Density + *; Size = Module Density * Module Banks */ - if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0) || (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)){ + if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0) + || (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) { print_debug("Assymetirc DIMM not compatible\r\n"); POST_CODE(ERROR_UNSUPPORTED_DIMM); __asm__ __volatile__("hlt\n"); }
dimm_size = spd_read_byte(dimm, SPD_BANK_DENSITY); - dimm_size |= (dimm_size << 8); /* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out*/ - dimm_size &= 0x01FC; /* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top*/ + dimm_size |= (dimm_size << 8); /* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out */ + dimm_size &= 0x01FC; /* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top */
- /* Module Density * Module Banks */ - dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */ + /* Module Density * Module Banks */ + dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */ dimm_size = __builtin_ctz(dimm_size); - if (dimm_size > 8){ /* 8 is 1GB only support 1GB per DIMM */ + if (dimm_size > 8) { /* 8 is 1GB only support 1GB per DIMM */ print_debug("Only support up to 1 GB per DIMM\r\n"); POST_CODE(ERROR_DENSITY_DIMM); __asm__ __volatile__("hlt\n"); } dimm_setting |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;
- /*; Field: PAGE size *; EEPROM byte usage: (4) Number of Column Addresses *; PageSize = 2^# Column Addresses * Data width in bytes (should be 8bytes for a normal DIMM) @@ -116,98 +117,98 @@ POST_CODE(ERROR_SET_PAGE); __asm__ __volatile__("hlt\n"); } - spd_byte -=7; - if (spd_byte > 5){ /* if the value is above 6 it means >12 address lines */ - spd_byte = 7; /* which means >32k so set to disabled */ + spd_byte -= 7; + if (spd_byte > 5) { /* if the value is above 6 it means >12 address lines */ + spd_byte = 7; /* which means >32k so set to disabled */ } - dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0=1k,1=2k,2=4k,etc */ + dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0=1k,1=2k,2=4k,etc */
msr = rdmsr(MC_CF07_DATA); - if (dimm == DIMM0){ + if (dimm == DIMM0) { msr.hi &= 0xFFFF0000; msr.hi |= dimm_setting; - }else{ + } else { msr.hi &= 0x0000FFFF; msr.hi |= dimm_setting << 16; } wrmsr(MC_CF07_DATA, msr); }
- -static void checkDDRMax(void){ +static void checkDDRMax(void) +{ uint8_t spd_byte0, spd_byte1; uint16_t speed;
- /* PC133 identifier */ + /* PC133 identifier */ spd_byte0 = spd_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX); - if (spd_byte0 == 0xFF){ - spd_byte0=0; + if (spd_byte0 == 0xFF) { + spd_byte0 = 0; } spd_byte1 = spd_read_byte(DIMM1, SPD_MIN_CYCLE_TIME_AT_CAS_MAX); - if (spd_byte1 == 0xFF){ - spd_byte1=0; + if (spd_byte1 == 0xFF) { + spd_byte1 = 0; }
/* I don't think you need this check. - if (spd_byte0 < 0xA0 || spd_byte0 < 0xA0){ - print_debug("DIMM overclocked. Check GeodeLink Speed\r\n"); - POST_CODE(POST_PLL_MEM_FAIL); - __asm__ __volatile__("hlt\n"); - }*/ - + if (spd_byte0 < 0xA0 || spd_byte0 < 0xA0){ + print_debug("DIMM overclocked. Check GeodeLink Speed\r\n"); + POST_CODE(POST_PLL_MEM_FAIL); + __asm__ __volatile__("hlt\n"); + } */
/* Use the slowest DIMM */ - if (spd_byte0 < spd_byte1){ + if (spd_byte0 < spd_byte1) { spd_byte0 = spd_byte1; }
/* Turn SPD ns time into MHZ. Check what the asm does to this math. */ - speed = 2*((10000/(((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F)))); + speed = 2 * ((10000 / (((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F))));
/* current speed > max speed? */ - if (GeodeLinkSpeed() > speed){ + if (GeodeLinkSpeed() > speed) { print_debug("DIMM overclocked. Check GeodeLink Speed\r\n"); POST_CODE(POST_PLL_MEM_FAIL); __asm__ __volatile__("hlt\n"); } }
+const uint16_t REF_RATE[] = { 15, 3, 7, 31, 62, 125 }; /* ns */
-const uint16_t REF_RATE[] = {15, 3, 7, 31, 62, 125}; /* ns */ - -static void set_refresh_rate(void){ +static void set_refresh_rate(void) +{ uint8_t spd_byte0, spd_byte1; uint16_t rate0, rate1; msr_t msr;
spd_byte0 = spd_read_byte(DIMM0, SPD_REFRESH); spd_byte0 &= 0xF; - if (spd_byte0 > 5){ + if (spd_byte0 > 5) { spd_byte0 = 5; } rate0 = REF_RATE[spd_byte0];
spd_byte1 = spd_read_byte(DIMM1, SPD_REFRESH); spd_byte1 &= 0xF; - if (spd_byte1 > 5){ + if (spd_byte1 > 5) { spd_byte1 = 5; } rate1 = REF_RATE[spd_byte1];
/* Use the faster rate (lowest number) */ - if (rate0 > rate1){ + if (rate0 > rate1) { rate0 = rate1; }
- msr = rdmsr(MC_CF07_DATA); - msr.lo|= ((rate0 * (GeodeLinkSpeed()/2))/16) << CF07_LOWER_REF_INT_SHIFT; - wrmsr(MC_CF07_DATA, msr); - } - + msr = rdmsr(MC_CF07_DATA); + msr.lo |= + ((rate0 * (GeodeLinkSpeed() / 2)) / 16) << CF07_LOWER_REF_INT_SHIFT; + wrmsr(MC_CF07_DATA, msr); +}
-const uint8_t CASDDR[] = {5, 5, 2, 6, 3, 7, 4, 0}; /* 1(1.5), 1.5, 2, 2.5, 3, 3.5, 4, 0 */ +const uint8_t CASDDR[] = { 5, 5, 2, 6, 3, 7, 4, 0 }; /* 1(1.5), 1.5, 2, 2.5, 3, 3.5, 4, 0 */
-static void setCAS(void){ +static void setCAS(void) +{ /*;***************************************************************************** ;* ;* setCAS @@ -236,226 +237,229 @@
/************************** DIMM0 **********************************/ casmap0 = spd_read_byte(DIMM0, SPD_ACCEPTABLE_CAS_LATENCIES); - if (casmap0 != 0xFF){ + if (casmap0 != 0xFF) { /* IF -.5 timing is supported, check -.5 timing > GeodeLink */ spd_byte = spd_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND); - if(spd_byte != 0){ + if (spd_byte != 0) { /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ - dimm_speed = 2*(10000/(((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); - if (dimm_speed >= glspeed){ + dimm_speed = + 2 * (10000 / + (((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); + if (dimm_speed >= glspeed) { /* IF -1 timing is supported, check -1 timing > GeodeLink */ - spd_byte = spd_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD); - if(spd_byte != 0){ + spd_byte = + spd_read_byte(DIMM0, + SPD_SDRAM_CYCLE_TIME_3RD); + if (spd_byte != 0) { /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ - dimm_speed = 2*(10000/(((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); - if (dimm_speed <= glspeed){ + dimm_speed = + 2 * (10000 / + (((spd_byte >> 4) * 10) + + (spd_byte & 0x0F))); + if (dimm_speed <= glspeed) { /* set we can use -.5 timing but not -1 */ - spd_byte = 31 - __builtin_clz((uint32_t)casmap0); /* just want bits in the lower byte since we have to cast to a 32 */ + spd_byte = 31 - __builtin_clz((uint32_t) casmap0); /* just want bits in the lower byte since we have to cast to a 32 */ casmap0 &= 0xFF << (--spd_byte); } - } /*MIN_CYCLE_10 !=0 */ - } - else{ /* Timing_05 < GLspeed, can't use -.5 or -1 timing */ - spd_byte = 31 - __builtin_clz((uint32_t)casmap0); /* just want bits in the lower byte since we have to cast to a 32 */ + } /*MIN_CYCLE_10 !=0 */ + } else { /* Timing_05 < GLspeed, can't use -.5 or -1 timing */ + spd_byte = 31 - __builtin_clz((uint32_t) casmap0); /* just want bits in the lower byte since we have to cast to a 32 */ casmap0 &= 0xFF << (spd_byte); } - } /*MIN_CYCLE_05 !=0 */ - } - else{ /* No DIMM */ - casmap0=0; + } /*MIN_CYCLE_05 !=0 */ + } else { /* No DIMM */ + casmap0 = 0; }
/************************** DIMM1 **********************************/ casmap1 = spd_read_byte(DIMM1, SPD_ACCEPTABLE_CAS_LATENCIES); - if (casmap1 != 0xFF){ + if (casmap1 != 0xFF) { /* IF -.5 timing is supported, check -.5 timing > GeodeLink */ spd_byte = spd_read_byte(DIMM1, SPD_SDRAM_CYCLE_TIME_2ND); - if(spd_byte != 0){ + if (spd_byte != 0) { /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ - dimm_speed = 2*(10000/(((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); - if (dimm_speed >= glspeed){ + dimm_speed = + 2 * (10000 / + (((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); + if (dimm_speed >= glspeed) { /* IF -1 timing is supported, check -1 timing > GeodeLink */ - spd_byte = spd_read_byte(DIMM1, SPD_SDRAM_CYCLE_TIME_3RD); - if(spd_byte != 0){ + spd_byte = + spd_read_byte(DIMM1, + SPD_SDRAM_CYCLE_TIME_3RD); + if (spd_byte != 0) { /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ - dimm_speed = 2*(10000/(((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); - if (dimm_speed <= glspeed){ + dimm_speed = + 2 * (10000 / + (((spd_byte >> 4) * 10) + + (spd_byte & 0x0F))); + if (dimm_speed <= glspeed) { /* set we can use -.5 timing but not -1 */ - spd_byte =31 - __builtin_clz((uint32_t)casmap1); /* just want bits in the lower byte since we have to cast to a 32 */ + spd_byte = 31 - __builtin_clz((uint32_t) casmap1); /* just want bits in the lower byte since we have to cast to a 32 */ casmap1 &= 0xFF << (--spd_byte); } - } /*MIN_CYCLE_10 !=0 */ - } - else{ /* Timing_05 < GLspeed, can't use -.5 or -1 timing */ - spd_byte = 31 - __builtin_clz((uint32_t)casmap1); /* just want bits in the lower byte since we have to cast to a 32 */ + } /*MIN_CYCLE_10 !=0 */ + } else { /* Timing_05 < GLspeed, can't use -.5 or -1 timing */ + spd_byte = 31 - __builtin_clz((uint32_t) casmap1); /* just want bits in the lower byte since we have to cast to a 32 */ casmap1 &= 0xFF << (spd_byte); } - } /*MIN_CYCLE_05 !=0 */ - } - else{ /* No DIMM */ - casmap1=0; + } /*MIN_CYCLE_05 !=0 */ + } else { /* No DIMM */ + casmap1 = 0; }
/********************* CAS_LAT MAP COMPARE ***************************/ - if (casmap0 == 0){ - spd_byte = CASDDR[__builtin_ctz((uint32_t)casmap1)]; - } - else if (casmap1 == 0){ - spd_byte = CASDDR[__builtin_ctz((uint32_t)casmap0)]; - } - else if ((casmap0 &= casmap1)){ - spd_byte = CASDDR[__builtin_ctz((uint32_t)casmap0)]; - } - else{ + if (casmap0 == 0) { + spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap1)]; + } else if (casmap1 == 0) { + spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap0)]; + } else if ((casmap0 &= casmap1)) { + spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap0)]; + } else { print_debug("DIMM CAS Latencies not compatible\r\n"); POST_CODE(ERROR_DIFF_DIMMS); __asm__ __volatile__("hlt\n"); }
- msr = rdmsr(MC_CF8F_DATA); msr.lo &= ~(7 << CF8F_LOWER_CAS_LAT_SHIFT); msr.lo |= spd_byte << CF8F_LOWER_CAS_LAT_SHIFT; wrmsr(MC_CF8F_DATA, msr); }
- -static void set_latencies(void){ +static void set_latencies(void) +{ uint32_t memspeed, dimm_setting; uint8_t spd_byte0, spd_byte1; msr_t msr;
- memspeed = GeodeLinkSpeed()/2; - dimm_setting=0; + memspeed = GeodeLinkSpeed() / 2; + dimm_setting = 0;
/* MC_CF8F setup */ /* tRAS */ spd_byte0 = spd_read_byte(DIMM0, SPD_tRAS); - if (spd_byte0 == 0xFF){ - spd_byte0=0; + if (spd_byte0 == 0xFF) { + spd_byte0 = 0; } spd_byte1 = spd_read_byte(DIMM1, SPD_tRAS); - if (spd_byte1 == 0xFF){ - spd_byte1=0; + if (spd_byte1 == 0xFF) { + spd_byte1 = 0; } - if (spd_byte0 < spd_byte1){ + if (spd_byte0 < spd_byte1) { spd_byte0 = spd_byte1; }
/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */ - spd_byte1 = (spd_byte0 * memspeed)/1000; - if(((spd_byte0 * memspeed)%1000)){ + spd_byte1 = (spd_byte0 * memspeed) / 1000; + if (((spd_byte0 * memspeed) % 1000)) { ++spd_byte1; } dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2PRE_SHIFT;
- /* tRP */ spd_byte0 = spd_read_byte(DIMM0, SPD_tRP); - if (spd_byte0 == 0xFF){ - spd_byte0=0; + if (spd_byte0 == 0xFF) { + spd_byte0 = 0; } spd_byte1 = spd_read_byte(DIMM1, SPD_tRP); - if (spd_byte1 == 0xFF){ - spd_byte1=0; + if (spd_byte1 == 0xFF) { + spd_byte1 = 0; } - if (spd_byte0 < spd_byte1){ + if (spd_byte0 < spd_byte1) { spd_byte0 = spd_byte1; }
/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */ - spd_byte1 = ((spd_byte0 >> 2) * memspeed)/1000; - if((((spd_byte0 >> 2) * memspeed)%1000)){ + spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000; + if ((((spd_byte0 >> 2) * memspeed) % 1000)) { ++spd_byte1; } dimm_setting |= spd_byte1 << CF8F_LOWER_PRE2ACT_SHIFT;
- /* tRCD */ spd_byte0 = spd_read_byte(DIMM0, SPD_tRCD); - if (spd_byte0 == 0xFF){ - spd_byte0=0; + if (spd_byte0 == 0xFF) { + spd_byte0 = 0; } spd_byte1 = spd_read_byte(DIMM1, SPD_tRCD); - if (spd_byte1 == 0xFF){ - spd_byte1=0; + if (spd_byte1 == 0xFF) { + spd_byte1 = 0; } - if (spd_byte0 < spd_byte1){ + if (spd_byte0 < spd_byte1) { spd_byte0 = spd_byte1; }
/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */ - spd_byte1 = ((spd_byte0 >> 2) * memspeed)/1000; - if((((spd_byte0 >> 2) * memspeed)%1000)){ + spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000; + if ((((spd_byte0 >> 2) * memspeed) % 1000)) { ++spd_byte1; } dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2CMD_SHIFT;
- /* tRRD */ spd_byte0 = spd_read_byte(DIMM0, SPD_tRRD); - if (spd_byte0 == 0xFF){ - spd_byte0=0; + if (spd_byte0 == 0xFF) { + spd_byte0 = 0; } spd_byte1 = spd_read_byte(DIMM1, SPD_tRRD); - if (spd_byte1 == 0xFF){ - spd_byte1=0; + if (spd_byte1 == 0xFF) { + spd_byte1 = 0; } - if (spd_byte0 < spd_byte1){ + if (spd_byte0 < spd_byte1) { spd_byte0 = spd_byte1; }
/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */ - spd_byte1 = ((spd_byte0 >> 2) * memspeed)/1000; - if((((spd_byte0 >> 2) * memspeed)%1000)){ + spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000; + if ((((spd_byte0 >> 2) * memspeed) % 1000)) { ++spd_byte1; } dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2ACT_SHIFT;
- /* tRC = tRP + tRAS */ - dimm_setting |= (((dimm_setting >> CF8F_LOWER_ACT2PRE_SHIFT) & 0x0F) + ((dimm_setting >> CF8F_LOWER_PRE2ACT_SHIFT) & 0x07)) \ - << CF8F_LOWER_ACT2ACTREF_SHIFT; - + dimm_setting |= + (((dimm_setting >> CF8F_LOWER_ACT2PRE_SHIFT) & 0x0F) + + ((dimm_setting >> CF8F_LOWER_PRE2ACT_SHIFT) & 0x07)) + << CF8F_LOWER_ACT2ACTREF_SHIFT;
msr = rdmsr(MC_CF8F_DATA); msr.lo &= 0xF00000FF; msr.lo |= dimm_setting; - msr.hi |= CF8F_UPPER_REORDER_DIS_SET; + msr.hi |= CF8F_UPPER_REORDER_DIS_SET; wrmsr(MC_CF8F_DATA, msr);
/* MC_CF1017 setup */ /* tRFC */ spd_byte0 = spd_read_byte(DIMM0, SPD_tRFC); - if (spd_byte0 == 0xFF){ - spd_byte0=0; + if (spd_byte0 == 0xFF) { + spd_byte0 = 0; } spd_byte1 = spd_read_byte(DIMM1, SPD_tRFC); - if (spd_byte1 == 0xFF){ - spd_byte1=0; + if (spd_byte1 == 0xFF) { + spd_byte1 = 0; } - if (spd_byte0 < spd_byte1){ + if (spd_byte0 < spd_byte1) { spd_byte0 = spd_byte1; }
- if (spd_byte0){ + if (spd_byte0) { /* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */ - spd_byte1 = (spd_byte0 * memspeed)/1000; - if(((spd_byte0 * memspeed)%1000)){ + spd_byte1 = (spd_byte0 * memspeed) / 1000; + if (((spd_byte0 * memspeed) % 1000)) { ++spd_byte1; } + } else { /* Not all SPDs have tRFC setting. Use this formula tRFC = tRC + 1 clk */ + spd_byte1 = + ((dimm_setting >> CF8F_LOWER_ACT2ACTREF_SHIFT) & 0x0F) + 1; } - else{ /* Not all SPDs have tRFC setting. Use this formula tRFC = tRC + 1 clk */ - spd_byte1 = ((dimm_setting >> CF8F_LOWER_ACT2ACTREF_SHIFT) & 0x0F) + 1; - } - dimm_setting = spd_byte1 << CF1017_LOWER_REF2ACT_SHIFT; /* note this clears the cf8f dimm setting */ + dimm_setting = spd_byte1 << CF1017_LOWER_REF2ACT_SHIFT; /* note this clears the cf8f dimm setting */ msr = rdmsr(MC_CF1017_DATA); msr.lo &= ~(0x1F << CF1017_LOWER_REF2ACT_SHIFT); msr.lo |= dimm_setting; wrmsr(MC_CF1017_DATA, msr);
/* tWTR: Set tWTR to 2 for 400MHz and above GLBUS (200Mhz mem) other wise it stay default(1) */ - if (memspeed > 198){ + if (memspeed > 198) { msr = rdmsr(MC_CF1017_DATA); msr.lo &= ~(0x7 << CF1017_LOWER_WR_TO_RD_SHIFT); msr.lo |= 2 << CF1017_LOWER_WR_TO_RD_SHIFT; @@ -463,41 +467,45 @@ } }
-static void set_extended_mode_registers(void){ +static void set_extended_mode_registers(void) +{ uint8_t spd_byte0, spd_byte1; msr_t msr; spd_byte0 = spd_read_byte(DIMM0, SPD_DEVICE_ATTRIBUTES_GENERAL); - if (spd_byte0 == 0xFF){ - spd_byte0=0; + if (spd_byte0 == 0xFF) { + spd_byte0 = 0; } spd_byte1 = spd_read_byte(DIMM1, SPD_DEVICE_ATTRIBUTES_GENERAL); - if (spd_byte1 == 0xFF){ - spd_byte1=0; + if (spd_byte1 == 0xFF) { + spd_byte1 = 0; } spd_byte1 &= spd_byte0;
msr = rdmsr(MC_CF07_DATA); - if (spd_byte1 & 1){ /* Drive Strength Control */ + if (spd_byte1 & 1) { /* Drive Strength Control */ msr.lo |= CF07_LOWER_EMR_DRV_SET; } - if (spd_byte1 & 2){ /* FET Control */ + if (spd_byte1 & 2) { /* FET Control */ msr.lo |= CF07_LOWER_EMR_QFC_SET; } wrmsr(MC_CF07_DATA, msr); }
-static void EnableMTest (void){ +static void EnableMTest(void) +{ msr_t msr;
msr = rdmsr(GLCP_DELAY_CONTROLS); - msr.hi &= ~(7 << 20); /* clear bits 54:52 */ - if (GeodeLinkSpeed() < 200){ + msr.hi &= ~(7 << 20); /* clear bits 54:52 */ + if (GeodeLinkSpeed() < 200) { msr.hi |= 2 << 20; } wrmsr(GLCP_DELAY_CONTROLS, msr);
msr = rdmsr(MC_CFCLK_DBUG); - msr.hi |= CFCLK_UPPER_MTST_B2B_DIS_SET | CFCLK_UPPER_MTEST_EN_SET | CFCLK_UPPER_MTST_RBEX_EN_SET; + msr.hi |= + CFCLK_UPPER_MTST_B2B_DIS_SET | CFCLK_UPPER_MTEST_EN_SET | + CFCLK_UPPER_MTST_RBEX_EN_SET; msr.lo |= CFCLK_LOWER_TRISTATE_DIS_SET; wrmsr(MC_CFCLK_DBUG, msr);
@@ -513,10 +521,9 @@ msrnum = MC_CF1017_DATA; msr = rdmsr(msrnum); msr.lo &= ~(7 << CF1017_LOWER_RD_TMG_CTL_SHIFT); - if (GeodeLinkSpeed() < 334){ + if (GeodeLinkSpeed() < 334) { msr.lo |= (3 << CF1017_LOWER_RD_TMG_CTL_SHIFT); - } - else{ + } else { msr.lo |= (4 << CF1017_LOWER_RD_TMG_CTL_SHIFT); } wrmsr(msrnum, msr); @@ -525,50 +532,49 @@ msrnum = MC_CF07_DATA; msr = rdmsr(msrnum); msr.lo &= ~0xF0; - msr.lo |= 0x40; /* set refresh to 4SDRAM clocks */ + msr.lo |= 0x40; /* set refresh to 4SDRAM clocks */ wrmsr(msrnum, msr);
/* Memory Interleave: Set HOI here otherwise default is LOI */ /* msrnum = MC_CF8F_DATA; - msr = rdmsr(msrnum); - msr.hi |= CF8F_UPPER_HOI_LOI_SET; - wrmsr(msrnum, msr); */ + msr = rdmsr(msrnum); + msr.hi |= CF8F_UPPER_HOI_LOI_SET; + wrmsr(msrnum, msr); */ }
- static void sdram_set_spd_registers(const struct mem_controller *ctrl) { uint8_t spd_byte;
- POST_CODE(POST_MEM_SETUP); // post_70h + POST_CODE(POST_MEM_SETUP); // post_70h
spd_byte = spd_read_byte(DIMM0, SPD_MODULE_ATTRIBUTES); /* Check DIMM is not Register and not Buffered DIMMs. */ - if ((spd_byte != 0xFF) && (spd_byte & 3) ){ + if ((spd_byte != 0xFF) && (spd_byte & 3)) { print_debug("DIMM0 NOT COMPATIBLE\r\n"); POST_CODE(ERROR_UNSUPPORTED_DIMM); __asm__ __volatile__("hlt\n"); } spd_byte = spd_read_byte(DIMM1, SPD_MODULE_ATTRIBUTES); - if ((spd_byte != 0xFF) && (spd_byte & 3)){ + if ((spd_byte != 0xFF) && (spd_byte & 3)) { print_debug("DIMM1 NOT COMPATIBLE\r\n"); POST_CODE(ERROR_UNSUPPORTED_DIMM); __asm__ __volatile__("hlt\n"); }
- POST_CODE(POST_MEM_SETUP2); // post_72h + POST_CODE(POST_MEM_SETUP2); // post_72h
/* Check that the memory is not overclocked. */ checkDDRMax();
/* Size the DIMMS */ - POST_CODE(POST_MEM_SETUP3); // post_73h + POST_CODE(POST_MEM_SETUP3); // post_73h auto_size_dimm(DIMM0); - POST_CODE(POST_MEM_SETUP4); // post_74h + POST_CODE(POST_MEM_SETUP4); // post_74h auto_size_dimm(DIMM1);
/* Set CAS latency */ - POST_CODE(POST_MEM_SETUP5); // post_75h + POST_CODE(POST_MEM_SETUP5); // post_75h setCAS();
/* Set all the other latencies here (tRAS, tRP....) */ @@ -601,65 +607,62 @@ ;* 9) MRS w/ memory config & reset DLL clear ;* 8) DDR SDRAM ready for normal operation ;********************************************************************/ - POST_CODE(POST_MEM_ENABLE); // post_76h + POST_CODE(POST_MEM_ENABLE); // post_76h
/* Only enable MTest for TLA memory debug */ - /*EnableMTest();*/ + /*EnableMTest(); */
/* If both Page Size = "Not Installed" we have a problems and should halt. */ msr = rdmsr(MC_CF07_DATA); - if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) \ - == ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))){ + if ((msr. + hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | + (7 << CF07_UPPER_D0_PSZ_SHIFT))) + == ((7 << CF07_UPPER_D1_PSZ_SHIFT) | + (7 << CF07_UPPER_D0_PSZ_SHIFT))) { print_debug("No memory in the system\r\n"); POST_CODE(ERROR_NO_DIMMS); __asm__ __volatile__("hlt\n"); }
- /* Set CKEs */ + /* Set CKEs */ msrnum = MC_CFCLK_DBUG; msr = rdmsr(msrnum); msr.lo &= ~(CFCLK_LOWER_MASK_CKE_SET0 | CFCLK_LOWER_MASK_CKE_SET1); wrmsr(msrnum, msr);
- /* Force Precharge All on next command, EMRS */ msrnum = MC_CFCLK_DBUG; msr = rdmsr(msrnum); msr.lo |= CFCLK_LOWER_FORCE_PRE_SET; - wrmsr(msrnum,msr); - + wrmsr(msrnum, msr);
/* EMRS to enable DLL (pre-setup done in setExtendedModeRegisters) */ - msrnum = MC_CF07_DATA; + msrnum = MC_CF07_DATA; msr = rdmsr(msrnum); msr.lo |= CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DDR_SET; wrmsr(msrnum, msr); msr.lo &= ~(CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DDR_SET); wrmsr(msrnum, msr);
- /* Clear Force Precharge All */ msrnum = MC_CFCLK_DBUG; msr = rdmsr(msrnum); msr.lo &= ~CFCLK_LOWER_FORCE_PRE_SET; wrmsr(msrnum, msr);
- /* MRS Reset DLL - set */ msrnum = MC_CF07_DATA; msr = rdmsr(msrnum); msr.lo |= CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DLL_RESET; - wrmsr(msrnum,msr); + wrmsr(msrnum, msr); msr.lo &= ~(CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DLL_RESET); wrmsr(msrnum, msr);
- /* 2us delay (200 clocks @ 200Mhz). We probably really don't need this but.... better safe. */ /* Wait 2 PORT61 ticks. between 15us and 30us */ /* This would be endless if the timer is stuck. */ - while ((inb(0x61))); /* find the first edge */ - while (!(~inb(0x61))); - + while ((inb(0x61))) ; /* find the first edge */ + while (!(~inb(0x61))) ;
/* Force Precharge All on the next command, auto-refresh */ msrnum = MC_CFCLK_DBUG; @@ -667,7 +670,6 @@ msr.lo |= CFCLK_LOWER_FORCE_PRE_SET; wrmsr(msrnum, msr);
- /* Manually AUTO refresh #1 */ /* If auto refresh was not enabled above we would need to do 8 refreshes to prime the pump before these 2. */ msrnum = MC_CF07_DATA; @@ -683,7 +685,6 @@ msr.lo &= ~CFCLK_LOWER_FORCE_PRE_SET; wrmsr(msrnum, msr);
- /* Manually AUTO refresh */ /* The MC should insert the right delay between the refreshes */ msrnum = MC_CF07_DATA; @@ -693,7 +694,6 @@ msr.lo &= ~CF07_LOWER_REF_TEST_SET; wrmsr(msrnum, msr);
- /* MRS Reset DLL - clear */ msrnum = MC_CF07_DATA; msr = rdmsr(msrnum); @@ -702,17 +702,16 @@ msr.lo &= ~CF07_LOWER_PROG_DRAM_SET; wrmsr(msrnum, msr);
- /* Allow MC to tristate during idle cycles with MTEST OFF */ msrnum = MC_CFCLK_DBUG; msr = rdmsr(msrnum); msr.lo &= ~CFCLK_LOWER_TRISTATE_DIS_SET; wrmsr(msrnum, msr);
- /* Disable SDCLK DIMM1 slot if no DIMM installed to save power. */ msr = rdmsr(MC_CF07_DATA); - if ((msr.hi & (7 << CF07_UPPER_D1_PSZ_SHIFT)) == (7 << CF07_UPPER_D1_PSZ_SHIFT)){ + if ((msr.hi & (7 << CF07_UPPER_D1_PSZ_SHIFT)) == + (7 << CF07_UPPER_D1_PSZ_SHIFT)) { msrnum = GLCP_DELAY_CONTROLS; msr = rdmsr(msrnum); msr.hi |= (1 << 23); /* SDCLK bit for 2.0 */ @@ -720,11 +719,10 @@ }
/* Set PMode0 Sensitivity Counter */ - msr.lo = 0; /* pmode 0=0 most aggressive */ + msr.lo = 0; /* pmode 0=0 most aggressive */ msr.hi = 0x200; /* pmode 1=200h */ wrmsr(MC_CF_PMCTR, msr);
- /* Set PMode1 Up delay enable */ msrnum = MC_CF1017_DATA; msr = rdmsr(msrnum); @@ -732,15 +730,15 @@ wrmsr(msrnum, msr);
print_debug("DRAM controller init done.\r\n"); - POST_CODE(POST_MEM_SETUP_GOOD); //0x7E + POST_CODE(POST_MEM_SETUP_GOOD); //0x7E
/* make sure there is nothing stale in the cache */ - /* CAR stack is in the cache __asm__ __volatile__("wbinvd\n");*/ + /* CAR stack is in the cache __asm__ __volatile__("wbinvd\n"); */
/* The RAM dll needs a write to lock on so generate a few dummy writes */ /* Note: The descriptor needs to be enabled to point at memory */ volatile unsigned long *ptr; - for (i=0;i<5;i++) { + for (i = 0; i < 5; i++) { ptr = (void *)i; *ptr = (unsigned long)i; } @@ -751,19 +749,18 @@ if ((msr.lo & 0x7FF) == 0x104) {
/* If you had it you would need to clear out the fail boot count flag */ - /* (depending on where it counts from etc).*/ + /* (depending on where it counts from etc). */
/* The reset we are about to perform clears the PM_SSC register in the */ - /* 5536 so will need to store the S3 resume flag in NVRAM otherwise */ - /* it would do a normal boot */ + /* 5536 so will need to store the S3 resume flag in NVRAM otherwise */ + /* it would do a normal boot */
/* Reset the system */ msrnum = MDD_SOFT_RESET; msr = rdmsr(msrnum); msr.lo |= 1; wrmsr(msrnum, msr); -} + } print_debug("RAM DLL lock\r\n");
- } Index: LinuxBIOSv2/src/northbridge/amd/lx/northbridge.h =================================================================== --- LinuxBIOSv2.orig/src/northbridge/amd/lx/northbridge.h 2007-05-04 13:44:14.000000000 -0600 +++ LinuxBIOSv2/src/northbridge/amd/lx/northbridge.h 2007-05-04 13:44:16.000000000 -0600 @@ -24,4 +24,4 @@ extern unsigned int lx_scan_root_bus(device_t root, unsigned int max); int sizeram(void);
-#endif /* NORTHBRIDGE_AMD_LX_H */ +#endif /* NORTHBRIDGE_AMD_LX_H */ Index: LinuxBIOSv2/src/northbridge/amd/lx/raminit.h =================================================================== --- LinuxBIOSv2.orig/src/northbridge/amd/lx/raminit.h 2007-05-04 13:44:14.000000000 -0600 +++ LinuxBIOSv2/src/northbridge/amd/lx/raminit.h 2007-05-04 13:44:16.000000000 -0600 @@ -27,4 +27,4 @@ uint16_t channel0[DIMM_SOCKETS]; };
-#endif /* RAMINIT_H */ +#endif /* RAMINIT_H */
-- Jordan Crouse Senior Linux Engineer Advanced Micro Devices, Inc. <www.amd.com/embeddedprocessors>
Fix the indent and whitespace to match LinuxBIOS standards
Signed-off-by: Jordan Crouse jordan.crouse@amd.com
Index: LinuxBIOSv2/src/cpu/amd/model_lx/cpubug.c =================================================================== --- LinuxBIOSv2.orig/src/cpu/amd/model_lx/cpubug.c 2007-05-04 12:58:36.000000000 -0600 +++ LinuxBIOSv2/src/cpu/amd/model_lx/cpubug.c 2007-05-04 12:58:48.000000000 -0600 @@ -30,7 +30,6 @@ #include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h>
- /************************************************************************** * * pcideadlock @@ -40,27 +39,27 @@ * There is also fix code in cache and PCI functions. This bug is very is pervasive. * **************************************************************************/ -static void pcideadlock(void){ +static void pcideadlock(void) +{ msr_t msr;
/* * forces serialization of all load misses. Setting this bit prevents the * DM pipe from backing up if a read request has to be held up waiting * for PCI writes to complete. - */ + */ msr = rdmsr(CPU_DM_CONFIG0); msr.lo |= DM_CONFIG0_LOWER_MISSER_SET; wrmsr(CPU_DM_CONFIG0, msr);
- /* write serialize memory hole to PCI. Need to unWS when something is * shadowed regardless of cachablility. */ msr.lo = 0x021212121; msr.hi = 0x021212121; - wrmsr( CPU_RCONF_A0_BF, msr); - wrmsr( CPU_RCONF_C0_DF, msr); - wrmsr( CPU_RCONF_E0_FF, msr); + wrmsr(CPU_RCONF_A0_BF, msr); + wrmsr(CPU_RCONF_C0_DF, msr); + wrmsr(CPU_RCONF_E0_FF, msr); }
/****************************************************************************/ @@ -74,17 +73,19 @@ /** to maintain coherency with and the cache is not enabled yet.*/ /***/ /****************************************************************************/ -static void disablememoryreadorder(void){ +static void disablememoryreadorder(void) +{ msr_t msr;
msr = rdmsr(MC_CF8F_DATA); - msr.hi |= CF8F_UPPER_REORDER_DIS_SET; + msr.hi |= CF8F_UPPER_REORDER_DIS_SET; wrmsr(MC_CF8F_DATA, msr); }
/* For cpu version C3. Should be the only released version */ -void cpubug(void) { - pcideadlock(); +void cpubug(void) +{ + pcideadlock(); disablememoryreadorder(); printk_debug("Done cpubug fixes \n"); } Index: LinuxBIOSv2/src/cpu/amd/model_lx/cpureginit.c =================================================================== --- LinuxBIOSv2.orig/src/cpu/amd/model_lx/cpureginit.c 2007-05-04 12:58:36.000000000 -0600 +++ LinuxBIOSv2/src/cpu/amd/model_lx/cpureginit.c 2007-05-04 12:58:48.000000000 -0600 @@ -25,7 +25,8 @@ ;* SetDelayControl ;* ;*************************************************************************/ -void SetDelayControl(void){ +void SetDelayControl(void) +{ unsigned int msrnum, glspeed; unsigned char spdbyte0, spdbyte1; msr_t msr; @@ -37,7 +38,7 @@ msr.hi = 0; msr.lo = 0x2814D352; wrmsr(msrnum, msr); - + msrnum = CPU_BC_MSS_ARRAY_CTL1; msr.hi = 0; msr.lo = 0x1068334D; @@ -46,8 +47,8 @@ msrnum = CPU_BC_MSS_ARRAY_CTL2; msr.hi = 0x00000106; msr.lo = 0x83104104; - wrmsr(msrnum,msr); - + wrmsr(msrnum, msr); + msrnum = GLCP_FIFOCTL; msr = rdmsr(msrnum); msr.hi = 0x00000005; @@ -59,39 +60,37 @@ msr.lo = 0x00000001; wrmsr(msrnum, msr);
- /* Debug Delay Control Setup Check - Leave it alone if it has been setup. FS2 or something is here.*/ + Leave it alone if it has been setup. FS2 or something is here. */ msrnum = GLCP_DELAY_CONTROLS; msr = rdmsr(msrnum); - if (msr.lo & ~(0x7C0)){ + if (msr.lo & ~(0x7C0)) { return; }
- /* - ; Delay Controls based on DIMM loading. UGH! - ; # of Devices = Module Width (SPD6) / Device Width(SPD13) * Physical Banks(SPD5) - ; Note - We only support module width of 64. - */ + ; Delay Controls based on DIMM loading. UGH! + ; # of Devices = Module Width (SPD6) / Device Width(SPD13) * Physical Banks(SPD5) + ; Note - We only support module width of 64. + */ spdbyte0 = spd_read_byte(DIMM0, SPD_PRIMARY_SDRAM_WIDTH); - if (spdbyte0 !=0xFF){ - spdbyte0 = (unsigned char) 64/spdbyte0 * (unsigned char) (spd_read_byte(DIMM0, SPD_NUM_DIMM_BANKS)); - } - else{ - spdbyte0=0; + if (spdbyte0 != 0xFF) { + spdbyte0 = + (unsigned char)64 / spdbyte0 * + (unsigned char)(spd_read_byte(DIMM0, SPD_NUM_DIMM_BANKS)); + } else { + spdbyte0 = 0; }
spdbyte1 = spd_read_byte(DIMM1, SPD_PRIMARY_SDRAM_WIDTH); - if (spdbyte1 !=0xFF){ - spdbyte1 = (unsigned char) 64/spdbyte1 * (unsigned char) (spd_read_byte(DIMM1, SPD_NUM_DIMM_BANKS)); - } - else{ - spdbyte1=0; + if (spdbyte1 != 0xFF) { + spdbyte1 = + (unsigned char)64 / spdbyte1 * + (unsigned char)(spd_read_byte(DIMM1, SPD_NUM_DIMM_BANKS)); + } else { + spdbyte1 = 0; }
- - /* The current thinking. Subject to change...
; "FUTURE ROBUSTNESS" PROPOSAL @@ -141,117 +140,104 @@ */ msr.hi = msr.lo = 0;
- if (spdbyte0 == 0 || spdbyte1 == 0){ + if (spdbyte0 == 0 || spdbyte1 == 0) { /* one dimm solution */ - if (spdbyte1 == 0){ + if (spdbyte1 == 0) { msr.hi |= 0x000800000; } spdbyte0 += spdbyte1; - if (spdbyte0 > 8){ + if (spdbyte0 > 8) { /* large dimm */ - if (glspeed < 334){ + if (glspeed < 334) { msr.hi |= 0x0837100AA; msr.lo |= 0x056960004; - } - else{ + } else { msr.hi |= 0x082710055; msr.lo |= 0x056960004; } - } - else if (spdbyte0 > 4){ + } else if (spdbyte0 > 4) { /* medium dimm */ - if (glspeed < 334){ + if (glspeed < 334) { msr.hi |= 0x0837100AA; msr.lo |= 0x056960004; - } - else{ + } else { msr.hi |= 0x0827100AA; msr.lo |= 0x056960004; } - } - else{ + } else { /* small dimm */ - if (glspeed < 334){ + if (glspeed < 334) { msr.hi |= 0x0837100FF; msr.lo |= 0x056960004; - } - else{ + } else { msr.hi |= 0x0827100FF; msr.lo |= 0x056960004; } } - } - else{ + } else { /* two dimm solution */ spdbyte0 += spdbyte1; - if (spdbyte0 > 24){ + if (spdbyte0 > 24) { /* huge dimms */ - if (glspeed < 334){ + if (glspeed < 334) { msr.hi |= 0x0B37100A5; msr.lo |= 0x056960004; - } - else{ + } else { msr.hi |= 0x0B2710000; msr.lo |= 0x056960004; } - } - else if (spdbyte0 > 16){ + } else if (spdbyte0 > 16) { /* large dimms */ - if (glspeed < 334){ + if (glspeed < 334) { msr.hi |= 0x0B37100A5; msr.lo |= 0x056960004; - } - else{ + } else { msr.hi |= 0x0B27100A5; msr.lo |= 0x056960004; } - } - else if (spdbyte0 >= 8){ + } else if (spdbyte0 >= 8) { /* medium dimms */ - if (glspeed < 334){ + if (glspeed < 334) { msr.hi |= 0x0937100A5; msr.lo |= 0x056960004; - } - else{ + } else { msr.hi |= 0x0C27100A5; msr.lo |= 0x056960004; } - } - else{ + } else { /* small dimms */ - if (glspeed < 334){ + if (glspeed < 334) { msr.hi |= 0x0837100A5; msr.lo |= 0x056960004; - } - else{ + } else { msr.hi |= 0x082710000; msr.lo |= 0x056960004; } } } - wrmsr(GLCP_DELAY_CONTROLS,msr); + wrmsr(GLCP_DELAY_CONTROLS, msr); return; }
/* ***************************************************************************/ /* * cpuRegInit*/ /* ***************************************************************************/ -void -cpuRegInit (void){ +void cpuRegInit(void) +{ int msrnum; msr_t msr; - + /* Castle 2.0 BTM periodic sync period. */ - /* [40:37] 1 sync record per 256 bytes */ + /* [40:37] 1 sync record per 256 bytes */ msrnum = CPU_PF_CONF; msr = rdmsr(msrnum); msr.hi |= (0x8 << 5); wrmsr(msrnum, msr);
/* - ; Castle performance setting. - ; Enable Quack for fewer re-RAS on the MC - */ + ; Castle performance setting. + ; Enable Quack for fewer re-RAS on the MC + */ msrnum = GLIU0_ARB; msr = rdmsr(msrnum); msr.hi &= ~ARB_UPPER_DACK_EN_SET; @@ -264,7 +250,7 @@ msr.hi |= ARB_UPPER_QUACK_EN_SET; wrmsr(msrnum, msr);
- /* GLIU port active enable, limit south pole masters (AES and PCI) to one outstanding transaction. */ + /* GLIU port active enable, limit south pole masters (AES and PCI) to one outstanding transaction. */ msrnum = GLIU1_PORT_ACTIVE; msr = rdmsr(msrnum); msr.lo &= ~0x880; @@ -277,32 +263,30 @@ msrnum = CPU_AC_SMM_CTL; msr = rdmsr(msrnum); msr.lo |= SMM_INST_EN_SET; - wrmsr(msrnum, msr); - + wrmsr(msrnum, msr);
/* FPU imprecise exceptions bit */ - msrnum = CPU_FPU_MSR_MODE; - msr = rdmsr(msrnum); - msr.lo |= FPU_IE_SET; - wrmsr(msrnum, msr); - + msrnum = CPU_FPU_MSR_MODE; + msr = rdmsr(msrnum); + msr.lo |= FPU_IE_SET; + wrmsr(msrnum, msr);
/* Power Savers (Do after BIST) */ - /* Enable Suspend on HLT & PAUSE instructions*/ + /* Enable Suspend on HLT & PAUSE instructions */ msrnum = CPU_XC_CONFIG; - msr = rdmsr(msrnum); - msr.lo |= XC_CONFIG_SUSP_ON_HLT | XC_CONFIG_SUSP_ON_PAUSE; - wrmsr(msrnum, msr); + msr = rdmsr(msrnum); + msr.lo |= XC_CONFIG_SUSP_ON_HLT | XC_CONFIG_SUSP_ON_PAUSE; + wrmsr(msrnum, msr);
/* Enable SUSP and allow TSC to run in Suspend (keep speed detection happy) */ msrnum = CPU_BC_CONF_0; - msr = rdmsr(msrnum); + msr = rdmsr(msrnum); msr.lo |= TSC_SUSP_SET | SUSP_EN_SET; msr.lo &= 0x0F0FFFFFF; - msr.lo |= 0x002000000; /* PBZ213: Set PAUSEDLY = 2 */ - wrmsr(msrnum, msr); + msr.lo |= 0x002000000; /* PBZ213: Set PAUSEDLY = 2 */ + wrmsr(msrnum, msr);
- /* Disable the debug clock to save power.*/ + /* Disable the debug clock to save power. */ /* NOTE: leave it enabled for fs2 debug */ /* msrnum = GLCP_DBGCLKCTL; msr.hi = 0; @@ -314,5 +298,5 @@ msrnum = GLCP_TH_OD; msr.hi = 0; msr.lo = 0x00000603C; - wrmsr(msrnum, msr); - } + wrmsr(msrnum, msr); +} Index: LinuxBIOSv2/src/cpu/amd/model_lx/model_lx_init.c =================================================================== --- LinuxBIOSv2.orig/src/cpu/amd/model_lx/model_lx_init.c 2007-05-04 12:58:36.000000000 -0600 +++ LinuxBIOSv2/src/cpu/amd/model_lx/model_lx_init.c 2007-05-04 12:58:48.000000000 -0600 @@ -33,12 +33,9 @@
static void vsm_end_post_smi(void) { - __asm__ volatile ( - "push %ax\n" + __asm__ volatile ("push %ax\n" "mov $0x5000, %ax\n" - ".byte 0x0f, 0x38\n" - "pop %ax\n" - ); + ".byte 0x0f, 0x38\n" "pop %ax\n"); }
static void model_lx_init(device_t dev) @@ -55,23 +52,23 @@ vsm_end_post_smi();
// Set gate A20 (legacy vsm disables it in late init) - printk_debug("A20 (0x92): %d\n",inb(0x92)); - outb(0x02,0x92); - printk_debug("A20 (0x92): %d\n",inb(0x92)); + printk_debug("A20 (0x92): %d\n", inb(0x92)); + outb(0x02, 0x92); + printk_debug("A20 (0x92): %d\n", inb(0x92));
printk_debug("CPU model_lx_init DONE\n"); };
static struct device_operations cpu_dev_ops = { - .init = model_lx_init, + .init = model_lx_init, };
static struct cpu_device_id cpu_table[] = { - { X86_VENDOR_AMD, 0x05A2 }, - { 0, 0 }, + {X86_VENDOR_AMD, 0x05A2}, + {0, 0}, };
static struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; Index: LinuxBIOSv2/src/cpu/amd/model_lx/syspreinit.c =================================================================== --- LinuxBIOSv2.orig/src/cpu/amd/model_lx/syspreinit.c 2007-05-04 12:58:36.000000000 -0600 +++ LinuxBIOSv2/src/cpu/amd/model_lx/syspreinit.c 2007-05-04 12:58:48.000000000 -0600 @@ -29,14 +29,14 @@ /* * Destroys: Al,*/ /* **/ /* ***************************************************************************/ -void -StartTimer1(void){ +void StartTimer1(void) +{ outb(0x56, 0x43); outb(0x12, 0x41); }
-void -SystemPreInit(void){ +void SystemPreInit(void) +{
/* they want a jump ... */ #ifndef USE_DCACHE_RAM Index: LinuxBIOSv2/src/cpu/amd/model_lx/vsmsetup.c =================================================================== --- LinuxBIOSv2.orig/src/cpu/amd/model_lx/vsmsetup.c 2007-05-04 12:58:36.000000000 -0600 +++ LinuxBIOSv2/src/cpu/amd/model_lx/vsmsetup.c 2007-05-04 13:01:05.000000000 -0600 @@ -74,8 +74,8 @@ * *--------------------------------------------------------------------*/
-/* Modified to be a self sufficient plug in so that it can be used - without reliance on other parts of core Linuxbios +/* Modified to be a self sufficient plug in so that it can be used + without reliance on other parts of core Linuxbios (C) 2005 Nick.Barker9@btinternet.com
Used initially for epia-m where there are problems getting the bios @@ -84,172 +84,146 @@
/* Declare a temporary global descriptor table - necessary because the Core part of the bios no longer sets up any 16 bit segments */ -__asm__ ( - /* pointer to original gdt */ - "gdtarg: \n" - " .word gdt_limit \n" - " .long gdt \n" - - /* compute the table limit */ - "__mygdt_limit = __mygdt_end - __mygdt - 1 \n" - - "__mygdtaddr: \n" - " .word __mygdt_limit \n" - " .long __mygdt \n" - - "__mygdt: \n" - /* selgdt 0, unused */ - " .word 0x0000, 0x0000 \n" - " .byte 0x00, 0x00, 0x00, 0x00 \n" - - /* selgdt 8, unused */ - " .word 0x0000, 0x0000 \n" - " .byte 0x00, 0x00, 0x00, 0x00 \n" - - /* selgdt 0x10, flat code segment */ - " .word 0xffff, 0x0000 \n" - " .byte 0x00, 0x9b, 0xcf, 0x00 \n" - - /* selgdt 0x18, flat data segment */ - " .word 0xffff, 0x0000 \n" - " .byte 0x00, 0x93, 0xcf, 0x00 \n" - - /* selgdt 0x20, unused */ - " .word 0x0000, 0x0000 \n" - " .byte 0x00, 0x00, 0x00, 0x00 \n" - - /* selgdt 0x28 16-bit 64k code at 0x00000000 */ - " .word 0xffff, 0x0000 \n" - " .byte 0, 0x9a, 0, 0 \n" - - /* selgdt 0x30 16-bit 64k data at 0x00000000 */ - " .word 0xffff, 0x0000 \n" - " .byte 0, 0x92, 0, 0 \n" - - "__mygdt_end: \n" -); +__asm__( + /* pointer to original gdt */ + "gdtarg: \n" + " .word gdt_limit \n" + " .long gdt \n" + /* compute the table limit */ + "__mygdt_limit = __mygdt_end - __mygdt - 1 \n" + "__mygdtaddr: \n" + " .word __mygdt_limit \n" + " .long __mygdt \n" + "__mygdt: \n" + /* selgdt 0, unused */ + " .word 0x0000, 0x0000 \n" + " .byte 0x00, 0x00, 0x00, 0x00 \n" + /* selgdt 8, unused */ + " .word 0x0000, 0x0000 \n" + " .byte 0x00, 0x00, 0x00, 0x00 \n" + /* selgdt 0x10, flat code segment */ + " .word 0xffff, 0x0000 \n" + " .byte 0x00, 0x9b, 0xcf, 0x00 \n" + /* selgdt 0x18, flat data segment */ + " .word 0xffff, 0x0000 \n" + " .byte 0x00, 0x93, 0xcf, 0x00 \n" + /* selgdt 0x20, unused */ + " .word 0x0000, 0x0000 \n" + " .byte 0x00, 0x00, 0x00, 0x00 \n" + /* selgdt 0x28 16-bit 64k code at 0x00000000 */ + " .word 0xffff, 0x0000 \n" + " .byte 0, 0x9a, 0, 0 \n" + /* selgdt 0x30 16-bit 64k data at 0x00000000 */ + " .word 0xffff, 0x0000 \n" + " .byte 0, 0x92, 0, 0 \n" + "__mygdt_end: \n");
/* Declare a pointer to where our idt is going to be i.e. at mem zero */ -__asm__ ("__myidt: \n" - /* 16-bit limit */ - " .word 1023 \n" - /* 24-bit base */ - " .long 0 \n" - " .word 0 \n" -); +__asm__("__myidt: \n" + /* 16-bit limit */ + " .word 1023 \n" + /* 24-bit base */ + " .long 0 \n" " .word 0 \n");
-/* The address arguments to this function are PHYSICAL ADDRESSES */ +/* The address arguments to this function are PHYSICAL ADDRESSES */ static void real_mode_switch_call_vsm(unsigned long smm, unsigned long sysm) { uint16_t entryHi = (VSA2_ENTRY_POINT & 0xffff0000) >> 4; uint16_t entryLo = (VSA2_ENTRY_POINT & 0xffff);
- __asm__ __volatile__ ( - // paranoia -- does ecx get saved? not sure. This is - // the easiest safe thing to do. - " pushal \n" - /* save the stack */ - " mov %%esp, __stack \n" - " jmp 1f \n" - "__stack: .long 0 \n" - "1:\n" - /* get devfn into %%ecx */ - " movl %%esp, %%ebp \n" + __asm__ __volatile__( + // paranoia -- does ecx get saved? not sure. This is + // the easiest safe thing to do. + " pushal \n" + /* save the stack */ + " mov %%esp, __stack \n" + " jmp 1f \n" + "__stack: .long 0 \n" "1:\n" + /* get devfn into %%ecx */ + " movl %%esp, %%ebp \n" #if 0 - /* I'm not happy about that pushal followed by esp-relative references. - * just do hard-codes for now - */ - " movl 8(%%ebp), %%ecx \n" - " movl 12(%%ebp), %%edx \n" + /* I'm not happy about that pushal followed by esp-relative references. + * just do hard-codes for now + */ + " movl 8(%%ebp), %%ecx \n" + " movl 12(%%ebp), %%edx \n" #endif - " movl %0, %%ecx \n" - " movl %1, %%edx \n" - - /* load 'our' gdt */ - " lgdt %%cs:__mygdtaddr \n" - - /* This configures CS properly for real mode. */ - " ljmp $0x28, $__rms_16bit\n" - "__rms_16bit: \n" - " .code16 \n" - /* 16 bit code from here on... */ - - /* Load the segment registers w/ properly configured segment - * descriptors. They will retain these configurations (limits, - * writability, etc.) once protected mode is turned off. */ - " mov $0x30, %%ax \n" - " mov %%ax, %%ds \n" - " mov %%ax, %%es \n" - " mov %%ax, %%fs \n" - " mov %%ax, %%gs \n" - " mov %%ax, %%ss \n" - - /* Turn off protection (bit 0 in CR0) */ - " movl %%cr0, %%eax \n" - " andl $0xFFFFFFFE, %%eax \n" - " movl %%eax, %%cr0 \n" - - /* Now really going into real mode */ - " ljmp $0, $__rms_real\n" - "__rms_real: \n" - - /* put the stack at the end of page zero. - * that way we can easily share it between real and protected, - * since the 16-bit ESP at segment 0 will work for any case. */ - /* Setup a stack */ - " mov $0x0, %%ax \n" - " mov %%ax, %%ss \n" - " movl $0x1000, %%eax \n" - " movl %%eax, %%esp \n" - - /* Load our 16 it idt */ - " xor %%ax, %%ax \n" - " mov %%ax, %%ds \n" - " lidt __myidt \n" - - /* Dump zeros in the other segregs */ - " mov %%ax, %%es \n" - /* FixMe: Big real mode for gs, fs? */ - " mov %%ax, %%fs \n" - " mov %%ax, %%gs \n" - " mov $0x40, %%ax \n" - " mov %%ax, %%ds \n" - //" mov %%cx, %%ax \n" - " movl %0, %%ecx \n" - " movl %1, %%edx \n" - - /* call the VSA2 entry point address */ - " lcall %2, %3\n" - - /* if we got here, just about done. - * Need to get back to protected mode */ - " movl %%cr0, %%eax \n" - " orl $0x0000001, %%eax\n" /* PE = 1 */ - " movl %%eax, %%cr0 \n" - - /* Now that we are in protected mode jump to a 32 bit code segment. */ - " data32 ljmp $0x10, $vsmrestart\n" - "vsmrestart:\n" - " .code32\n" - " movw $0x18, %%ax \n" - " mov %%ax, %%ds \n" - " mov %%ax, %%es \n" - " mov %%ax, %%fs \n" - " mov %%ax, %%gs \n" - " mov %%ax, %%ss \n" - - /* restore proper gdt and idt */ - " lgdt %%cs:gdtarg \n" - " lidt idtarg \n" - - ".globl vsm_exit \n" - "vsm_exit: \n" - " mov __stack, %%esp \n" - " popal \n" - :: "g" (smm), "g" (sysm), "g" (entryHi), "g" (entryLo)); + " movl %0, %%ecx \n" + " movl %1, %%edx \n" + /* load 'our' gdt */ + " lgdt %%cs:__mygdtaddr \n" + /* This configures CS properly for real mode. */ + " ljmp $0x28, $__rms_16bit\n" + "__rms_16bit: \n" + " .code16 \n" + /* 16 bit code from here on... */ + /* Load the segment registers w/ properly configured segment + * descriptors. They will retain these configurations (limits, + * writability, etc.) once protected mode is turned off. */ + " mov $0x30, %%ax \n" + " mov %%ax, %%ds \n" + " mov %%ax, %%es \n" + " mov %%ax, %%fs \n" + " mov %%ax, %%gs \n" + " mov %%ax, %%ss \n" + /* Turn off protection (bit 0 in CR0) */ + " movl %%cr0, %%eax \n" + " andl $0xFFFFFFFE, %%eax \n" + " movl %%eax, %%cr0 \n" + /* Now really going into real mode */ + " ljmp $0, $__rms_real\n" + "__rms_real: \n" + /* put the stack at the end of page zero. + * that way we can easily share it between real and protected, + * since the 16-bit ESP at segment 0 will work for any case. */ + /* Setup a stack */ + " mov $0x0, %%ax \n" + " mov %%ax, %%ss \n" + " movl $0x1000, %%eax \n" + " movl %%eax, %%esp \n" + /* Load our 16 it idt */ + " xor %%ax, %%ax \n" + " mov %%ax, %%ds \n" + " lidt __myidt \n" + /* Dump zeros in the other segregs */ + " mov %%ax, %%es \n" + /* FixMe: Big real mode for gs, fs? */ + " mov %%ax, %%fs \n" + " mov %%ax, %%gs \n" + " mov $0x40, %%ax \n" + " mov %%ax, %%ds \n" + //" mov %%cx, %%ax \n" + " movl %0, %%ecx \n" + " movl %1, %%edx \n" + /* call the VSA2 entry point address */ + " lcall %2, %3\n" + /* if we got here, just about done. + * Need to get back to protected mode */ + " movl %%cr0, %%eax \n" " orl $0x0000001, %%eax\n" /* PE = 1 */ + " movl %%eax, %%cr0 \n" + /* Now that we are in protected mode jump to a 32 bit code segment. */ + " data32 ljmp $0x10, $vsmrestart\n" + "vsmrestart:\n" + " .code32\n" + " movw $0x18, %%ax \n" + " mov %%ax, %%ds \n" + " mov %%ax, %%es \n" + " mov %%ax, %%fs \n" + " mov %%ax, %%gs \n" + " mov %%ax, %%ss \n" + /* restore proper gdt and idt */ + " lgdt %%cs:gdtarg \n" + " lidt idtarg \n" + ".globl vsm_exit \n" + "vsm_exit: \n" + " mov __stack, %%esp \n" + " popal \n":: + "g" + (smm), + "g"(sysm), "g"(entryHi), "g"(entryLo)); }
-__asm__ (".text\n""real_mode_switch_end:\n"); +__asm__(".text\n" "real_mode_switch_end:\n"); extern char real_mode_switch_end[];
// andrei: some VSA virtual register helpers: raw read and MSR read @@ -257,17 +231,14 @@ uint32_t VSA_vrRead(uint16_t classIndex) { unsigned eax, ebx, ecx, edx; - asm volatile( - - "movw $0x0AC1C, %%dx \n" - "orl $0x0FC530000, %%eax \n" - "outl %%eax, %%dx \n" - "addb $2, %%dl \n" - "inw %%dx, %%ax \n" - - : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) - : "a" (classIndex) - ); + asm volatile ("movw $0x0AC1C, %%dx \n" + "orl $0x0FC530000, %%eax \n" + "outl %%eax, %%dx \n" + "addb $2, %%dl \n" + "inw %%dx, %%ax \n":"=a" + (eax), "=b"(ebx), "=c"(ecx), "=d"(edx) + :"a"(classIndex) + );
return eax; } @@ -275,17 +246,14 @@ uint32_t VSA_msrRead(uint32_t msrAddr) { unsigned eax, ebx, ecx, edx; - asm volatile( - - "movw $0x0AC1C, %%dx \n" - "movl $0x0FC530007, %%eax \n" - "outl %%eax, %%dx \n" - "addb $2, %%dl \n" - "inw %%dx, %%ax \n" - - : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) - : "c" (msrAddr) - ); + asm volatile ("movw $0x0AC1C, %%dx \n" + "movl $0x0FC530007, %%eax \n" + "outl %%eax, %%dx \n" + "addb $2, %%dl \n" + "inw %%dx, %%ax \n":"=a" + (eax), "=b"(ebx), "=c"(ecx), "=d"(edx) + :"c"(msrAddr) + );
return eax; } @@ -296,38 +264,38 @@ unsigned long busdevfn; unsigned int rom = 0; unsigned char *buf; - unsigned int size = SMM_SIZE*1024; + unsigned int size = SMM_SIZE * 1024; int i; - unsigned long ilen, olen; - + unsigned long ilen, olen; + printk_err("do_vsmbios\n"); /* clear vsm bios data area */ for (i = 0x400; i < 0x500; i++) { - *(volatile unsigned char *) i = 0; + *(volatile unsigned char *)i = 0; }
/* declare rom address here - keep any config data out of the way * of core LXB stuff */
/* this is the base of rom on the LX at present. At some point, this has to be - * much better parameterized - */ + * much better parameterized + */ //rom = 0xfff80000; //rom = 0xfffc0000; /* the VSA starts at the base of rom - 64 */ //rom = ((unsigned long) 0) - (ROM_SIZE + 64*1024); - + //rom = 0xfffc8000;
//VSA is cat onto the end after LB builds - rom = ((unsigned long) 0) - (ROM_SIZE + 36 * 1024); - buf = (unsigned char *) VSA2_BUFFER; - olen = unrv2b((uint8_t *)rom, buf, &ilen); + rom = ((unsigned long)0) - (ROM_SIZE + 36 * 1024); + buf = (unsigned char *)VSA2_BUFFER; + olen = unrv2b((uint8_t *) rom, buf, &ilen); printk_debug("buf ilen %d olen%d\n", ilen, olen); printk_debug("buf %p *buf %d buf[256k] %d\n", - buf, buf[0], buf[SMM_SIZE*1024]); + buf, buf[0], buf[SMM_SIZE * 1024]); printk_debug("buf[0x20] signature is %x:%x:%x:%x\n", - buf[0x20] ,buf[0x21] ,buf[0x22],buf[0x23]); + buf[0x20], buf[0x21], buf[0x22], buf[0x23]); /* check for post code at start of vsainit.bin. If you don't see it, don't bother. */ if ((buf[0x20] != 0xb0) || (buf[0x21] != 0x10) || @@ -335,11 +303,10 @@ printk_err("do_vsmbios: no vsainit.bin signature, skipping!\n"); return; } - //memcpy((void *) VSA2_BUFFER, buf, size);
//for (i = 0; i < 0x800000; i++) - // outb(0xaa, 0x80); + // outb(0xaa, 0x80);
/* ecx gets smm, edx gets sysm */ printk_err("Call real_mode_switch_call_vsm\n"); @@ -350,166 +317,148 @@ outb(0x12, 0x41);
// check that VSA is running OK - if(VSA_vrRead(SIGNATURE) == VSA2_SIGNATURE) + if (VSA_vrRead(SIGNATURE) == VSA2_SIGNATURE) printk_debug("do_vsmbios: VSA2 VR signature verified\n"); - else printk_err("do_vsmbios: VSA2 VR signature not valid, install failed!\n"); + else + printk_err + ("do_vsmbios: VSA2 VR signature not valid, install failed!\n"); }
- -// we had hoped to avoid this. -// this is a stub IDT only. It's main purpose is to ignore calls -// to the BIOS. +// we had hoped to avoid this. +// this is a stub IDT only. It's main purpose is to ignore calls +// to the BIOS. // no longer. Dammit. We have to respond to these. struct realidt { unsigned short offset, cs; -}; +};
// from a handy writeup that andrey found.
-// handler. -// There are some assumptions we can make here. -// First, the Top Of Stack (TOS) is located on the top of page zero. -// we can share this stack between real and protected mode. +// handler. +// There are some assumptions we can make here. +// First, the Top Of Stack (TOS) is located on the top of page zero. +// we can share this stack between real and protected mode. // that simplifies a lot of things ... -// we'll just push all the registers on the stack as longwords, -// and pop to protected mode. -// second, since this only ever runs as part of linuxbios, +// we'll just push all the registers on the stack as longwords, +// and pop to protected mode. +// second, since this only ever runs as part of linuxbios, // we know all the segment register values -- so we don't save any. -// keep the handler that calls things small. It can do a call to +// keep the handler that calls things small. It can do a call to // more complex code in linuxbios itself. This helps a lot as we don't // have to do address fixup in this little stub, and calls are absolute // so the handler is relocatable. void handler(void) { - __asm__ __volatile__ ( - " .code16 \n" - "idthandle: \n" - " pushal \n" - " movb $0, %al \n" - " ljmp $0, $callbiosint16\n" - "end_idthandle: \n" - " .code32 \n" - ); + __asm__ __volatile__(" .code16 \n" + "idthandle: \n" + " pushal \n" + " movb $0, %al \n" + " ljmp $0, $callbiosint16\n" + "end_idthandle: \n" + " .code32 \n"); }
void debughandler(void) { - __asm__ __volatile__ ( - " .code16 \n" - "debughandle: \n" - " pushw %cx \n" - " movw $250, %cx \n" - "dbh1: \n" - " loop dbh1 \n" - " popw %cx \n" - " iret \n" - "end_debughandle: \n" - ".code32 \n" - ); + __asm__ __volatile__(" .code16 \n" + "debughandle: \n" + " pushw %cx \n" + " movw $250, %cx \n" + "dbh1: \n" + " loop dbh1 \n" + " popw %cx \n" + " iret \n" + "end_debughandle: \n" ".code32 \n"); }
// Calling conventions. The first C function is called with this stuff // on the stack. They look like value parameters, but note that if you -// modify them they will go back to the INTx function modified. +// modify them they will go back to the INTx function modified. // the C function will call the biosint function with these as -// REFERENCE parameters. In this way, we can easily get +// REFERENCE parameters. In this way, we can easily get // returns back to the INTx caller (i.e. vgabios) void callbiosint(void) { - __asm__ __volatile__ ( - " .code16 \n" - "callbiosint16: \n" - " push %ds \n" - " push %es \n" - " push %fs \n" - " push %gs \n" - // clean up the int #. To save space we put it in the lower - // byte. But the top 24 bits are junk. - " andl $0xff, %eax\n" - // this push does two things: - // - put the INT # on the stack as a parameter - // - provides us with a temp for the %cr0 mods. - " pushl %eax \n" - " movb $0xbb, %al\n" - " outb %al, $0x80\n" - " movl %cr0, %eax\n" - " orl $0x00000001, %eax\n" /* PE = 1 */ - " movl %eax, %cr0\n" - /* Now that we are in protected mode jump to a 32 bit code segment. */ - " data32 ljmp $0x10, $biosprotect\n" - "biosprotect: \n" - " .code32 \n" - " movw $0x18, %ax \n" - " mov %ax, %ds \n" - " mov %ax, %es \n" - " mov %ax, %fs \n" - " mov %ax, %gs \n" - " mov %ax, %ss \n" - " lidt idtarg \n" - " call biosint \n" - // back to real mode ... - " ljmp $0x28, $__rms_16bit2\n" - "__rms_16bit2: \n" - " .code16 \n" - /* 16 bit code from here on... */ - /* Load the segment registers w/ properly configured segment - * descriptors. They will retain these configurations (limits, - * writability, etc.) once protected mode is turned off. */ - " mov $0x30, %ax \n" - " mov %ax, %ds \n" - " mov %ax, %es \n" - " mov %ax, %fs \n" - " mov %ax, %gs \n" - " mov %ax, %ss \n" - - /* Turn off protection (bit 0 in CR0) */ - " movl %cr0, %eax \n" - " andl $0xFFFFFFFE, %eax \n" - " movl %eax, %cr0 \n" - - /* Now really going into real mode */ - " ljmp $0, $__rms_real2 \n" - "__rms_real2: \n" - - /* Setup a stack - * FixME: where is esp? */ - /* no need for a fix here. The esp is shared from 32-bit and 16-bit mode. - * you have to hack on the ss, but the esp remains the same across - * modes. - */ - " mov $0x0, %ax \n" - " mov %ax, %ss \n" - - /* debugging for RGM */ - " mov $0x11, %al \n" - " outb %al, $0x80 \n" - - /* Load our 16 bit idt */ - " xor %ax, %ax \n" - " mov %ax, %ds \n" - " lidt __myidt \n" - - /* Dump zeros in the other segregs */ - " mov %ax, %es \n" - " mov %ax, %fs \n" - " mov %ax, %gs \n" - " mov $0x40, %ax \n" - " mov %ax, %ds \n" - - /* pop the INT # that you pushed earlier */ - " popl %eax \n" - " pop %gs \n" - " pop %fs \n" - " pop %es \n" - " pop %ds \n" - " popal \n" - " iret \n" - " .code32 \n" - ); + __asm__ __volatile__(" .code16 \n" + "callbiosint16: \n" + " push %ds \n" + " push %es \n" + " push %fs \n" " push %gs \n" + // clean up the int #. To save space we put it in the lower + // byte. But the top 24 bits are junk. + " andl $0xff, %eax\n" + // this push does two things: + // - put the INT # on the stack as a parameter + // - provides us with a temp for the %cr0 mods. + " pushl %eax \n" " movb $0xbb, %al\n" " outb %al, $0x80\n" " movl %cr0, %eax\n" " orl $0x00000001, %eax\n" /* PE = 1 */ + " movl %eax, %cr0\n" + /* Now that we are in protected mode jump to a 32 bit code segment. */ + " data32 ljmp $0x10, $biosprotect\n" + "biosprotect: \n" + " .code32 \n" + " movw $0x18, %ax \n" + " mov %ax, %ds \n" + " mov %ax, %es \n" + " mov %ax, %fs \n" + " mov %ax, %gs \n" + " mov %ax, %ss \n" + " lidt idtarg \n" + " call biosint \n" + // back to real mode ... + " ljmp $0x28, $__rms_16bit2\n" + "__rms_16bit2: \n" + " .code16 \n" + /* 16 bit code from here on... */ + /* Load the segment registers w/ properly configured segment + * descriptors. They will retain these configurations (limits, + * writability, etc.) once protected mode is turned off. */ + " mov $0x30, %ax \n" + " mov %ax, %ds \n" + " mov %ax, %es \n" + " mov %ax, %fs \n" + " mov %ax, %gs \n" + " mov %ax, %ss \n" + /* Turn off protection (bit 0 in CR0) */ + " movl %cr0, %eax \n" + " andl $0xFFFFFFFE, %eax \n" + " movl %eax, %cr0 \n" + /* Now really going into real mode */ + " ljmp $0, $__rms_real2 \n" + "__rms_real2: \n" + /* Setup a stack + * FixME: where is esp? */ + /* no need for a fix here. The esp is shared from 32-bit and 16-bit mode. + * you have to hack on the ss, but the esp remains the same across + * modes. + */ + " mov $0x0, %ax \n" + " mov %ax, %ss \n" + /* debugging for RGM */ + " mov $0x11, %al \n" + " outb %al, $0x80 \n" + /* Load our 16 bit idt */ + " xor %ax, %ax \n" + " mov %ax, %ds \n" + " lidt __myidt \n" + /* Dump zeros in the other segregs */ + " mov %ax, %es \n" + " mov %ax, %fs \n" + " mov %ax, %gs \n" + " mov $0x40, %ax \n" + " mov %ax, %ds \n" + /* pop the INT # that you pushed earlier */ + " popl %eax \n" + " pop %gs \n" + " pop %fs \n" + " pop %es \n" + " pop %ds \n" + " popal \n" + " iret \n" + " .code32 \n"); }
enum { - PCIBIOS = 0x1a, + PCIBIOS = 0x1a, MEMSIZE = 0x12 };
@@ -519,29 +468,29 @@
int handleint21(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp, unsigned long *pesp, unsigned long *pebx, unsigned long *pedx, - unsigned long *pecx, unsigned long *peax, unsigned long *pflags - ); + unsigned long *pecx, unsigned long *peax, + unsigned long *pflags);
int biosint(unsigned long intnumber, unsigned long gsfs, unsigned long dses, unsigned long edi, unsigned long esi, - unsigned long ebp, unsigned long esp, - unsigned long ebx, unsigned long edx, - unsigned long ecx, unsigned long eax, + unsigned long ebp, unsigned long esp, + unsigned long ebx, unsigned long edx, + unsigned long ecx, unsigned long eax, unsigned long cs_ip, unsigned short stackflags) { - unsigned long ip; - unsigned long cs; + unsigned long ip; + unsigned long cs; unsigned long flags; int ret = -1;
ip = cs_ip & 0xffff; cs = cs_ip >> 16; flags = stackflags; - + printk_debug("biosint: INT# 0x%lx\n", intnumber); - printk_debug("biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n", - eax, ebx, ecx, edx); + printk_debug("biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n", + eax, ebx, ecx, edx); printk_debug("biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n", ebp, esp, edi, esi); printk_debug("biosint: ip 0x%x cs 0x%x flags 0x%x\n", @@ -549,15 +498,15 @@ printk_debug("biosint: gs 0x%x fs 0x%x ds 0x%x es 0x%x\n", gsfs >> 16, gsfs & 0xffff, dses >> 16, dses & 0xffff);
- // cases in a good compiler are just as good as your own tables. + // cases in a good compiler are just as good as your own tables. switch (intnumber) { - case 0 ... 15: + case 0...15: // These are not BIOS service, but the CPU-generated exceptions printk_info("biosint: Oops, exception %u\n", intnumber); if (esp < 0x1000) { printk_debug("Stack contents: "); while (esp < 0x1000) { - printk_debug("0x%04x ", *(unsigned short *) esp); + printk_debug("0x%04x ", *(unsigned short *)esp); esp += 2; } printk_debug("\n"); @@ -566,82 +515,78 @@ // "longjmp" //vga_exit(); break; - + case PCIBIOS: - ret = pcibios( &edi, &esi, &ebp, &esp, - &ebx, &edx, &ecx, &eax, &flags); + ret = pcibios(&edi, &esi, &ebp, &esp, + &ebx, &edx, &ecx, &eax, &flags); break; - case MEMSIZE: - // who cares. + case MEMSIZE: + // who cares. eax = 128 * 1024; ret = 0; break; case 0x15: - ret=handleint21( &edi, &esi, &ebp, &esp, - &ebx, &edx, &ecx, &eax, &flags); + ret = handleint21(&edi, &esi, &ebp, &esp, + &ebx, &edx, &ecx, &eax, &flags); break; default: - printk_info("BIOSINT: Unsupport int #0x%x\n", - intnumber); + printk_info("BIOSINT: Unsupport int #0x%x\n", intnumber); break; } if (ret) - flags |= 1; // carry flags + flags |= 1; // carry flags else flags &= ~1; stackflags = flags; return ret; -} - +}
-void setup_realmode_idt(void) +void setup_realmode_idt(void) { extern unsigned char idthandle, end_idthandle; extern unsigned char debughandle, end_debughandle;
int i; - struct realidt *idts = (struct realidt *) 0; + struct realidt *idts = (struct realidt *)0; int codesize = &end_idthandle - &idthandle; unsigned char *intbyte, *codeptr; - + // for each int, we create a customized little handler - // that just pushes %ax, puts the int # in %al, - // then calls the common interrupt handler. - // this necessitated because intel didn't know much about + // that just pushes %ax, puts the int # in %al, + // then calls the common interrupt handler. + // this necessitated because intel didn't know much about // architecture when they did the 8086 (it shows) // (hmm do they know anymore even now :-) - // obviously you can see I don't really care about memory + // obviously you can see I don't really care about memory // efficiency. If I did I would probe back through the stack // and get it that way. But that's really disgusting. for (i = 0; i < 256; i++) { idts[i].cs = 0; - codeptr = (unsigned char*) 4096 + i * codesize; - idts[i].offset = (unsigned) codeptr; + codeptr = (unsigned char *)4096 + i * codesize; + idts[i].offset = (unsigned)codeptr; memcpy(codeptr, &idthandle, codesize); intbyte = codeptr + 3; *intbyte = i; } - + // fixed entry points - + // VGA BIOSes tend to hardcode f000:f065 as the previous handler of - // int10. + // int10. // calling convention here is the same as INTs, we can reuse // the int entry code. - codeptr = (unsigned char*) 0xff065; + codeptr = (unsigned char *)0xff065; memcpy(codeptr, &idthandle, codesize); intbyte = codeptr + 3; - *intbyte = 0x42; /* int42 is the relocated int10 */ + *intbyte = 0x42; /* int42 is the relocated int10 */
/* debug handler - useful to set a programmable delay between instructions if the TF bit is set upon call to real mode */ idts[1].cs = 0; idts[1].offset = 16384; - memcpy((void*)16384, &debughandle, &end_debughandle - &debughandle); + memcpy((void *)16384, &debughandle, &end_debughandle - &debughandle); }
- - enum { CHECK = 0xb001, FINDDEV = 0xb102, @@ -654,15 +599,15 @@ };
// errors go in AH. Just set these up so that word assigns -// will work. KISS. +// will work. KISS. enum { PCIBIOS_NODEV = 0x8600, PCIBIOS_BADREG = 0x8700 };
int -pcibios(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp, - unsigned long *pesp, unsigned long *pebx, unsigned long *pedx, +pcibios(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp, + unsigned long *pesp, unsigned long *pebx, unsigned long *pedx, unsigned long *pecx, unsigned long *peax, unsigned long *pflags) { unsigned long edi = *pedi; @@ -674,150 +619,153 @@ unsigned long ecx = *pecx; unsigned long eax = *peax; unsigned long flags = *pflags; - unsigned short func = (unsigned short) eax; + unsigned short func = (unsigned short)eax; int retval = 0; unsigned short devid, vendorid, devfn; - short devindex; /* Use short to get rid of gabage in upper half of 32-bit register */ + short devindex; /* Use short to get rid of gabage in upper half of 32-bit register */ unsigned char bus; device_t dev; - - switch(func) { - case CHECK: + + switch (func) { + case CHECK: *pedx = 0x4350; *pecx = 0x2049; retval = 0; break; case FINDDEV: - { - devid = *pecx; - vendorid = *pedx; - devindex = *pesi; - dev = 0; - while ((dev = dev_find_device(vendorid, devid, dev))) { - if (devindex <= 0) - break; - devindex--; - } - if (dev) { - unsigned short busdevfn; - *peax = 0; - // busnum is an unsigned char; - // devfn is an int, so we mask it off. - busdevfn = (dev->bus->secondary << 8) - | (dev->path.u.pci.devfn & 0xff); - printk_debug("0x%x: return 0x%x\n", func, busdevfn); - *pebx = busdevfn; - retval = 0; - } else { - *peax = PCIBIOS_NODEV; - retval = -1; + { + devid = *pecx; + vendorid = *pedx; + devindex = *pesi; + dev = 0; + while ((dev = dev_find_device(vendorid, devid, dev))) { + if (devindex <= 0) + break; + devindex--; + } + if (dev) { + unsigned short busdevfn; + *peax = 0; + // busnum is an unsigned char; + // devfn is an int, so we mask it off. + busdevfn = (dev->bus->secondary << 8) + | (dev->path.u.pci.devfn & 0xff); + printk_debug("0x%x: return 0x%x\n", func, + busdevfn); + *pebx = busdevfn; + retval = 0; + } else { + *peax = PCIBIOS_NODEV; + retval = -1; + } } - } - break; + break; case READCONFDWORD: case READCONFWORD: case READCONFBYTE: case WRITECONFDWORD: case WRITECONFWORD: case WRITECONFBYTE: - { - unsigned long dword; - unsigned short word; - unsigned char byte; - unsigned char reg; - - devfn = *pebx & 0xff; - bus = *pebx >> 8; - reg = *pedi; - dev = dev_find_slot(bus, devfn); - if (! dev) { - printk_debug("0x%x: BAD DEVICE bus %d devfn 0x%x\n", func, bus, devfn); - // idiots. the pcibios guys assumed you'd never pass a bad bus/devfn! - *peax = PCIBIOS_BADREG; - retval = -1; - } - switch(func) { - case READCONFBYTE: - byte = pci_read_config8(dev, reg); - *pecx = byte; - break; - case READCONFWORD: - word = pci_read_config16(dev, reg); - *pecx = word; - break; - case READCONFDWORD: - dword = pci_read_config32(dev, reg); - *pecx = dword; - break; - case WRITECONFBYTE: - byte = *pecx; - pci_write_config8(dev, reg, byte); - break; - case WRITECONFWORD: - word = *pecx; - pci_write_config16(dev, reg, word); - break; - case WRITECONFDWORD: - dword = *pecx; - pci_write_config32(dev, reg, dword); - break; - } - - if (retval) - retval = PCIBIOS_BADREG; - printk_debug("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%lx\n", + { + unsigned long dword; + unsigned short word; + unsigned char byte; + unsigned char reg; + + devfn = *pebx & 0xff; + bus = *pebx >> 8; + reg = *pedi; + dev = dev_find_slot(bus, devfn); + if (!dev) { + printk_debug + ("0x%x: BAD DEVICE bus %d devfn 0x%x\n", + func, bus, devfn); + // idiots. the pcibios guys assumed you'd never pass a bad bus/devfn! + *peax = PCIBIOS_BADREG; + retval = -1; + } + switch (func) { + case READCONFBYTE: + byte = pci_read_config8(dev, reg); + *pecx = byte; + break; + case READCONFWORD: + word = pci_read_config16(dev, reg); + *pecx = word; + break; + case READCONFDWORD: + dword = pci_read_config32(dev, reg); + *pecx = dword; + break; + case WRITECONFBYTE: + byte = *pecx; + pci_write_config8(dev, reg, byte); + break; + case WRITECONFWORD: + word = *pecx; + pci_write_config16(dev, reg, word); + break; + case WRITECONFDWORD: + dword = *pecx; + pci_write_config32(dev, reg, dword); + break; + } + + if (retval) + retval = PCIBIOS_BADREG; + printk_debug + ("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%lx\n", func, bus, devfn, reg, *pecx); - *peax = 0; - retval = 0; - } - break; + *peax = 0; + retval = 0; + } + break; default: - printk_err("UNSUPPORTED PCIBIOS FUNCTION 0x%x\n", func); + printk_err("UNSUPPORTED PCIBIOS FUNCTION 0x%x\n", func); break; } - + return retval; -} +}
int handleint21(unsigned long *edi, unsigned long *esi, unsigned long *ebp, unsigned long *esp, unsigned long *ebx, unsigned long *edx, unsigned long *ecx, unsigned long *eax, unsigned long *flags) { - int res=-1; + int res = -1; printk_debug("handleint21, eax 0x%x\n", *eax); - switch(*eax&0xffff) - { + switch (*eax & 0xffff) { case 0x5f19: break; case 0x5f18: - *eax=0x5f; - *ebx=0x545; // MCLK = 133, 32M frame buffer, 256 M main memory - *ecx=0x060; - res=0; + *eax = 0x5f; + *ebx = 0x545; // MCLK = 133, 32M frame buffer, 256 M main memory + *ecx = 0x060; + res = 0; break; case 0x5f00: *eax = 0x8600; break; case 0x5f01: *eax = 0x5f; - *ecx = (*ecx & 0xffffff00 ) | 2; // panel type = 2 = 1024 * 768 + *ecx = (*ecx & 0xffffff00) | 2; // panel type = 2 = 1024 * 768 res = 0; break; case 0x5f02: - *eax=0x5f; - *ebx= (*ebx & 0xffff0000) | 2; - *ecx= (*ecx & 0xffff0000) | 0x401; // PAL + crt only - *edx= (*edx & 0xffff0000) | 0; // TV Layout - default - res=0; + *eax = 0x5f; + *ebx = (*ebx & 0xffff0000) | 2; + *ecx = (*ecx & 0xffff0000) | 0x401; // PAL + crt only + *edx = (*edx & 0xffff0000) | 0; // TV Layout - default + res = 0; break; case 0x5f0f: - *eax=0x860f; + *eax = 0x860f; break; case 0xBEA7: - *eax=66; + *eax = 66; break; case 0xBEA4: - *eax=500; + *eax = 500; break; } return res;
-- Jordan Crouse Senior Linux Engineer Advanced Micro Devices, Inc. <www.amd.com/embeddedprocessors>
Fix the indent and whitespace to match LinuxBIOS standards
Signed-off-by: Jordan Crouse jordan.crouse@amd.com
Index: LinuxBIOSv2/src/southbridge/amd/cs5536/chip.h =================================================================== --- LinuxBIOSv2.orig/src/southbridge/amd/cs5536/chip.h 2007-05-07 14:29:18.000000000 -0600 +++ LinuxBIOSv2/src/southbridge/amd/cs5536/chip.h 2007-05-07 14:29:40.000000000 -0600 @@ -21,26 +21,26 @@ #ifndef _SOUTHBRIDGE_AMD_CS5536 #define _SOUTHBRIDGE_AMD_CS5536
-#define MAX_UNWANTED_VPCI 8 /* increase if needed */ +#define MAX_UNWANTED_VPCI 8 /* increase if needed */
extern struct chip_operations southbridge_amd_cs5536_ops;
struct southbridge_amd_cs5536_config { - unsigned int lpc_serirq_enable; /* interrupt enables for LPC bus; each bit is an irq 0-15 */ - unsigned int lpc_serirq_polarity; /* LPC IRQ polarity; each bit is an irq 0-15 */ - unsigned char lpc_serirq_mode; /* 0:Continuous 1:Quiet */ - unsigned int enable_gpio_int_route; /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. See virtual pci spec... */ + unsigned int lpc_serirq_enable; /* interrupt enables for LPC bus; each bit is an irq 0-15 */ + unsigned int lpc_serirq_polarity; /* LPC IRQ polarity; each bit is an irq 0-15 */ + unsigned char lpc_serirq_mode; /* 0:Continuous 1:Quiet */ + unsigned int enable_gpio_int_route; /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. See virtual pci spec... */ unsigned char enable_ide_nand_flash; /* 0:IDE 1:FLASH, if you are using nand flash instead of IDE drive */ - unsigned char enable_USBP4_device; /* Enable USB Port 4 0:host 1:device */ + unsigned char enable_USBP4_device; /* Enable USB Port 4 0:host 1:device */ unsigned int enable_USBP4_overcurrent; /* 0:off, xxxx:overcurrent setting, e.g. 0x3FEA CS5536 - Data Book (pages 380-381) */ - unsigned char com1_enable; /* enable COM1 */ - unsigned int com1_address; /* e.g. 0x3F8 */ - unsigned int com1_irq; /* e.g. 4 */ - unsigned char com2_enable; /* enable COM2 */ - unsigned int com2_address; /* e.g. 0x2F8 */ - unsigned int com2_irq; /* e.g. 3 */ + unsigned char com1_enable; /* enable COM1 */ + unsigned int com1_address; /* e.g. 0x3F8 */ + unsigned int com1_irq; /* e.g. 4 */ + unsigned char com2_enable; /* enable COM2 */ + unsigned int com2_address; /* e.g. 0x2F8 */ + unsigned int com2_irq; /* e.g. 3 */ unsigned int unwanted_vpci[MAX_UNWANTED_VPCI]; /* the following allow you to disable unwanted virtualized PCI devices */
};
-#endif /* _SOUTHBRIDGE_AMD_CS5536 */ +#endif /* _SOUTHBRIDGE_AMD_CS5536 */ Index: LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.c =================================================================== --- LinuxBIOSv2.orig/src/southbridge/amd/cs5536/cs5536.c 2007-05-07 09:45:45.000000000 -0600 +++ LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.c 2007-05-07 14:30:03.000000000 -0600 @@ -41,23 +41,23 @@
/* Master Configuration Register for Bus Masters.*/ struct msrinit SB_MASTER_CONF_TABLE[] = { - {USB2_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00008f000}}, - {ATA_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00048f000}}, - {AC97_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00008f000}}, - {MDD_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00000f000}}, - {0,{0,0}} + {USB2_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000}}, + {ATA_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00048f000}}, + {AC97_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000}}, + {MDD_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00000f000}}, + {0, {0, 0}} };
/* 5536 Clock Gating*/ struct msrinit CS5536_CLOCK_GATING_TABLE[] = { /* MSR Setting*/ - {GLIU_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000004}}, - {GLPCI_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}}, - {GLCP_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000004}}, - {MDD_SB_GLD_MSR_PM, {.hi=0,.lo=0x050554111}}, /* SMBus clock gating errata (PBZ 2226 & SiBZ 3977)*/ - {ATA_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}}, - {AC97_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}}, - {0,{0,0}} + {GLIU_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000004}}, + {GLPCI_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000005}}, + {GLCP_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000004}}, + {MDD_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x050554111}}, /* SMBus clock gating errata (PBZ 2226 & SiBZ 3977) */ + {ATA_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000005}}, + {AC97_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000005}}, + {0, {0, 0}} };
struct acpiinit { @@ -73,24 +73,24 @@ {ACPI_IO_BASE + 0x18, 0x0FFFFFFFF}, {ACPI_IO_BASE + 0x00, 0x0000FFFF}, {PMS_IO_BASE + PM_SCLK, 0x000000E00}, - {PMS_IO_BASE + PM_SED, 0x000004601}, + {PMS_IO_BASE + PM_SED, 0x000004601}, {PMS_IO_BASE + PM_SIDD, 0x000008C02}, - {PMS_IO_BASE + PM_WKD, 0x0000000A0}, + {PMS_IO_BASE + PM_WKD, 0x0000000A0}, {PMS_IO_BASE + PM_WKXD, 0x0000000A0}, - {0,0,0} + {0, 0, 0} };
struct FLASH_DEVICE { - unsigned char fType; /* Flash type: NOR or NAND */ + unsigned char fType; /* Flash type: NOR or NAND */ unsigned char fInterface; /* Flash interface: I/O or Memory */ - unsigned long fMask; /* Flash size/mask */ + unsigned long fMask; /* Flash size/mask */ };
struct FLASH_DEVICE FlashInitTable[] = { - { FLASH_TYPE_NAND, FLASH_IF_MEM, FLASH_MEM_4K }, /* CS0, or Flash Device 0 */ - { FLASH_TYPE_NONE, 0, 0 }, /* CS1, or Flash Device 1 */ - { FLASH_TYPE_NONE, 0, 0 }, /* CS2, or Flash Device 2 */ - { FLASH_TYPE_NONE, 0, 0 }, /* CS3, or Flash Device 3 */ + {FLASH_TYPE_NAND, FLASH_IF_MEM, FLASH_MEM_4K}, /* CS0, or Flash Device 0 */ + {FLASH_TYPE_NONE, 0, 0}, /* CS1, or Flash Device 1 */ + {FLASH_TYPE_NONE, 0, 0}, /* CS2, or Flash Device 2 */ + {FLASH_TYPE_NONE, 0, 0}, /* CS3, or Flash Device 3 */ };
#define FlashInitTableLen (sizeof(FlashInitTable)/sizeof(FlashInitTable[0])) @@ -100,8 +100,7 @@ MDD_LBAR_FLSH1, MDD_LBAR_FLSH2, MDD_LBAR_FLSH3 - }; - +};
/* ***************************************************************************/ /* **/ @@ -110,39 +109,39 @@ /* * Program ACPI LBAR and initialize ACPI registers.*/ /* **/ /* ***************************************************************************/ -static void pmChipsetInit(void) { +static void pmChipsetInit(void) +{ uint32_t val = 0; uint16_t port;
- port = (PMS_IO_BASE + 0x010); - val = 0x0E00 ; /* 1ms*/ + port = (PMS_IO_BASE + 0x010); + val = 0x0E00; /* 1ms */ outl(val, port);
- /* PM_WKXD*/ - /* Make sure bits[3:0]=0000b to clear the*/ - /* saved Sx state*/ - port = (PMS_IO_BASE + 0x034); - val = 0x0A0 ; /* 5ms*/ + /* PM_WKXD */ + /* Make sure bits[3:0]=0000b to clear the */ + /* saved Sx state */ + port = (PMS_IO_BASE + 0x034); + val = 0x0A0; /* 5ms */ outl(val, port);
- /* PM_WKD*/ - port = (PMS_IO_BASE + 0x030); + /* PM_WKD */ + port = (PMS_IO_BASE + 0x030); outl(val, port);
- /* PM_SED*/ - port = (PMS_IO_BASE + 0x014); + /* PM_SED */ + port = (PMS_IO_BASE + 0x014); /* mov eax, 0x057642 ; 100ms, works*/ - val = 0x04601 ; /* 5ms*/ + val = 0x04601; /* 5ms */ outl(val, port);
- /* PM_SIDD*/ - port = (PMS_IO_BASE + 0x020); + /* PM_SIDD */ + port = (PMS_IO_BASE + 0x020); /* mov eax, 0x0AEC84 ; 200ms, works*/ - val = 0x08C02 ; /* 10ms*/ + val = 0x08C02; /* 10ms */ outl(val, port); }
- /*************************************************************************** * * ChipsetFlashSetup @@ -152,7 +151,8 @@ * configured (don't call it if you want IDE). * **************************************************************************/ -static void ChipsetFlashSetup(void){ +static void ChipsetFlashSetup(void) +{ msr_t msr; int i; int numEnabled = 0; @@ -173,13 +173,15 @@ else msr.hi &= ~0x00000004; msr.hi |= FlashInitTable[i].fMask; - printk_debug("MSR(0x%08X, %08X_%08X)\n", FlashPort[i], msr.hi, msr.lo); + printk_debug("MSR(0x%08X, %08X_%08X)\n", FlashPort[i], + msr.hi, msr.lo); wrmsr(FlashPort[i], msr);
/* now write-enable the device */ msr = rdmsr(MDD_NORF_CNTRL); msr.lo |= (1 << i); - printk_debug("MSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL, msr.hi, msr.lo); + printk_debug("MSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL, + msr.hi, msr.lo); wrmsr(MDD_NORF_CNTRL, msr);
/* update the number enabled */ @@ -190,24 +192,26 @@ printk_debug("ChipsetFlashSetup: Finish\n");
} + /* ***************************************************************************/ /* **/ /* * enable_ide_nand_flash_header */ /* Run after VSA init to enable the flash PCI device header */ /* **/ /* ***************************************************************************/ -static void enable_ide_nand_flash_header(){ - /* Tell VSA to use FLASH PCI header. Not IDE header.*/ +static void enable_ide_nand_flash_header() +{ + /* Tell VSA to use FLASH PCI header. Not IDE header. */ outl(0x80007A40, 0xCF8); outl(0xDEADBEEF, 0xCFC); }
- #define RTC_CENTURY 0x32 #define RTC_DOMA 0x3D #define RTC_MONA 0x3E
-static void lpc_init(struct southbridge_amd_cs5536_config *sb){ +static void lpc_init(struct southbridge_amd_cs5536_config *sb) +{ msr_t msr;
if (sb->lpc_serirq_enable) { @@ -216,7 +220,7 @@ wrmsr(MDD_IRQM_LPC, msr); if (sb->lpc_serirq_polarity) { msr.lo = sb->lpc_serirq_polarity << 16; - msr.lo |= (sb->lpc_serirq_mode << 6) | (1 << 7); /* enable */ + msr.lo |= (sb->lpc_serirq_mode << 6) | (1 << 7); /* enable */ msr.hi = 0; wrmsr(MDD_LPC_SIRQ, msr); } @@ -246,43 +250,44 @@ isa_dma_init(); }
- -static void uarts_init(struct southbridge_amd_cs5536_config *sb){ +static void uarts_init(struct southbridge_amd_cs5536_config *sb) +{ msr_t msr; uint16_t addr; uint32_t gpio_addr; device_t dev;
- dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, 0); + dev = + dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, 0); gpio_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1); - gpio_addr &= ~1; /* clear IO bit */ + gpio_addr &= ~1; /* clear IO bit */ printk_debug("GPIO_ADDR: %08X\n", gpio_addr);
/* This could be extended to support IR modes */
/* COM1 */ - if (sb->com1_enable){ + if (sb->com1_enable) { /* Set the address */ - switch (sb->com1_address){ - case 0x3F8: + switch (sb->com1_address) { + case 0x3F8: addr = 7; break;
- case 0x3E8: + case 0x3E8: addr = 6; break;
- case 0x2F8: + case 0x2F8: addr = 5; break;
- case 0x2E8: + case 0x2E8: addr = 4; break; } msr = rdmsr(MDD_LEG_IO); msr.lo |= addr << 16; - wrmsr(MDD_LEG_IO,msr); + wrmsr(MDD_LEG_IO, msr);
/* Set the IRQ */ msr = rdmsr(MDD_IRQM_YHIGH); @@ -301,8 +306,9 @@ /* Set: INAUX1 Select (0x34) */ outl(GPIOL_9_SET, gpio_addr + GPIOL_IN_AUX1_SELECT);
- /* Set: GPIO 8 + 9 Pull Up (0x18) */ - outl(GPIOL_8_SET | GPIOL_9_SET, gpio_addr + GPIOL_PULLUP_ENABLE); + /* Set: GPIO 8 + 9 Pull Up (0x18) */ + outl(GPIOL_8_SET | GPIOL_9_SET, + gpio_addr + GPIOL_PULLUP_ENABLE);
/* enable COM1 */ /* Bit 1 = device enable Bit 4 = allow access to the upper banks */ @@ -310,47 +316,45 @@ msr.hi = 0; wrmsr(MDD_UART1_CONF, msr);
- } - else{ + } else { /* Reset and disable COM1 */ printk_err("Not disabling COM1 due to a bug ...\n"); /* for now, don't do this! */ return; msr = rdmsr(MDD_UART1_CONF); - msr.lo = 1; // reset + msr.lo = 1; // reset wrmsr(MDD_UART1_CONF, msr); - msr.lo = 0; // disabled + msr.lo = 0; // disabled wrmsr(MDD_UART1_CONF, msr);
/* Disable the IRQ */ msr = rdmsr(MDD_LEG_IO); msr.lo |= ~(0xF << 16); - wrmsr(MDD_LEG_IO,msr); + wrmsr(MDD_LEG_IO, msr); }
/* COM2 */ - if (sb->com2_enable){ - switch (sb->com2_address){ - case 0x3F8: + if (sb->com2_enable) { + switch (sb->com2_address) { + case 0x3F8: addr = 7; break;
- case 0x3E8: + case 0x3E8: addr = 6; break;
- case 0x2F8: + case 0x2F8: addr = 5; break;
- case 0x2E8: + case 0x2E8: addr = 4; break; } msr = rdmsr(MDD_LEG_IO); msr.lo |= addr << 20; - wrmsr(MDD_LEG_IO,msr); - + wrmsr(MDD_LEG_IO, msr);
/* Set the IRQ */ msr = rdmsr(MDD_IRQM_YHIGH); @@ -361,7 +365,7 @@ /* Set: Output Enable (0x4) */ outl(GPIOL_3_SET, gpio_addr + GPIOL_OUTPUT_ENABLE); /* Set: OUTAUX1 Select (0x10) */ - outl(GPIOL_3_SET,gpio_addr + GPIOL_OUT_AUX1_SELECT); + outl(GPIOL_3_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT);
/* GPIO4 - UART2_TX */ /* Set: Input Enable (0x20) */ @@ -369,8 +373,9 @@ /* Set: INAUX1 Select (0x34) */ outl(GPIOL_4_SET, gpio_addr + GPIOL_IN_AUX1_SELECT);
- /* Set: GPIO 3 + 3 Pull Up (0x18) */ - outl(GPIOL_3_SET | GPIOL_4_SET, gpio_addr + GPIOL_PULLUP_ENABLE); + /* Set: GPIO 3 + 3 Pull Up (0x18) */ + outl(GPIOL_3_SET | GPIOL_4_SET, + gpio_addr + GPIOL_PULLUP_ENABLE);
/* enable COM2 */ /* Bit 1 = device enable Bit 4 = allow access to the upper banks */ @@ -378,48 +383,45 @@ msr.hi = 0; wrmsr(MDD_UART2_CONF, msr);
- } - else{ + } else { /* Reset and disable COM2 */ msr = rdmsr(MDD_UART2_CONF); - msr.lo = 1; // reset + msr.lo = 1; // reset wrmsr(MDD_UART2_CONF, msr); - msr.lo = 0; // disabled + msr.lo = 0; // disabled wrmsr(MDD_UART2_CONF, msr);
/* Disable the IRQ */ msr = rdmsr(MDD_LEG_IO); msr.lo |= ~(0xF << 20); - wrmsr(MDD_LEG_IO,msr); + wrmsr(MDD_LEG_IO, msr); } }
- - #define HCCPARAMS 0x08 #define IPREG04 0xA0 - #define USB_HCCPW_SET (1 << 1) +#define USB_HCCPW_SET (1 << 1) #define UOCCAP 0x00 - #define APU_SET (1 << 15) +#define APU_SET (1 << 15) #define UOCMUX 0x04 - #define PMUX_HOST 0x02 - #define PMUX_DEVICE 0x03 - #define PUEN_SET (1 << 2) +#define PMUX_HOST 0x02 +#define PMUX_DEVICE 0x03 +#define PUEN_SET (1 << 2) #define UDCDEVCTL 0x404 - #define UDC_SD_SET (1 << 10) +#define UDC_SD_SET (1 << 10) #define UOCCTL 0x0C - #define PADEN_SET (1 << 7) - +#define PADEN_SET (1 << 7)
static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) { - uint32_t * bar; + uint32_t *bar; msr_t msr; device_t dev;
- - dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_EHCI, 0); - if(dev){ + dev = + dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_EHCI, + 0); + if (dev) {
/* Serial Short Detect Enable */ msr = rdmsr(USB2_SB_GLD_MSR_CONF); @@ -427,7 +429,7 @@ wrmsr(USB2_SB_GLD_MSR_CONF, msr);
/* write to clear diag register */ - wrmsr(USB2_SB_GLD_MSR_DIAG,rdmsr(USB2_SB_GLD_MSR_DIAG)); + wrmsr(USB2_SB_GLD_MSR_DIAG, rdmsr(USB2_SB_GLD_MSR_DIAG));
bar = (uint32_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
@@ -438,9 +440,9 @@ *(bar + HCCPARAMS) = 0x00005012; }
- - dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OTG, 0); - if(dev){ + dev = + dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OTG, 0); + if (dev) { bar = (uint32_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
*(bar + UOCMUX) &= PUEN_SET; @@ -448,8 +450,7 @@ /* Host or Device? */ if (sb->enable_USBP4_device) { *(bar + UOCMUX) |= PMUX_DEVICE; - } - else{ + } else { *(bar + UOCMUX) |= PMUX_HOST; }
@@ -460,35 +461,45 @@ }
/* PBz#6466: If the UOC(OTG) device, port 4, is configured as a device, - * then perform the following sequence: + * then perform the following sequence: * * - set SD bit in DEVCTRL udc register * - set PADEN (former OTGPADEN) bit in uoc register * - set APU bit in uoc register */ if (sb->enable_USBP4_device) { - dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_UDC, 0); - if(dev){ - bar = (uint32_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0); + dev = + dev_find_device(PCI_VENDOR_ID_AMD, + PCI_DEVICE_ID_AMD_CS5536_UDC, 0); + if (dev) { + bar = + (uint32_t *) pci_read_config32(dev, + PCI_BASE_ADDRESS_0); *(bar + UDCDEVCTL) |= UDC_SD_SET;
}
- dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OTG, 0); - if(dev){ - bar = (uint32_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0); + dev = + dev_find_device(PCI_VENDOR_ID_AMD, + PCI_DEVICE_ID_AMD_CS5536_OTG, 0); + if (dev) { + bar = + (uint32_t *) pci_read_config32(dev, + PCI_BASE_ADDRESS_0); *(bar + UOCCTL) |= PADEN_SET; *(bar + UOCCAP) |= APU_SET; } }
/* Disable virtual PCI UDC and OTG headers */ - dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_UDC, 0); - if(dev){ + dev = + dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_UDC, 0); + if (dev) { pci_write_config8(dev, 0x7C, 0xDEADBEEF); }
- dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OTG, 0); - if(dev){ + dev = + dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OTG, 0); + if (dev) { pci_write_config8(dev, 0x7C, 0xDEADBEEF); } } @@ -499,20 +510,22 @@ /* Called from northbridge init (Pre-VSA). */ /* **/ /* ***************************************************************************/ -void chipsetinit (void){ +void chipsetinit(void) +{ device_t dev; msr_t msr; uint32_t msrnum; - struct southbridge_amd_cs5536_config *sb = (struct southbridge_amd_cs5536_config *)dev->chip_info; + struct southbridge_amd_cs5536_config *sb = + (struct southbridge_amd_cs5536_config *)dev->chip_info; struct msrinit *csi;
- outb( P80_CHIPSET_INIT, 0x80); + outb(P80_CHIPSET_INIT, 0x80);
/* we hope NEVER to be in linuxbios when S3 resumes - if (! IsS3Resume()) */ + if (! IsS3Resume()) */ { struct acpiinit *aci = acpi_init_table; - for(; aci->ioreg; aci++) { + for (; aci->ioreg; aci++) { outl(aci->regdata, aci->ioreg); inl(aci->ioreg); } @@ -520,43 +533,42 @@ pmChipsetInit(); }
- /* set hd IRQ */ - outl( GPIOL_2_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE); - outl( GPIOL_2_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT); + outl(GPIOL_2_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE); + outl(GPIOL_2_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
- /* Allow IO read and writes during a ATA DMA operation.*/ - /* This could be done in the HD rom but do it here for easier debugging.*/ + /* Allow IO read and writes during a ATA DMA operation. */ + /* This could be done in the HD rom but do it here for easier debugging. */ msrnum = ATA_SB_GLD_MSR_ERR; msr = rdmsr(msrnum); msr.lo &= ~0x100; wrmsr(msrnum, msr);
- /* Enable Post Primary IDE.*/ + /* Enable Post Primary IDE. */ msrnum = GLPCI_SB_CTRL; msr = rdmsr(msrnum); - msr.lo |= GLPCI_CRTL_PPIDE_SET; + msr.lo |= GLPCI_CRTL_PPIDE_SET; wrmsr(msrnum, msr);
- csi = SB_MASTER_CONF_TABLE; - for(; csi->msrnum; csi++){ + for (; csi->msrnum; csi++) { msr.lo = csi->msr.lo; msr.hi = csi->msr.hi; - wrmsr(csi->msrnum, msr); // MSR - see table above + wrmsr(csi->msrnum, msr); // MSR - see table above }
- /* Flash BAR size Setup*/ - printk_err("%sDoing ChipsetFlashSetup()\n", sb->enable_ide_nand_flash == 1 ? "" : "Not "); + /* Flash BAR size Setup */ + printk_err("%sDoing ChipsetFlashSetup()\n", + sb->enable_ide_nand_flash == 1 ? "" : "Not "); if (sb->enable_ide_nand_flash == 1) ChipsetFlashSetup();
/* */ - /* Set up Hardware Clock Gating*/ + /* Set up Hardware Clock Gating */ /* */ { csi = CS5536_CLOCK_GATING_TABLE; - for(; csi->msrnum; csi++){ + for (; csi->msrnum; csi++) { msr.lo = csi->msr.lo; msr.hi = csi->msr.hi; wrmsr(csi->msrnum, msr); // MSR - see table above @@ -566,7 +578,8 @@
static void southbridge_init(struct device *dev) { - struct southbridge_amd_cs5536_config *sb = (struct southbridge_amd_cs5536_config *)dev->chip_info; + struct southbridge_amd_cs5536_config *sb = + (struct southbridge_amd_cs5536_config *)dev->chip_info; int i; /* * struct device *gpiodev; @@ -578,12 +591,15 @@ lpc_init(sb); uarts_init(sb);
- if (sb->enable_gpio_int_route){ - vrWrite((VRC_MISCELLANEOUS << 8) + PCI_INT_AB, (sb->enable_gpio_int_route & 0xFFFF)); - vrWrite((VRC_MISCELLANEOUS << 8) + PCI_INT_CD, (sb->enable_gpio_int_route >> 16)); + if (sb->enable_gpio_int_route) { + vrWrite((VRC_MISCELLANEOUS << 8) + PCI_INT_AB, + (sb->enable_gpio_int_route & 0xFFFF)); + vrWrite((VRC_MISCELLANEOUS << 8) + PCI_INT_CD, + (sb->enable_gpio_int_route >> 16)); }
- printk_err("cs5536: %s: enable_ide_nand_flash is %d\n", __FUNCTION__, sb->enable_ide_nand_flash); + printk_err("cs5536: %s: enable_ide_nand_flash is %d\n", __FUNCTION__, + sb->enable_ide_nand_flash); if (sb->enable_ide_nand_flash == 1) { enable_ide_nand_flash_header(); } @@ -592,13 +608,13 @@
/* disable unwanted virtual PCI devices */ for (i = 0; (i < MAX_UNWANTED_VPCI) && (0 != sb->unwanted_vpci[i]); i++) { - printk_debug("Disabling VPCI device: 0x%08X\n", sb->unwanted_vpci[i]); + printk_debug("Disabling VPCI device: 0x%08X\n", + sb->unwanted_vpci[i]); outl(sb->unwanted_vpci[i] + 0x7C, 0xCF8); - outl(0xDEADBEEF, 0xCFC); + outl(0xDEADBEEF, 0xCFC); } }
- static void southbridge_enable(struct device *dev) { printk_err("cs5536: %s: dev is %p\n", __FUNCTION__, dev); @@ -613,24 +629,24 @@ }
static struct device_operations southbridge_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, .enable_resources = cs5536_pci_dev_enable_resources, - .init = southbridge_init, -// .enable = southbridge_enable, - .scan_bus = scan_static_bus, + .init = southbridge_init, +// .enable = southbridge_enable, + .scan_bus = scan_static_bus, };
static struct pci_driver cs5536_pci_driver __pci_driver = { - .ops = &southbridge_ops, + .ops = &southbridge_ops, .vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_AMD_CS5536_ISA };
struct chip_operations southbridge_amd_cs5536_ops = { CHIP_NAME("AMD Geode CS5536 Southbridge") - /* This is only called when this device is listed in the - * static device tree. - */ - .enable_dev = southbridge_enable, + /* This is only called when this device is listed in the + * static device tree. + */ + .enable_dev = southbridge_enable, }; Index: LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_early_setup.c =================================================================== --- LinuxBIOSv2.orig/src/southbridge/amd/cs5536/cs5536_early_setup.c 2007-05-07 09:45:40.000000000 -0600 +++ LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_early_setup.c 2007-05-07 14:29:40.000000000 -0600 @@ -33,9 +33,13 @@ /* forward MSR access to CS5536_GLINK_PORT_NUM to CS5536_DEV_NUM */ msr.hi = msr.lo = 0x00000000; if (CS5536_GLINK_PORT_NUM <= 4) { - msr.lo = CS5536_DEV_NUM << (unsigned char)((CS5536_GLINK_PORT_NUM - 1) * 8); + msr.lo = + CS5536_DEV_NUM << (unsigned + char)((CS5536_GLINK_PORT_NUM - 1) * 8); } else { - msr.hi = CS5536_DEV_NUM << (unsigned char)((CS5536_GLINK_PORT_NUM - 5) * 8); + msr.hi = + CS5536_DEV_NUM << (unsigned + char)((CS5536_GLINK_PORT_NUM - 5) * 8); } wrmsr(GLPCI_ExtMSR, msr); } @@ -92,13 +96,13 @@
static void cs5536_setup_power_button(void) { - /* Power Button Setup */ + /* Power Button Setup */ outl(0x40020000, PMS_IO_BASE + 0x40);
/* setup GPIO24, it is the external signal for 5536 vsb_work_aux - ; which controls all voltage rails except Vstandby & Vmem. - ; We need to enable, OUT_AUX1 and OUTPUT_ENABLE in this order. - ; If GPIO24 is not enabled then soft-off will not work. */ + ; which controls all voltage rails except Vstandby & Vmem. + ; We need to enable, OUT_AUX1 and OUTPUT_ENABLE in this order. + ; If GPIO24 is not enabled then soft-off will not work. */ outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUT_AUX1_SELECT); outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
@@ -124,17 +128,17 @@ { msr_t msr; /* ; The UARTs default to enabled. - ; Disable and reset them and configure them later. (SIO init) */ + ; Disable and reset them and configure them later. (SIO init) */ msr = rdmsr(MDD_UART1_CONF); - msr.lo = 1; // reset + msr.lo = 1; // reset wrmsr(MDD_UART1_CONF, msr); - msr.lo = 0; // disabled + msr.lo = 0; // disabled wrmsr(MDD_UART1_CONF, msr);
msr = rdmsr(MDD_UART2_CONF); - msr.lo = 1; // reset + msr.lo = 1; // reset wrmsr(MDD_UART2_CONF, msr); - msr.lo = 0; // disabled + msr.lo = 0; // disabled wrmsr(MDD_UART2_CONF, msr); }
@@ -149,7 +153,6 @@ wrmsr(GLPCI_SB_CTRL, msr); }
- /* see page 412 of the cs5536 companion book */ static void cs5536_setup_onchipuart(void) { @@ -157,11 +160,11 @@
/* Setup early for polling only mode. * 1. Eanble GPIO 8 to OUT_AUX1, 9 to IN_AUX1 - * GPIO LBAR + 0x04, LBAR + 0x10, LBAR + 0x20, LBAR + 34 + * GPIO LBAR + 0x04, LBAR + 0x10, LBAR + 0x20, LBAR + 34 * 2. Enable UART IO space in MDD - * MSR 0x51400014 bit 18:16 + * MSR 0x51400014 bit 18:16 * 3. Enable UART controller - * MSR 0x5140003A bit 0, 1 + * MSR 0x5140003A bit 0, 1 */
/* GPIO8 - UART1_TX */ @@ -178,10 +181,10 @@ /* set address to 3F8 */ msr = rdmsr(MDD_LEG_IO); msr.lo |= 0x7 << 16; - wrmsr(MDD_LEG_IO,msr); + wrmsr(MDD_LEG_IO, msr);
- /* Bit 1 = DEVEN (device enable) - * Bit 4 = EN_BANKS (allow access to the upper banks + /* Bit 1 = DEVEN (device enable) + * Bit 4 = EN_BANKS (allow access to the upper banks */ msr.lo = (1 << 4) | (1 << 1); msr.hi = 0; Index: LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_early_smbus.c =================================================================== --- LinuxBIOSv2.orig/src/southbridge/amd/cs5536/cs5536_early_smbus.c 2007-05-07 09:45:40.000000000 -0600 +++ LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_early_smbus.c 2007-05-07 14:29:40.000000000 -0600 @@ -24,13 +24,12 @@ #define SMBUS_WAIT_UNTIL_DONE_TIMEOUT -3 #define SMBUS_TIMEOUT (1000)
- /* initialization for SMBus Controller */ static void cs5536_enable_smbus(void) {
/* Set SCL freq and enable SMB controller */ - /*outb((0x20 << 1) | SMB_CTRL2_ENABLE, smbus_io_base + SMB_CTRL2);*/ + /*outb((0x20 << 1) | SMB_CTRL2_ENABLE, smbus_io_base + SMB_CTRL2); */ outb((0x7F << 1) | SMB_CTRL2_ENABLE, SMBUS_IO_BASE + SMB_CTRL2);
/* Setup SMBus host controller address to 0xEF */ @@ -43,8 +42,8 @@ /* inb(0x80); */ }
- -static int smbus_wait(unsigned smbus_io_base) { +static int smbus_wait(unsigned smbus_io_base) +{ unsigned long loops = SMBUS_TIMEOUT; unsigned char val;
@@ -54,10 +53,10 @@ if ((val & SMB_STS_SDAST) != 0) break; if (val & (SMB_STS_BER | SMB_STS_NEGACK)) { - /*printk_debug("SMBUS WAIT ERROR %x\n", val);*/ + /*printk_debug("SMBUS WAIT ERROR %x\n", val); */ return SMBUS_ERROR; } - } while(--loops); + } while (--loops); return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT; }
@@ -91,8 +90,8 @@ break; } outb((0x7F << 1) | SMB_CTRL2_ENABLE, smbus_io_base + SMB_CTRL2); - } while(--loops); - return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT; + } while (--loops); + return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT; }
static int smbus_stop_condition(unsigned smbus_io_base) @@ -106,14 +105,15 @@ unsigned char val = inb(smbus_io_base + SMB_CTRL1);
/* if (state) */ - outb(val | SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1); + outb(val | SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1); /* else outb(val & ~SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1); */ return 0; }
-static int smbus_send_slave_address(unsigned smbus_io_base, unsigned char device) +static int smbus_send_slave_address(unsigned smbus_io_base, + unsigned char device) { unsigned char val;
@@ -122,9 +122,8 @@
/* check for bus conflict and NACK */ val = inb(smbus_io_base + SMB_STS); - if (((val & SMB_STS_BER) != 0) || - ((val & SMB_STS_NEGACK) != 0)) { - /* printk_debug("SEND SLAVE ERROR (%x)\n", val);*/ + if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0)) { + /* printk_debug("SEND SLAVE ERROR (%x)\n", val); */ return SMBUS_ERROR; } return smbus_wait(smbus_io_base); @@ -139,8 +138,7 @@
/* check for bus conflict and NACK */ val = inb(smbus_io_base + SMB_STS); - if (((val & SMB_STS_BER) != 0) || - ((val & SMB_STS_NEGACK) != 0)) + if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0)) return SMBUS_ERROR;
return smbus_wait(smbus_io_base); @@ -151,7 +149,9 @@ return inb(smbus_io_base + SMB_SDA); }
-static unsigned char do_smbus_read_byte(unsigned smbus_io_base, unsigned char device, unsigned char address) +static unsigned char do_smbus_read_byte(unsigned smbus_io_base, + unsigned char device, + unsigned char address) { unsigned char error = 0;
@@ -170,7 +170,7 @@ goto err; }
- smbus_ack(smbus_io_base, 1 ); + smbus_ack(smbus_io_base, 1);
if ((smbus_send_command(smbus_io_base, address))) { error = 4; @@ -194,13 +194,12 @@
return smbus_get_result(smbus_io_base);
- -err: + err: print_debug("SMBUS READ ERROR:"); - print_debug_hex8(error); - print_debug(" device:"); - print_debug_hex8(device); - print_debug("\r\n"); + print_debug_hex8(error); + print_debug(" device:"); + print_debug_hex8(device); + print_debug("\r\n"); /* stop, clean up the error, and leave */ smbus_stop_condition(smbus_io_base); outb(inb(smbus_io_base + SMB_STS), smbus_io_base + SMB_STS); @@ -210,6 +209,5 @@
static inline int smbus_read_byte(unsigned device, unsigned address) { - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); + return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } - Index: LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_ide.c =================================================================== --- LinuxBIOSv2.orig/src/southbridge/amd/cs5536/cs5536_ide.c 2007-05-07 09:45:40.000000000 -0600 +++ LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_ide.c 2007-05-07 14:29:40.000000000 -0600 @@ -25,9 +25,9 @@ #include "cs5536.h"
#define IDE_CFG 0x40 - #define CHANEN (1L << 1) - #define PWB (1L << 14) - #define CABLE (1L << 16) +#define CHANEN (1L << 1) +#define PWB (1L << 14) +#define CABLE (1L << 16) #define IDE_DTC 0x48 #define IDE_CAST 0x4C #define IDE_ETC 0x50 @@ -54,15 +54,15 @@ }
static struct device_operations ide_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .enable = 0, + .init = ide_init, + .enable = 0, };
static struct pci_driver ide_driver __pci_driver = { - .ops = &ide_ops, + .ops = &ide_ops, .vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_AMD_CS5536_IDE, }; Index: LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_smbus2.h =================================================================== --- LinuxBIOSv2.orig/src/southbridge/amd/cs5536/cs5536_smbus2.h 2007-05-07 14:29:18.000000000 -0600 +++ LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_smbus2.h 2007-05-07 14:29:40.000000000 -0600 @@ -62,13 +62,13 @@ #define SMBUS_TIMEOUT (100*1000*10) #define SMBUS_STATUS_MASK 0xfbff
- static void smbus_delay(void) { inb(0x80); }
-static int smbus_wait(unsigned smbus_io_base) { +static int smbus_wait(unsigned smbus_io_base) +{ unsigned long loops = SMBUS_TIMEOUT; unsigned char val;
@@ -81,13 +81,14 @@ printk_debug("SMBUS WAIT ERROR %x\n", val); return SMBUS_ERROR; } - } while(--loops); + } while (--loops);
outb(0, smbus_io_base + SMB_STS); return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT; }
-static int smbus_write(unsigned smbus_io_base, unsigned char byte) { +static int smbus_write(unsigned smbus_io_base, unsigned char byte) +{
outb(byte, smbus_io_base + SMB_SDA); return smbus_wait(smbus_io_base); @@ -122,17 +123,17 @@ if ((val & SMB_CTRL1_STOP) == 0) { break; } - } while(--loops); - return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT; + } while (--loops); + return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT;
/* Make sure everything is cleared and ready to go */
val = inb(smbus_io_base + SMB_CTRL1); outb(val & ~(SMB_CTRL1_STASTRE | SMB_CTRL1_NMINTE), - smbus_io_base + SMB_CTRL1); + smbus_io_base + SMB_CTRL1);
outb(SMB_STS_BER | SMB_STS_NEGACK | SMB_STS_STASTR, - smbus_io_base + SMB_STS); + smbus_io_base + SMB_STS);
val = inb(smbus_io_base + SMB_CTRL_STS); outb(val | SMB_CSTS_BB, smbus_io_base + SMB_CTRL_STS); @@ -159,7 +160,8 @@ return 0; }
-static int smbus_send_slave_address(unsigned smbus_io_base, unsigned char device) +static int smbus_send_slave_address(unsigned smbus_io_base, + unsigned char device) { unsigned char val;
@@ -168,8 +170,7 @@
/* check for bus conflict and NACK */ val = inb(smbus_io_base + SMB_STS); - if (((val & SMB_STS_BER) != 0) || - ((val & SMB_STS_NEGACK) != 0)) { + if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0)) { printk_debug("SEND SLAVE ERROR (%x)\n", val); return SMBUS_ERROR; } @@ -178,22 +179,21 @@
static int smbus_send_command(unsigned smbus_io_base, unsigned char command) { - unsigned char val; + unsigned char val;
/* send the command */ outb(command, smbus_io_base + SMB_SDA);
/* check for bus conflict and NACK */ val = inb(smbus_io_base + SMB_STS); - if (((val & SMB_STS_BER) != 0) || - ((val & SMB_STS_NEGACK) != 0)) + if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0)) return SMBUS_ERROR;
return smbus_wait(smbus_io_base); }
static void _doread(unsigned smbus_io_base, unsigned char device, - unsigned char address, unsigned char *data, int count) + unsigned char address, unsigned char *data, int count) { int ret; int index = 0; @@ -207,7 +207,7 @@ if ((ret = smbus_start_condition(smbus_io_base))) goto err;
- index++; /* 2 */ + index++; /* 2 */ if ((ret = smbus_send_slave_address(smbus_io_base, device))) goto err;
@@ -226,7 +226,7 @@ if ((ret = smbus_send_slave_address(smbus_io_base, device | 0x01))) goto err;
- while(count) { + while (count) { /* Set the ACK if this is the next to last byte */ smbus_ack(smbus_io_base, (count == 2) ? 1 : 0);
@@ -249,12 +249,12 @@
return;
- err: + err: printk_debug("SMBUS READ ERROR (%d): %d\n", index, ret); }
static unsigned char do_smbus_read_byte(unsigned smbus_io_base, - unsigned char device, + unsigned char device, unsigned char address) { unsigned char val = 0; @@ -263,16 +263,18 @@ }
static unsigned short do_smbus_read_word(unsigned smbus_io_base, - unsigned char device, unsigned char address) + unsigned char device, + unsigned char address) { unsigned short val = 0; - _doread(smbus_io_base, device, address, (unsigned char *) &val, - sizeof(val)); + _doread(smbus_io_base, device, address, (unsigned char *)&val, + sizeof(val)); return val; }
static int _dowrite(unsigned smbus_io_base, unsigned char device, - unsigned char address, unsigned char *data, int count) { + unsigned char address, unsigned char *data, int count) +{
int ret;
@@ -288,7 +290,7 @@ if ((ret = smbus_send_command(smbus_io_base, address))) goto err;
- while(count) { + while (count) { if ((ret = smbus_write(smbus_io_base, *data++))) goto err; count--; @@ -297,21 +299,21 @@ smbus_stop_condition(smbus_io_base); return 0;
- err: + err: printk_debug("SMBUS WRITE ERROR: %d\n", ret); return -1; }
- static int do_smbus_write_byte(unsigned smbus_io_base, unsigned char device, - unsigned char address, unsigned char data) + unsigned char address, unsigned char data) { return _dowrite(smbus_io_base, device, address, - (unsigned char *) &data, 1); + (unsigned char *)&data, 1); }
-static int do_smbus_write_word(unsigned smbus_io_base, unsigned char device, unsigned char address, - unsigned short data) +static int do_smbus_write_word(unsigned smbus_io_base, unsigned char device, + unsigned char address, unsigned short data) { - return _dowrite(smbus_io_base, device ,address, (unsigned char *) &data, 2); + return _dowrite(smbus_io_base, device, address, (unsigned char *)&data, + 2); } Index: LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.h =================================================================== --- LinuxBIOSv2.orig/src/southbridge/amd/cs5536/cs5536.h 2007-05-07 09:45:40.000000000 -0600 +++ LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.h 2007-05-07 14:29:40.000000000 -0600 @@ -23,21 +23,21 @@ #define Cx5536_ID ( 0x208F1022)
/* SouthBridge Equates */ -#define CS5536_GLINK_PORT_NUM 0x02 /* port of the SouthBridge */ -#define NB_PCI ((2 << 29) + (4 << 26)) /* NB GLPCI is in the same location on all Geodes. */ +#define CS5536_GLINK_PORT_NUM 0x02 /* port of the SouthBridge */ +#define NB_PCI ((2 << 29) + (4 << 26)) /* NB GLPCI is in the same location on all Geodes. */ #define MSR_SB ((CS5536_GLINK_PORT_NUM << 23) + NB_PCI) /* address to the SouthBridge */ -#define SB_SHIFT 20 /* 29 -> 26 -> 23 -> 20...... When making a SB address uses this shift. */ +#define SB_SHIFT 20 /* 29 -> 26 -> 23 -> 20...... When making a SB address uses this shift. */
-#define CS5536_DEV_NUM 0x0F /* default PCI device number for CS5536 */ +#define CS5536_DEV_NUM 0x0F /* default PCI device number for CS5536 */ #define SMBUS_IO_BASE 0x6000 #define GPIO_IO_BASE 0x6100 #define MFGPT_IO_BASE 0x6200 #define ACPI_IO_BASE 0x9C00 #define PMS_IO_BASE 0x9D00
-#define CS5535_IDSEL 0x02000000 // IDSEL = AD25, device #15 +#define CS5535_IDSEL 0x02000000 // IDSEL = AD25, device #15 #define CHIPSET_DEV_NUM 15 -#define IDSEL_BASE 11 // bit 11 = device 1 +#define IDSEL_BASE 11 // bit 11 = device 1
/* Cs5536 as follows. */ /* SB_GLIU */ @@ -50,8 +50,8 @@ /* port6 - USB Controller #1 */ /* port7 - GLCP */
-#define MSR_SB_GLIU ((9 << 14) + MSR_SB) /* 51024xxx or 510*xxxx - fake out just like GL0 on CPU. */ -#define MSR_SB_GLPCI (MSR_SB) /* 5100xxxx - don't go to the GLIU */ +#define MSR_SB_GLIU ((9 << 14) + MSR_SB) /* 51024xxx or 510*xxxx - fake out just like GL0 on CPU. */ +#define MSR_SB_GLPCI (MSR_SB) /* 5100xxxx - don't go to the GLIU */ #define MSR_SB_USB2 ((2 << SB_SHIFT) + MSR_SB) /* 5120xxxx */ #define MSR_SB_ATA ((3 << SB_SHIFT) + MSR_SB) /* 5130xxxx */ #define MSR_SB_MDD ((4 << SB_SHIFT) + MSR_SB) /* 5140xxxx, a.k.a. DIVIL = Diverse Integrated Logic device */ @@ -78,13 +78,13 @@ /* */ #define USB2_SB_GLD_MSR_CAP (MSR_SB_USB2 + 0x00) #define USB2_SB_GLD_MSR_CONF (MSR_SB_USB2 + 0x01) - #define USB2_UPPER_SSDEN_SET (1 << 3 ) /* Bit 35 */ +#define USB2_UPPER_SSDEN_SET (1 << 3 ) /* Bit 35 */ #define USB2_SB_GLD_MSR_PM (MSR_SB_USB2 + 0x04) #define USB2_SB_GLD_MSR_DIAG (MSR_SB_USB2 + 0x05) #define USB2_SB_GLD_MSR_OHCI_BASE (MSR_SB_USB2 + 0x08) #define USB2_SB_GLD_MSR_EHCI_BASE (MSR_SB_USB2 + 0x09) #define USB2_SB_GLD_MSR_DEVCTL_BASE (MSR_SB_USB2 + 0x0A) -#define USB2_SB_GLD_MSR_UOC_BASE (MSR_SB_USB2 + 0x0B) /* Option controller base */ +#define USB2_SB_GLD_MSR_UOC_BASE (MSR_SB_USB2 + 0x0B) /* Option controller base */
/* */ /* ATA*/ @@ -203,7 +203,6 @@ #define MDD_RTC_MONA_IND (MSR_SB_MDD + 0x056) #define MDD_RTC_CENTURY_OFFSET (MSR_SB_MDD + 0x057)
- /* ***********************************************************/ /* LBUS Device Equates - */ /* ***********************************************************/ @@ -321,7 +320,6 @@ #define GPIOH_30_CLEAR (1 << 30) #define GPIOH_31_CLEAR (1 << 31)
- /* GPIO LOW Bank Bit Registers*/ #define GPIOL_OUTPUT_VALUE (0x00) #define GPIOL_OUTPUT_ENABLE (0x04) @@ -439,7 +437,6 @@ #define PM_AWKD (0x50) #define PM_SSC (0x54)
- /* FLASH device macros */ #define FLASH_TYPE_NONE 0 /* No flash device installed */ #define FLASH_TYPE_NAND 1 /* NAND device */ @@ -467,5 +464,4 @@ #define FLASH_IO_128B 0x0000FF80 #define FLASH_IO_256B 0x0000FF00
- -#endif /* _CS5536_H */ +#endif /* _CS5536_H */
-- Jordan Crouse Senior Linux Engineer Advanced Micro Devices, Inc. <www.amd.com/embeddedprocessors>
On Mon, May 07, 2007 at 02:38:42PM -0600, jordan.crouse@amd.com wrote:
Doing my part to keep the list traffic up, here are patches to fix the licenses on the LX northbridge, 5536 southbridge, and norwich mainboard directory. These are followed up with patches to clean the whitespace and indentation on all LX directories. This should bring everything up to code (no pun intended).
Thanks a lot! I'll go over these and commit one by one. The coding style patches might need some adaptions. I guess you used 'indent'? That cannot fully be trusted, so some manual fixup is necessary -- I'll do that before committing.
Uwe.
* jordan.crouse@amd.com jordan.crouse@amd.com [070507 22:38]:
Doing my part to keep the list traffic up, here are patches to fix the licenses on the LX northbridge, 5536 southbridge, and norwich mainboard directory. These are followed up with patches to clean the whitespace and indentation on all LX directories. This should bring everything up to code (no pun intended).
Dear Jordan,
Thank you very much. I checked all of the missing patches in now, including some minor massaging in some places.
Sorry for the long delay.
We are all looking forward to your next contributions.
Best wishes,
Stefan
-
jordan.crouse＠amd.com -
Stefan Reinauer -
Uwe Hermann