Hi, If I theoretically had a flash chip that was larger than 128Mb, it requires 3-4 byte addressing.
Does / could coreboot support such large memory, or would the limitation live somewhere else in the system?
Cheers, R
On Thu, Mar 28, 2019 at 06:55:50AM +0800, Rafael Send wrote:
Hi, If I theoretically had a flash chip that was larger than 128Mb, it requires 3-4 byte addressing.
Does / could coreboot support such large memory, or would the limitation live somewhere else in the system?
My guess is it depends first on the platform: If the integrated flash controller is not just plain SPI it has to support the 4 byte mode. Second on the coreboot driver: I've not checked if anything is implemented yet but I don't see limitations on the software side.
Hope this helps,
Julien VdG
Cheers, R
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Hi, Where would I generally find information about what controls the flash chip? I don't actually own the board in question (yet), so I can't do any hardware inspection, and I don't known enough about computer architecture on the hardware level to know this off the top of my head...
Thanks, R
On Thu, Mar 28, 2019, 3:08 AM Julien Viard de Galbert julien@vdg.name wrote:
On Thu, Mar 28, 2019 at 06:55:50AM +0800, Rafael Send wrote:
Hi, If I theoretically had a flash chip that was larger than 128Mb, it
requires
3-4 byte addressing.
Does / could coreboot support such large memory, or would the limitation live somewhere else in the system?
My guess is it depends first on the platform: If the integrated flash controller is not just plain SPI it has to support the 4 byte mode. Second on the coreboot driver: I've not checked if anything is implemented yet but I don't see limitations on the software side.
Hope this helps,
Julien VdG
Cheers, R
coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
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Hello Rafael,
On 28.03.19 17:12, Rafael Send wrote:
Where would I generally find information about what controls the flash chip?
in the datasheet of the chip that is connected to the BIOS flash. What chip that is, is not always easy to answer. If you don't have access to the board's schematics, visual inspection might help.
What Peter told us, btw., applies only to x86 platforms. If you target x86, coreboot support for more than 16MiB will be hard, because that is the limit what is memory mapped. To access more than 16MiB on x86, you'd need a SPI driver (which coreboot has) and use that to access files (which is the harder part, because coreboot on x86 is special).
Please tell us more about your target hardware and use case. Usually, you don't need that much flash for coreboot. So there may be other options to consider (e.g. a SPI driver in your payload).
Nico
Hi Nico- Can you clarify what you mean by coreboot on x86 is special?
Does that mean even if 3-byte addresses are supported (which would allow addressing more than 128Mb / 16MiB of memory), it specifically doesn't work on x86?
I'm looking at the coreboot port that was done for the Thinkpad X210, which is a Chinese custom motherboard that updates the X201 form factor with an i7-8650U / i7-8550u / i5-8250U CPU, and just for the hell of it I'm wondering what the largest piece of BIOS memory is I can get on there. Hardware-wise, I can get up to 512Mb / 64MiB into the chip form factor. If we can address it, that opens up interesting possibilities for embedding full OS distributions there (such as my previous question about TinyCore).
Gruß, R
On Fri, Mar 29, 2019 at 10:10 AM Nico Huber nico.h@gmx.de wrote:
Hello Rafael,
On 28.03.19 17:12, Rafael Send wrote:
Where would I generally find information about what controls the flash
chip?
in the datasheet of the chip that is connected to the BIOS flash. What chip that is, is not always easy to answer. If you don't have access to the board's schematics, visual inspection might help.
What Peter told us, btw., applies only to x86 platforms. If you target x86, coreboot support for more than 16MiB will be hard, because that is the limit what is memory mapped. To access more than 16MiB on x86, you'd need a SPI driver (which coreboot has) and use that to access files (which is the harder part, because coreboot on x86 is special).
Please tell us more about your target hardware and use case. Usually, you don't need that much flash for coreboot. So there may be other options to consider (e.g. a SPI driver in your payload).
Nico
On 29.03.19 19:08, Rafael Send wrote:
Hi Nico- Can you clarify what you mean by coreboot on x86 is special?
on x86, there are two ways to access a SPI flash chip: 1. you can ask the SPI controller via a register based interface to access the flash chip. 2. by default, the flash chip contents of the BIOS region* of the flash chip is memory mapped (i.e. you can read from it just like you read from RAM).
1. may support >16MiB chips/regions.
2. is usually limited to 8MiB or 16MiB depending on the chipset. I would guess 16MiB in your case, but I can't promise.
2. is used by coreboot. However, with some additional code you can also use 1.
*Intel shares the flash chip with other chipset components, e.g. ME firmware.
Does that mean even if 3-byte addresses are supported (which would allow addressing more than 128Mb / 16MiB of memory), it specifically doesn't work on x86?
No. The x86 thing is just a current software limitation that can be lifted. But still, there may be chips (e.g. EC) between the flash and the Intel chipset that may have their own limits.
I'm looking at the coreboot port that was done for the Thinkpad X210, which is a Chinese custom motherboard that updates the X201 form factor with an i7-8650U / i7-8550u / i5-8250U CPU, and just for the hell of it I'm wondering what the largest piece of BIOS memory is I can get on there. Hardware-wise, I can get up to 512Mb / 64MiB into the chip form factor. If we can address it, that opens up interesting possibilities for embedding full OS distributions there (such as my previous question about TinyCore).
The chipset supports up to two chips of 64MiB each. But I don't know if the flash is directly connected.
In case of a full OS in flash, I would suggest a SPI driver in the OS kernel, anyway. Otherwise, you'd have to let coreboot load a lot of data from flash at once and that would slow it down (but that doesn't have to be a concern).
Nico
'Tag- Good information.
However, as I'm an EE not a SW engineer I wouldn't be able to make any modifications to coreboot code myself (at least not without a lot of time & study). Hardware modifications on the other hand are easier for me.
Also, I was incorrect about the largest part I can get in the correct footprint. It's actually "only" 256Mb / 32MiB.
R
On Fri, Mar 29, 2019 at 12:03 PM Nico Huber nico.h@gmx.de wrote:
On 29.03.19 19:08, Rafael Send wrote:
Hi Nico- Can you clarify what you mean by coreboot on x86 is special?
on x86, there are two ways to access a SPI flash chip: 1. you can ask the SPI controller via a register based interface to access the flash chip. 2. by default, the flash chip contents of the BIOS region* of the flash chip is memory mapped (i.e. you can read from it just like you read from RAM).
may support >16MiB chips/regions.
is usually limited to 8MiB or 16MiB depending on the chipset. I
would guess 16MiB in your case, but I can't promise.
- is used by coreboot. However, with some additional code you can
also use 1.
*Intel shares the flash chip with other chipset components, e.g. ME firmware.
Does that mean even if 3-byte addresses are supported (which would allow addressing more than 128Mb / 16MiB of memory), it specifically doesn't
work
on x86?
No. The x86 thing is just a current software limitation that can be lifted. But still, there may be chips (e.g. EC) between the flash and the Intel chipset that may have their own limits.
I'm looking at the coreboot port that was done for the Thinkpad X210,
which
is a Chinese custom motherboard that updates the X201 form factor with an i7-8650U / i7-8550u / i5-8250U CPU, and just for the hell of it I'm wondering what the largest piece of BIOS memory is I can get on there. Hardware-wise, I can get up to 512Mb / 64MiB into the chip form factor.
If
we can address it, that opens up interesting possibilities for embedding full OS distributions there (such as my previous question about
TinyCore).
The chipset supports up to two chips of 64MiB each. But I don't know if the flash is directly connected.
In case of a full OS in flash, I would suggest a SPI driver in the OS kernel, anyway. Otherwise, you'd have to let coreboot load a lot of data from flash at once and that would slow it down (but that doesn't have to be a concern).
Nico
Rafael Send wrote:
If I theoretically had a flash chip that was larger than 128Mb, it requires 3-4 byte addressing.
The de facto standard commands all use 3 byte addresses.
Does / could coreboot support such large memory, or would the limitation live somewhere else in the system?
coreboot doesn't need to know about SPI. (It does, e.g. to enable block locks for some chips, but that's unrelated to booting.)
The platform hardware exposes the SPI flash mapped at top of 4 GByte of physical address space.
The platform hardware would have to know to use 4 byte address commands.
I don't know if any platforms do - I guess that they don't.
//Peter
-
Julien Viard de Galbert -
Nico Huber -
Peter Stuge -
Rafael Send