I am using FC10. GCC 4.3.2.
...............................
make[1]: Leaving directory `/home/baozheng/LinuxBIOS/coreboot-v2-org/util/cbfstool'
make -C fallback coreboot.rom
cat: ../../VERSION: No such file or directory
make[1]: Entering directory `/home/baozheng/LinuxBIOS/coreboot-v2-org/targets/amd/serengeti_cheetah_ fam10/serengeti_cheetah_fam10/fallback'
gcc -m32 -x assembler-with-cpp -DASSEMBLY -E -I/home/baozheng/LinuxBIOS/coreboot-v2-org/src/include -I/home/baozheng/LinuxBIOS/coreboot-v2-org/src/arch/i386/include -I/usr/lib/gcc/i386-redhat-linux/4.3.2/include -include /home/baozheng/LinuxBIOS/coreboot-v2-org/targets/amd/serengeti_cheetah_f am10/serengeti_cheetah_fam10/fallback/settings.h -I/home/baozheng/LinuxBIOS/coreboot-v2-org/util/x86emu/include -I. -I/home/baozheng/LinuxBIOS/coreboot-v2-org/src crt0.S > crt0.s.new && mv crt0.s.new crt0.s
gcc -m32 -Wa,-acdlns -c -o crt0.o crt0.s >crt0.disasm
gcc -m32 -Wl,--build-id=none -nostdlib -nostartfiles -static -o coreboot -T ldscript.ld crt0.o src/lib/lzma.o src/lib/cbfs.o src/arch/i386/lib/cbfs_and_run.o src/lib/uart8250.o src/lib/memcmp.o src/lib/memcpy.o src/lib/memset.o src/console/vtxprintf.o src/arch/i386/lib/printk_init.o
nm -n coreboot | sort > coreboot.map
objdump -dS coreboot > coreboot.disasm
objcopy --gap-fill 0xff -O binary coreboot coreboot.strip
PAYLOAD=payload; if [ 1 -eq 1 ]; then PAYLOAD=/dev/null; touch cbfs-support; fi; ./buildrom coreboot.strip coreboot.rom $PAYLOAD 0x7f000 0x7f000
Payload: 0 coreboot: 520192 ROM size: 520192 Left space: 0
if [ 0 -eq 1 -a 1 -eq 1 ]; then echo l > cbfs-support; fi
make[1]: Leaving directory `/home/baozheng/LinuxBIOS/coreboot-v2-org/targets/amd/serengeti_cheetah_ fam10/serengeti_cheetah_fam10/fallback'
make -C failover coreboot.rom
cat: ../../VERSION: No such file or directory
make[1]: Entering directory `/home/baozheng/LinuxBIOS/coreboot-v2-org/targets/amd/serengeti_cheetah_ fam10/serengeti_cheetah_fam10/failover'
gcc -m32 -x assembler-with-cpp -DASSEMBLY -E -I/home/baozheng/LinuxBIOS/coreboot-v2-org/src/include -I/home/baozheng/LinuxBIOS/coreboot-v2-org/src/arch/i386/include -I/usr/lib/gcc/i386-redhat-linux/4.3.2/include -include /home/baozheng/LinuxBIOS/coreboot-v2-org/targets/amd/serengeti_cheetah_f am10/serengeti_cheetah_fam10/failover/settings.h -I/home/baozheng/LinuxBIOS/coreboot-v2-org/util/x86emu/include -I. -I/home/baozheng/LinuxBIOS/coreboot-v2-org/src crt0.S > crt0.s.new && mv crt0.s.new crt0.s
gcc -m32 -Wa,-acdlns -c -o crt0.o crt0.s >crt0.disasm
gcc -m32 -Wl,--build-id=none -nostdlib -nostartfiles -static -o coreboot -T ldscript.ld crt0.o src/lib/uart8250.o src/lib/memcmp.o src/lib/memcpy.o src/lib/memset.o src/console/vtxprintf.o src/arch/i386/lib/printk_init.o
nm -n coreboot | sort > coreboot.map
objdump -dS coreboot > coreboot.disasm
objcopy --gap-fill 0xff -O binary coreboot coreboot.strip
cp coreboot.strip coreboot.rom
make[1]: Leaving directory `/home/baozheng/LinuxBIOS/coreboot-v2-org/targets/amd/serengeti_cheetah_ fam10/serengeti_cheetah_fam10/failover'
rm -f ./coreboot.rom
cat fallback/coreboot.rom failover/coreboot.rom > ./coreboot.rom.bootblock
./cbfs/cbfstool ./coreboot.rom create 1048576 528384 ./coreboot.rom.bootblock
./cbfs/cbfstool ./coreboot.rom add-payload ../payload.elf fallback/payload
make: *** [coreboot.rom] Segmentation fault
make: *** Deleting file `coreboot.rom'
Am Dienstag, den 15.09.2009, 11:00 +0800 schrieb Bao, Zheng:
./cbfs/cbfstool ./coreboot.rom add-payload ../payload.elf fallback/payload
make: *** [coreboot.rom] Segmentation fault
r4634 fixes segmentation faults when the file cannot be found. "../payload.elf" is suspicious - are you sure that is the right path?
If you're certain that this file should exist at that place, and if the segmentation fault still occurs with r4634, some more information is necessary: - which payload is this (so I can try to reproduce it, a copy of the payload binary would help the most) - is your build machine 32bit or 64bit?
Regards, Patrick
It was fixed.
Zheng
-----Original Message----- From: Patrick Georgi [mailto:patrick@georgi-clan.de] Sent: Tuesday, September 15, 2009 4:26 PM To: Bao, Zheng Cc: coreboot@coreboot.org Subject: Re: [coreboot] r4633 building error of serengeti_cheetah_fam10
Am Dienstag, den 15.09.2009, 11:00 +0800 schrieb Bao, Zheng:
./cbfs/cbfstool ./coreboot.rom add-payload ../payload.elf fallback/payload
make: *** [coreboot.rom] Segmentation fault
r4634 fixes segmentation faults when the file cannot be found. "../payload.elf" is suspicious - are you sure that is the right path?
If you're certain that this file should exist at that place, and if the segmentation fault still occurs with r4634, some more information is necessary: - which payload is this (so I can try to reproduce it, a copy of the payload binary would help the most) - is your build machine 32bit or 64bit?
Regards, Patrick
The latest filo crashes if CBFS is enabled.
The CBFS can not work on my Fam10 board for a long time. I have to disable it all the time.
Can you guys test it?
Zheng
Log: ......................... PCI: 00:18.4 links 0 child on link 0 NULL Done allocating resources. Enabling resources... PCI: 00:18.0 cmd <- 00 PCI: 00:00.0 subsystem <- 1022/2b80 PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 bridge ctrl <- 000b PCI: 00:01.0 cmd <- 07 PCI: 01:05.0 subsystem <- 1022/2b80 PCI: 01:05.0 cmd <- 03 PCI: 00:04.0 bridge ctrl <- 0003 PCI: 00:04.0 cmd <- 00 PCI: 00:09.0 bridge ctrl <- 0003 PCI: 00:09.0 cmd <- 00 PCI: 00:0a.0 bridge ctrl <- 0003 PCI: 00:0a.0 cmd <- 06 PCI: 04:00.0 cmd <- 02 PCI: 00:11.0 cmd <- 03 PCI: 00:12.0 subsystem <- 1022/2b80 PCI: 00:12.0 cmd <- 02 PCI: 00:12.1 subsystem <- 1022/2b80 PCI: 00:12.1 cmd <- 02 PCI: 00:12.2 subsystem <- 1022/2b80 PCI: 00:12.2 cmd <- 02 PCI: 00:13.0 subsystem <- 1022/2b80 PCI: 00:13.0 cmd <- 02 PCI: 00:13.1 subsystem <- 1022/2b80 PCI: 00:13.1 cmd <- 02 PCI: 00:13.2 subsystem <- 1022/2b80 PCI: 00:13.2 cmd <- 02 PCI: 00:14.0 subsystem <- 1022/2b80 PCI: 00:14.0 cmd <- 403 PCI: 00:14.1 subsystem <- 1022/2b80 PCI: 00:14.1 cmd <- 01 PCI: 00:14.2 subsystem <- 1022/2b80 PCI: 00:14.2 cmd <- 02 PCI: 00:14.3 subsystem <- 1022/2b80 PCI: 00:14.3 cmd <- 0f sb700 lpc decode:PNP: 002e.1, base=0x000003f8, end=0x000003ff sb700 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000067 sb700 lpc decode:PNP: 002e.5, base=0x00000064, end=0x0000006b PNP: 002e.6 missing enable_resources PCI: 00:14.4 bridge ctrl <- 0003 PCI: 00:14.4 cmd <- 07 PCI: 05:05.0 cmd <- 02 PCI: 00:14.5 subsystem <- 1022/2b80 PCI: 00:14.5 cmd <- 02 PCI: 00:18.1 subsystem <- 1022/2b80 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1022/2b80 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 subsystem <- 1022/2b80 PCI: 00:18.4 cmd <- 00 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init start_eip=0x0000e000, offset=0x00200000, code_size=0x0000005b Initializing CPU #0 CPU: vendor AMD device 100f42 CPU: family 10, model 04, stepping 02 nodeid = 00, coreid = 00 Enabling cache
Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 1024MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 1024MB, range: 256MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 2, base: 768MB, range: 256MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs
MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled
Setting up local apic... apic_id: 0x00 done. CPU model: AMD Processor model unknown siblings = 03, CPU #0 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 2. Sending STARTUP #1 to 1. After apic_write. Initializing CPU #1 Startup point 1. Waiting for send to finish... +CPU: vendor AMD device 100f42 Sending STARTUP #2 to 1. After apic_write. CPU: family 10, model 04, stepping 02 Startup point 1. Waiting for send to finish... +nodeid = 00, coreid = 01 After Startup. Enabling cache Asserting INIT.
Setting fixed MTRRs(0-88) type: UC Waiting for send to finish... +Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Deasserting INIT. Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM Waiting for send to finish... +#startup loops: 2. Sending STARTUP #1 to 2. After apic_write. DONE fixed MTRRs Startup point 1. Waiting for send to finish... +Setting variable MTRR 0, base: 0MB, range: 1024MB, type WB Sending STARTUP #2 to 2. After apic_write. ADDRESS_MASK_HIGH=0xffff Startup point 1. Waiting for send to finish... +Setting variable MTRR 1, base: 1024MB, range: 256MB, type WB After Startup. ADDRESS_MASK_HIGH=0xffff Asserting INIT. Setting variable MTRR 2, base: 768MB, range: 256MB, type UC Waiting for send to finish... +ADDRESS_MASK_HIGH=0xffff Initializing CPU #2 DONE variable MTRRs Clear out the extra MTRR's CPU: vendor AMD device 100f42 Deasserting INIT. call enable_var_mtrr() Waiting for send to finish... +Leave x86_setup_var_mtrrs #startup loops: 2. Sending STARTUP #1 to 3. After apic_write.
MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled
Startup point 1. Waiting for send to finish... +Setting up local apic...Sending STARTUP #2 to 3. After apic_write. apic_id: 0x01 done. Startup point 1. Waiting for send to finish... +CPU model: AMD Processor model unknown After Startup. Waiting for 3 CPUS to stop siblings = 03, CPU: family 10, model 04, stepping 02 CPU #1 initialized Initializing CPU #3 Waiting for 2 CPUS to stop nodeid = 00, coreid = 02 CPU: vendor AMD device 100f42 Enabling cache CPU: family 10, model 04, stepping 02
Setting fixed MTRRs(0-88) type: UC nodeid = 00, coreid = 03 Enabling cache
Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM Setting variable MTRR 0, base: 0MB, range: 1024MB, type WB DONE fixed MTRRs ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 0, base: 0MB, range: 1024MB, type WB Setting variable MTRR 1, base: 1024MB, range: 256MB, type WB ADDRESS_MASK_HIGH=0xffff ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 1024MB, range: 256MB, type WB Setting variable MTRR 2, base: 768MB, range: 256MB, type UC ADDRESS_MASK_HIGH=0xffff ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 2, base: 768MB, range: 256MB, type UC DONE variable MTRRs Clear out the extra MTRR's ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs call enable_var_mtrr()
MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled
Leave x86_setup_var_mtrrs Setting up local apic... MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled
apic_id: 0x02 done. Setting up local apic...CPU model: AMD Processor model unknown apic_id: 0x03 done. siblings = 03, CPU model: AMD Processor model unknown CPU #2 initialized siblings = 03, Waiting for 1 CPUS to stop CPU #3 initialized All AP CPUs stopped PCI: 00:18.0 init PCI: 00:00.0 init pcie_init in rs780_ht.c PCI: 01:05.0 init internal_gfx_pci_dev_init device=9615, vendor=1002, vga_rom_address=0xfff00000. BTDC: MEMCLK = 0 BTDC: NB HT speed = 1c750b60. BTDC: CPU HT speed = 8ff50b60. BTDC: HT width = 11110020. Check CBFS header at fff7efe0 magic is 4f524243 Found CBFS header at fff7efe0 Check fallback/payload CBFS: follow chain: fff00000 + 38 + 15a48 + align -> fff15a80 Check fallback/coreboot_ram CBFS: follow chain: fff15a80 + 38 + 3801c + align -> fff4db00 Check CBFS: follow chain: fff4db00 + 28 + 314b8 + align -> fff7f000 CBFS: Could not find file pci1002,9615.rom In cbfs, rom address for PCI: 01:05.0 = 00000000 On mainboard, rom address for PCI: 01:05.0 = fff00000 PCI Expansion ROM, signature 0x414c, INIT size 0xa400, data ptr 0x6166 Incorrect Expansion ROM Header Signature 414c PCI: 00:11.0 init sata_bar0=2020 sata_bar1=2040 sata_bar2=2028 sata_bar3=2044 sata_bar4=2000 sata_bar5=d0309000 SATA port 0 status = 13 drive detection done after 0 ms Primary Master device is ready after 1 tries SATA port 1 status = 0 No Primary Slave SATA drive on Slot1 SATA port 2 status = 0 No Secondary Master SATA drive on Slot2 SATA port 3 status = 0 No Secondary Slave SATA drive on Slot3 PCI: 00:12.0 init PCI: 00:12.1 init PCI: 00:12.2 init usb2_bar0=d0309400 PCI: 00:13.0 init PCI: 00:13.1 init PCI: 00:13.2 init usb2_bar0=d0309500 PCI: 00:14.5 init PCI: 00:14.0 init sm_init(). lapicid = 0000000000000000 set power on after power fail ++++++++++no set NMI+++++ RTC Init Invalid CMOS LB checksum sm_init() end PCI: 00:14.1 init Check CBFS header at fff7efe0 magic is 4f524243 Found CBFS header at fff7efe0 Check fallback/payload CBFS: follow chain: fff00000 + 38 + 15a48 + align -> fff15a80 Check fallback/coreboot_ram CBFS: follow chain: fff15a80 + 38 + 3801c + align -> fff4db00 Check CBFS: follow chain: fff4db00 + 28 + 314b8 + align -> fff7f000 CBFS: Could not find file pci1002,439c.rom In cbfs, rom address for PCI: 00:14.1 = 00000000 On mainboard, rom address for PCI: 00:14.1 = 0 PCI: 00:14.2 init base = d0300000 codec_mask = 08 PCI: 00:14.3 init PNP: 002e.1 init PNP: 002e.5 init Keyboard init... Keyboard controller output buffer result timeout Timeout while enabling keyboard. (No keyboard present?) Keyboard controller output buffer result timeout Timeout waiting for keyboard after reset. PCI: 00:14.4 init PCI: 00:18.1 init Check CBFS header at fff7efe0 magic is 4f524243 Found CBFS header at fff7efe0 Check fallback/payload CBFS: follow chain: fff00000 + 38 + 15a48 + align -> fff15a80 Check fallback/coreboot_ram CBFS: follow chain: fff15a80 + 38 + 3801c + align -> fff4db00 Check CBFS: follow chain: fff4db00 + 28 + 314b8 + align -> fff7f000 CBFS: Could not find file pci1022,1201.rom In cbfs, rom address for PCI: 00:18.1 = 00000000 On mainboard, rom address for PCI: 00:18.1 = 0 PCI: 00:18.2 init Check CBFS header at fff7efe0 magic is 4f524243 Found CBFS header at fff7efe0 Check fallback/payload CBFS: follow chain: fff00000 + 38 + 15a48 + align -> fff15a80 Check fallback/coreboot_ram CBFS: follow chain: fff15a80 + 38 + 3801c + align -> fff4db00 Check CBFS: follow chain: fff4db00 + 28 + 314b8 + align -> fff7f000 CBFS: Could not find file pci1022,1202.rom In cbfs, rom address for PCI: 00:18.2 = 00000000 On mainboard, rom address for PCI: 00:18.2 = 0 PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 00:18.4 init Check CBFS header at fff7efe0 magic is 4f524243 Found CBFS header at fff7efe0 Check fallback/payload CBFS: follow chain: fff00000 + 38 + 15a48 + align -> fff15a80 Check fallback/coreboot_ram CBFS: follow chain: fff15a80 + 38 + 3801c + align -> fff4db00 Check CBFS: follow chain: fff4db00 + 28 + 314b8 + align -> fff7f000 CBFS: Could not find file pci1022,1204.rom In cbfs, rom address for PCI: 00:18.4 = 00000000 On mainboard, rom address for PCI: 00:18.4 = 0 PCI: 04:00.0 init Check CBFS header at fff7efe0 magic is 4f524243 Found CBFS header at fff7efe0 Check fallback/payload CBFS: follow chain: fff00000 + 38 + 15a48 + align -> fff15a80 Check fallback/coreboot_ram CBFS: follow chain: fff15a80 + 38 + 3801c + align -> fff4db00 Check CBFS: follow chain: fff4db00 + 28 + 314b8 + align -> fff7f000 CBFS: Could not find file pci14e4,167b.rom In cbfs, rom address for PCI: 04:00.0 = 00000000 On card, rom address for PCI: 04:00.0 = 0 PCI: 05:05.0 init Check CBFS header at fff7efe0 magic is 4f524243 Found CBFS header at fff7efe0 Check fallback/payload CBFS: follow chain: fff00000 + 38 + 15a48 + align -> fff15a80 Check fallback/coreboot_ram CBFS: follow chain: fff15a80 + 38 + 3801c + align -> fff4db00 Check CBFS: follow chain: fff4db00 + 28 + 314b8 + align -> fff7f000 CBFS: Could not find file pci104c,8025.rom In cbfs, rom address for PCI: 05:05.0 = 00000000 On card, rom address for PCI: 05:05.0 = 0 Devices initialized Show all devs...After init. Root Device: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 4 resources PCI: 00:18.0: enabled 1, 3 resources PCI: 00:00.0: enabled 1, 1 resources PCI: 00:01.0: enabled 1, 3 resources PCI: 01:05.0: enabled 1, 4 resources PCI: 00:02.0: enabled 0, 0 resources PCI: 00:03.0: enabled 0, 0 resources PCI: 00:04.0: enabled 1, 3 resources PCI: 00:05.0: enabled 0, 0 resources PCI: 00:06.0: enabled 0, 0 resources PCI: 00:07.0: enabled 0, 0 resources PCI: 00:08.0: enabled 0, 0 resources PCI: 00:09.0: enabled 1, 3 resources PCI: 00:0a.0: enabled 1, 3 resources PCI: 00:11.0: enabled 1, 6 resources PCI: 00:12.0: enabled 1, 1 resources PCI: 00:12.1: enabled 1, 1 resources PCI: 00:12.2: enabled 1, 1 resources PCI: 00:13.0: enabled 1, 1 resources PCI: 00:13.1: enabled 1, 1 resources PCI: 00:13.2: enabled 1, 1 resources PCI: 00:14.5: enabled 1, 1 resources PCI: 00:14.0: enabled 1, 2 resources I2C: 01:50: enabled 1, 0 resources I2C: 01:51: enabled 1, 0 resources I2C: 01:52: enabled 1, 0 resources I2C: 01:53: enabled 1, 0 resources PCI: 00:14.1: enabled 1, 5 resources PCI: 00:14.2: enabled 1, 1 resources PCI: 00:14.3: enabled 1, 4 resources PNP: 002e.0: enabled 0, 3 resources PNP: 002e.1: enabled 1, 2 resources PNP: 002e.2: enabled 0, 4 resources PNP: 002e.3: enabled 0, 2 resources PNP: 002e.4: enabled 0, 0 resources PNP: 002e.5: enabled 1, 3 resources PNP: 002e.6: enabled 1, 1 resources PNP: 002e.7: enabled 0, 0 resources PNP: 002e.8: enabled 0, 2 resources PNP: 002e.9: enabled 0, 1 resources PNP: 002e.a: enabled 0, 0 resources PCI: 00:14.4: enabled 1, 3 resources PCI: 00:18.1: enabled 1, 0 resources PCI: 00:18.2: enabled 1, 0 resources PCI: 00:18.3: enabled 1, 1 resources PCI: 00:18.4: enabled 1, 0 resources APIC: 01: enabled 1, 0 resources APIC: 02: enabled 1, 0 resources APIC: 03: enabled 1, 0 resources PCI: 04:00.0: enabled 1, 1 resources PCI: 05:05.0: enabled 1, 2 resources High Tables Base is 3fff0000. Writing IRQ routing tables to 0xf0000...done. Writing IRQ routing tables to 0x3fff0000...done. ACPI: Writing ACPI tables at 3fff0400... ACPI: * HPET at 3fff04e8 ACPI: added table 1/40 Length now 40 ACPI: * MADT at 3fff0520 ACPI: added table 2/40 Length now 44 ACPI: * SRAT at 3fff0590 SRAT: lapic cpu_index=00, node_id=00, apic_id=00 SRAT: lapic cpu_index=01, node_id=00, apic_id=01 SRAT: lapic cpu_index=02, node_id=00, apic_id=02 SRAT: lapic cpu_index=03, node_id=00, apic_id=03 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0020 startk=00000300, sizek=000ffd00 ACPI: added table 3/40 Length now 48 ACPI: * SLIT at 3fff0650 ACPI: added table 4/40 Length now 52 ACPI: * SSDT at 3fff0680 ACPI: added table 5/40 Length now 56 ACPI: * SSDT for PState at 3fff0cb5 ACPI: * DSDT at 3fff0cb8 ACPI: * DSDT @ 3fff0cb8 Length 298b ACPI: * FACS at 3fff3648 ACPI: * FADT at 3fff3688 pm_base: 0x0800 ACPI: added table 6/40 Length now 60 ACPI: done. Wrote the mp table end at: 000f0440 - 000f057c Wrote the mp table end at: 3fff3810 - 3fff394c Moving GDT to 0x3fff3c00...ok Multiboot Information structure has been written. Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500 - 00000518 checksum 7fdf New low_table_end: 0x00000518 Now going to write high coreboot table at 0x3fff4000 rom_table_end = 0x3fff4000 Adjust low_table_end from 0x00000518 to 0x00001000 Adjust rom_table_end from 0x3fff4000 to 0x40000000 Adding high table area uma_memory_start=0x30000000, uma_memory_size=0x0 Wrote coreboot table at: 3fff4000 - 3fff4918 checksum c71b Check CBFS header at fff7efe0 magic is 4f524243 Found CBFS header at fff7efe0 Check fallback/payload Got a payload Loading segment from rom address 0xfff00038 parameter section (skipped) Loading segment from rom address 0xfff00054 data (compression=0) malloc Enter, size 36, free_mem_ptr 0023d57c malloc 0023d57c New segment dstaddr 0x100000 memsize 0x1650b0 srcaddr 0xfff000d8 filesize 0x15960 (cleaned up) New segment addr 0x100000 size 0x1650b0 offset 0xfff000d8 filesize 0x15960 Loading segment from rom address 0xfff00070 data (compression=0) malloc Enter, size 36, free_mem_ptr 0023d5a0 malloc 0023d5a0 New segment dstaddr 0x2650b0 memsize 0x48 srcaddr 0xfff15a38 filesize 0x48 (cleaned up) New segment addr 0x2650b0 size 0x48 offset 0xfff15a38 filesize 0x48 Loading segment from rom address 0xfff0008c Entry Point 0x0010008c Loading Segment: addr: 0x0000000000100000 memsz: 0x00000000001650b0 filesz: 0x0000000000015960 lb: [0x0000000000200000, 0x00000000002fc000) segment: [0x0000000000100000, 0x0000000000115960, 0x00000000002650b0) malloc Enter, size 36, free_mem_ptr 0023d5c4 malloc 0023d5c4 early: [0x0000000000100000, 0x0000000000115960, 0x0000000000200000) bounce: [0x000000002fe08000, 0x000000002fe08000, 0x000000002fe6d0b0) Post relocation: addr: 0x000000002fe08000 memsz: 0x00000000000650b0 filesz: 0x0000000000000000 Loading Segment: addr: 0x00000000002650b0 memsz: 0x0000000000000048 filesz: 0x0000000000000048 lb: [0x0000000000200000, 0x00000000002fc000) segment: [0x00000000002650b0, 0x00000000002650f8, 0x00000000002650f8) bounce: [0x000000002fe6d0b0, 0x000000002fe6d0f8, 0x000000002fe6d0f8) Post relocation: addr: 0x000000002fe6d0b0 memsz: 0x0000000000000048 filesz: 0x0000000000000048 it's not compressed! [ 0x000000002fe6d0b0, 000000002fe6d0f8, 0x000000002fe6d0f8) <- 00000000fff15a38 Loaded segments Jumping to boot code at 10008c entry = 0x0010008c lb_start = 0x00200000 lb_size = 0x000fc000 adjust = 0x2fc08000 buffer = 0x2fe08000 elf_boot_notes = 0x002318d0 adjusted_boot_notes = 0x2fe398d0
INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} ---
Issuing SOFT_RESET...
-----Original Message----- From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Bao, Zheng Sent: Wednesday, September 16, 2009 10:56 AM To: Patrick Georgi Cc: coreboot@coreboot.org Subject: Re: [coreboot] r4633 building error of serengeti_cheetah_fam10
It was fixed.
Zheng
-----Original Message----- From: Patrick Georgi [mailto:patrick@georgi-clan.de] Sent: Tuesday, September 15, 2009 4:26 PM To: Bao, Zheng Cc: coreboot@coreboot.org Subject: Re: [coreboot] r4633 building error of serengeti_cheetah_fam10
Am Dienstag, den 15.09.2009, 11:00 +0800 schrieb Bao, Zheng:
./cbfs/cbfstool ./coreboot.rom add-payload ../payload.elf fallback/payload
make: *** [coreboot.rom] Segmentation fault
r4634 fixes segmentation faults when the file cannot be found. "../payload.elf" is suspicious - are you sure that is the right path?
If you're certain that this file should exist at that place, and if the segmentation fault still occurs with r4634, some more information is necessary: - which payload is this (so I can try to reproduce it, a copy of the payload binary would help the most) - is your build machine 32bit or 64bit?
Regards, Patrick
The whole log is attached.
Zheng
-----Original Message----- From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Bao, Zheng Sent: Wednesday, September 16, 2009 1:38 PM To: Patrick Georgi Cc: coreboot@coreboot.org Subject: Re: [coreboot] r4633 building error of serengeti_cheetah_fam10
The latest filo crashes if CBFS is enabled.
The CBFS can not work on my Fam10 board for a long time. I have to disable it all the time.
Can you guys test it?
Zheng
Log: ......................... PCI: 00:18.4 links 0 child on link 0 NULL Done allocating resources. Enabling resources... PCI: 00:18.0 cmd <- 00 PCI: 00:00.0 subsystem <- 1022/2b80 PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 bridge ctrl <- 000b PCI: 00:01.0 cmd <- 07 PCI: 01:05.0 subsystem <- 1022/2b80 PCI: 01:05.0 cmd <- 03 PCI: 00:04.0 bridge ctrl <- 0003 PCI: 00:04.0 cmd <- 00 PCI: 00:09.0 bridge ctrl <- 0003 PCI: 00:09.0 cmd <- 00 PCI: 00:0a.0 bridge ctrl <- 0003 PCI: 00:0a.0 cmd <- 06 PCI: 04:00.0 cmd <- 02 PCI: 00:11.0 cmd <- 03 PCI: 00:12.0 subsystem <- 1022/2b80 PCI: 00:12.0 cmd <- 02 PCI: 00:12.1 subsystem <- 1022/2b80 PCI: 00:12.1 cmd <- 02 PCI: 00:12.2 subsystem <- 1022/2b80 PCI: 00:12.2 cmd <- 02 PCI: 00:13.0 subsystem <- 1022/2b80 PCI: 00:13.0 cmd <- 02 PCI: 00:13.1 subsystem <- 1022/2b80 PCI: 00:13.1 cmd <- 02 PCI: 00:13.2 subsystem <- 1022/2b80 PCI: 00:13.2 cmd <- 02 PCI: 00:14.0 subsystem <- 1022/2b80 PCI: 00:14.0 cmd <- 403 PCI: 00:14.1 subsystem <- 1022/2b80 PCI: 00:14.1 cmd <- 01 PCI: 00:14.2 subsystem <- 1022/2b80 PCI: 00:14.2 cmd <- 02 PCI: 00:14.3 subsystem <- 1022/2b80 PCI: 00:14.3 cmd <- 0f sb700 lpc decode:PNP: 002e.1, base=0x000003f8, end=0x000003ff sb700 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000067 sb700 lpc decode:PNP: 002e.5, base=0x00000064, end=0x0000006b PNP: 002e.6 missing enable_resources PCI: 00:14.4 bridge ctrl <- 0003 PCI: 00:14.4 cmd <- 07 PCI: 05:05.0 cmd <- 02 PCI: 00:14.5 subsystem <- 1022/2b80 PCI: 00:14.5 cmd <- 02 PCI: 00:18.1 subsystem <- 1022/2b80 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1022/2b80 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 subsystem <- 1022/2b80 PCI: 00:18.4 cmd <- 00 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init start_eip=0x0000e000, offset=0x00200000, code_size=0x0000005b Initializing CPU #0 CPU: vendor AMD device 100f42 CPU: family 10, model 04, stepping 02 nodeid = 00, coreid = 00 Enabling cache
Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 1024MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 1024MB, range: 256MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 2, base: 768MB, range: 256MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs
MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled
Setting up local apic... apic_id: 0x00 done. CPU model: AMD Processor model unknown siblings = 03, CPU #0 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 2. Sending STARTUP #1 to 1. After apic_write. Initializing CPU #1 Startup point 1. Waiting for send to finish... +CPU: vendor AMD device 100f42 Sending STARTUP #2 to 1. After apic_write. CPU: family 10, model 04, stepping 02 Startup point 1. Waiting for send to finish... +nodeid = 00, coreid = 01 After Startup. Enabling cache Asserting INIT.
Setting fixed MTRRs(0-88) type: UC Waiting for send to finish... +Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Deasserting INIT. Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM Waiting for send to finish... +#startup loops: 2. Sending STARTUP #1 to 2. After apic_write. DONE fixed MTRRs Startup point 1. Waiting for send to finish... +Setting variable MTRR 0, base: 0MB, range: 1024MB, type WB Sending STARTUP #2 to 2. After apic_write. ADDRESS_MASK_HIGH=0xffff Startup point 1. Waiting for send to finish... +Setting variable MTRR 1, base: 1024MB, range: 256MB, type WB After Startup. ADDRESS_MASK_HIGH=0xffff Asserting INIT. Setting variable MTRR 2, base: 768MB, range: 256MB, type UC Waiting for send to finish... +ADDRESS_MASK_HIGH=0xffff Initializing CPU #2 DONE variable MTRRs Clear out the extra MTRR's CPU: vendor AMD device 100f42 Deasserting INIT. call enable_var_mtrr() Waiting for send to finish... +Leave x86_setup_var_mtrrs #startup loops: 2. Sending STARTUP #1 to 3. After apic_write.
MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled
Startup point 1. Waiting for send to finish... +Setting up local apic...Sending STARTUP #2 to 3. After apic_write. apic_id: 0x01 done. Startup point 1. Waiting for send to finish... +CPU model: AMD Processor model unknown After Startup. Waiting for 3 CPUS to stop siblings = 03, CPU: family 10, model 04, stepping 02 CPU #1 initialized Initializing CPU #3 Waiting for 2 CPUS to stop nodeid = 00, coreid = 02 CPU: vendor AMD device 100f42 Enabling cache CPU: family 10, model 04, stepping 02
Setting fixed MTRRs(0-88) type: UC nodeid = 00, coreid = 03 Enabling cache
Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM Setting variable MTRR 0, base: 0MB, range: 1024MB, type WB DONE fixed MTRRs ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 0, base: 0MB, range: 1024MB, type WB Setting variable MTRR 1, base: 1024MB, range: 256MB, type WB ADDRESS_MASK_HIGH=0xffff ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 1024MB, range: 256MB, type WB Setting variable MTRR 2, base: 768MB, range: 256MB, type UC ADDRESS_MASK_HIGH=0xffff ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 2, base: 768MB, range: 256MB, type UC DONE variable MTRRs Clear out the extra MTRR's ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs call enable_var_mtrr()
MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled
Leave x86_setup_var_mtrrs Setting up local apic... MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled
apic_id: 0x02 done. Setting up local apic...CPU model: AMD Processor model unknown apic_id: 0x03 done. siblings = 03, CPU model: AMD Processor model unknown CPU #2 initialized siblings = 03, Waiting for 1 CPUS to stop CPU #3 initialized All AP CPUs stopped PCI: 00:18.0 init PCI: 00:00.0 init pcie_init in rs780_ht.c PCI: 01:05.0 init internal_gfx_pci_dev_init device=9615, vendor=1002, vga_rom_address=0xfff00000. BTDC: MEMCLK = 0 BTDC: NB HT speed = 1c750b60. BTDC: CPU HT speed = 8ff50b60. BTDC: HT width = 11110020. Check CBFS header at fff7efe0 magic is 4f524243 Found CBFS header at fff7efe0 Check fallback/payload CBFS: follow chain: fff00000 + 38 + 15a48 + align -> fff15a80 Check fallback/coreboot_ram CBFS: follow chain: fff15a80 + 38 + 3801c + align -> fff4db00 Check CBFS: follow chain: fff4db00 + 28 + 314b8 + align -> fff7f000 CBFS: Could not find file pci1002,9615.rom In cbfs, rom address for PCI: 01:05.0 = 00000000 On mainboard, rom address for PCI: 01:05.0 = fff00000 PCI Expansion ROM, signature 0x414c, INIT size 0xa400, data ptr 0x6166 Incorrect Expansion ROM Header Signature 414c PCI: 00:11.0 init sata_bar0=2020 sata_bar1=2040 sata_bar2=2028 sata_bar3=2044 sata_bar4=2000 sata_bar5=d0309000 SATA port 0 status = 13 drive detection done after 0 ms Primary Master device is ready after 1 tries SATA port 1 status = 0 No Primary Slave SATA drive on Slot1 SATA port 2 status = 0 No Secondary Master SATA drive on Slot2 SATA port 3 status = 0 No Secondary Slave SATA drive on Slot3 PCI: 00:12.0 init PCI: 00:12.1 init PCI: 00:12.2 init usb2_bar0=d0309400 PCI: 00:13.0 init PCI: 00:13.1 init PCI: 00:13.2 init usb2_bar0=d0309500 PCI: 00:14.5 init PCI: 00:14.0 init sm_init(). lapicid = 0000000000000000 set power on after power fail ++++++++++no set NMI+++++ RTC Init Invalid CMOS LB checksum sm_init() end PCI: 00:14.1 init Check CBFS header at fff7efe0 magic is 4f524243 Found CBFS header at fff7efe0 Check fallback/payload CBFS: follow chain: fff00000 + 38 + 15a48 + align -> fff15a80 Check fallback/coreboot_ram CBFS: follow chain: fff15a80 + 38 + 3801c + align -> fff4db00 Check CBFS: follow chain: fff4db00 + 28 + 314b8 + align -> fff7f000 CBFS: Could not find file pci1002,439c.rom In cbfs, rom address for PCI: 00:14.1 = 00000000 On mainboard, rom address for PCI: 00:14.1 = 0 PCI: 00:14.2 init base = d0300000 codec_mask = 08 PCI: 00:14.3 init PNP: 002e.1 init PNP: 002e.5 init Keyboard init... Keyboard controller output buffer result timeout Timeout while enabling keyboard. (No keyboard present?) Keyboard controller output buffer result timeout Timeout waiting for keyboard after reset. PCI: 00:14.4 init PCI: 00:18.1 init Check CBFS header at fff7efe0 magic is 4f524243 Found CBFS header at fff7efe0 Check fallback/payload CBFS: follow chain: fff00000 + 38 + 15a48 + align -> fff15a80 Check fallback/coreboot_ram CBFS: follow chain: fff15a80 + 38 + 3801c + align -> fff4db00 Check CBFS: follow chain: fff4db00 + 28 + 314b8 + align -> fff7f000 CBFS: Could not find file pci1022,1201.rom In cbfs, rom address for PCI: 00:18.1 = 00000000 On mainboard, rom address for PCI: 00:18.1 = 0 PCI: 00:18.2 init Check CBFS header at fff7efe0 magic is 4f524243 Found CBFS header at fff7efe0 Check fallback/payload CBFS: follow chain: fff00000 + 38 + 15a48 + align -> fff15a80 Check fallback/coreboot_ram CBFS: follow chain: fff15a80 + 38 + 3801c + align -> fff4db00 Check CBFS: follow chain: fff4db00 + 28 + 314b8 + align -> fff7f000 CBFS: Could not find file pci1022,1202.rom In cbfs, rom address for PCI: 00:18.2 = 00000000 On mainboard, rom address for PCI: 00:18.2 = 0 PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 00:18.4 init Check CBFS header at fff7efe0 magic is 4f524243 Found CBFS header at fff7efe0 Check fallback/payload CBFS: follow chain: fff00000 + 38 + 15a48 + align -> fff15a80 Check fallback/coreboot_ram CBFS: follow chain: fff15a80 + 38 + 3801c + align -> fff4db00 Check CBFS: follow chain: fff4db00 + 28 + 314b8 + align -> fff7f000 CBFS: Could not find file pci1022,1204.rom In cbfs, rom address for PCI: 00:18.4 = 00000000 On mainboard, rom address for PCI: 00:18.4 = 0 PCI: 04:00.0 init Check CBFS header at fff7efe0 magic is 4f524243 Found CBFS header at fff7efe0 Check fallback/payload CBFS: follow chain: fff00000 + 38 + 15a48 + align -> fff15a80 Check fallback/coreboot_ram CBFS: follow chain: fff15a80 + 38 + 3801c + align -> fff4db00 Check CBFS: follow chain: fff4db00 + 28 + 314b8 + align -> fff7f000 CBFS: Could not find file pci14e4,167b.rom In cbfs, rom address for PCI: 04:00.0 = 00000000 On card, rom address for PCI: 04:00.0 = 0 PCI: 05:05.0 init Check CBFS header at fff7efe0 magic is 4f524243 Found CBFS header at fff7efe0 Check fallback/payload CBFS: follow chain: fff00000 + 38 + 15a48 + align -> fff15a80 Check fallback/coreboot_ram CBFS: follow chain: fff15a80 + 38 + 3801c + align -> fff4db00 Check CBFS: follow chain: fff4db00 + 28 + 314b8 + align -> fff7f000 CBFS: Could not find file pci104c,8025.rom In cbfs, rom address for PCI: 05:05.0 = 00000000 On card, rom address for PCI: 05:05.0 = 0 Devices initialized Show all devs...After init. Root Device: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 4 resources PCI: 00:18.0: enabled 1, 3 resources PCI: 00:00.0: enabled 1, 1 resources PCI: 00:01.0: enabled 1, 3 resources PCI: 01:05.0: enabled 1, 4 resources PCI: 00:02.0: enabled 0, 0 resources PCI: 00:03.0: enabled 0, 0 resources PCI: 00:04.0: enabled 1, 3 resources PCI: 00:05.0: enabled 0, 0 resources PCI: 00:06.0: enabled 0, 0 resources PCI: 00:07.0: enabled 0, 0 resources PCI: 00:08.0: enabled 0, 0 resources PCI: 00:09.0: enabled 1, 3 resources PCI: 00:0a.0: enabled 1, 3 resources PCI: 00:11.0: enabled 1, 6 resources PCI: 00:12.0: enabled 1, 1 resources PCI: 00:12.1: enabled 1, 1 resources PCI: 00:12.2: enabled 1, 1 resources PCI: 00:13.0: enabled 1, 1 resources PCI: 00:13.1: enabled 1, 1 resources PCI: 00:13.2: enabled 1, 1 resources PCI: 00:14.5: enabled 1, 1 resources PCI: 00:14.0: enabled 1, 2 resources I2C: 01:50: enabled 1, 0 resources I2C: 01:51: enabled 1, 0 resources I2C: 01:52: enabled 1, 0 resources I2C: 01:53: enabled 1, 0 resources PCI: 00:14.1: enabled 1, 5 resources PCI: 00:14.2: enabled 1, 1 resources PCI: 00:14.3: enabled 1, 4 resources PNP: 002e.0: enabled 0, 3 resources PNP: 002e.1: enabled 1, 2 resources PNP: 002e.2: enabled 0, 4 resources PNP: 002e.3: enabled 0, 2 resources PNP: 002e.4: enabled 0, 0 resources PNP: 002e.5: enabled 1, 3 resources PNP: 002e.6: enabled 1, 1 resources PNP: 002e.7: enabled 0, 0 resources PNP: 002e.8: enabled 0, 2 resources PNP: 002e.9: enabled 0, 1 resources PNP: 002e.a: enabled 0, 0 resources PCI: 00:14.4: enabled 1, 3 resources PCI: 00:18.1: enabled 1, 0 resources PCI: 00:18.2: enabled 1, 0 resources PCI: 00:18.3: enabled 1, 1 resources PCI: 00:18.4: enabled 1, 0 resources APIC: 01: enabled 1, 0 resources APIC: 02: enabled 1, 0 resources APIC: 03: enabled 1, 0 resources PCI: 04:00.0: enabled 1, 1 resources PCI: 05:05.0: enabled 1, 2 resources High Tables Base is 3fff0000. Writing IRQ routing tables to 0xf0000...done. Writing IRQ routing tables to 0x3fff0000...done. ACPI: Writing ACPI tables at 3fff0400... ACPI: * HPET at 3fff04e8 ACPI: added table 1/40 Length now 40 ACPI: * MADT at 3fff0520 ACPI: added table 2/40 Length now 44 ACPI: * SRAT at 3fff0590 SRAT: lapic cpu_index=00, node_id=00, apic_id=00 SRAT: lapic cpu_index=01, node_id=00, apic_id=01 SRAT: lapic cpu_index=02, node_id=00, apic_id=02 SRAT: lapic cpu_index=03, node_id=00, apic_id=03 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0020 startk=00000300, sizek=000ffd00 ACPI: added table 3/40 Length now 48 ACPI: * SLIT at 3fff0650 ACPI: added table 4/40 Length now 52 ACPI: * SSDT at 3fff0680 ACPI: added table 5/40 Length now 56 ACPI: * SSDT for PState at 3fff0cb5 ACPI: * DSDT at 3fff0cb8 ACPI: * DSDT @ 3fff0cb8 Length 298b ACPI: * FACS at 3fff3648 ACPI: * FADT at 3fff3688 pm_base: 0x0800 ACPI: added table 6/40 Length now 60 ACPI: done. Wrote the mp table end at: 000f0440 - 000f057c Wrote the mp table end at: 3fff3810 - 3fff394c Moving GDT to 0x3fff3c00...ok Multiboot Information structure has been written. Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500 - 00000518 checksum 7fdf New low_table_end: 0x00000518 Now going to write high coreboot table at 0x3fff4000 rom_table_end = 0x3fff4000 Adjust low_table_end from 0x00000518 to 0x00001000 Adjust rom_table_end from 0x3fff4000 to 0x40000000 Adding high table area uma_memory_start=0x30000000, uma_memory_size=0x0 Wrote coreboot table at: 3fff4000 - 3fff4918 checksum c71b Check CBFS header at fff7efe0 magic is 4f524243 Found CBFS header at fff7efe0 Check fallback/payload Got a payload Loading segment from rom address 0xfff00038 parameter section (skipped) Loading segment from rom address 0xfff00054 data (compression=0) malloc Enter, size 36, free_mem_ptr 0023d57c malloc 0023d57c New segment dstaddr 0x100000 memsize 0x1650b0 srcaddr 0xfff000d8 filesize 0x15960 (cleaned up) New segment addr 0x100000 size 0x1650b0 offset 0xfff000d8 filesize 0x15960 Loading segment from rom address 0xfff00070 data (compression=0) malloc Enter, size 36, free_mem_ptr 0023d5a0 malloc 0023d5a0 New segment dstaddr 0x2650b0 memsize 0x48 srcaddr 0xfff15a38 filesize 0x48 (cleaned up) New segment addr 0x2650b0 size 0x48 offset 0xfff15a38 filesize 0x48 Loading segment from rom address 0xfff0008c Entry Point 0x0010008c Loading Segment: addr: 0x0000000000100000 memsz: 0x00000000001650b0 filesz: 0x0000000000015960 lb: [0x0000000000200000, 0x00000000002fc000) segment: [0x0000000000100000, 0x0000000000115960, 0x00000000002650b0) malloc Enter, size 36, free_mem_ptr 0023d5c4 malloc 0023d5c4 early: [0x0000000000100000, 0x0000000000115960, 0x0000000000200000) bounce: [0x000000002fe08000, 0x000000002fe08000, 0x000000002fe6d0b0) Post relocation: addr: 0x000000002fe08000 memsz: 0x00000000000650b0 filesz: 0x0000000000000000 Loading Segment: addr: 0x00000000002650b0 memsz: 0x0000000000000048 filesz: 0x0000000000000048 lb: [0x0000000000200000, 0x00000000002fc000) segment: [0x00000000002650b0, 0x00000000002650f8, 0x00000000002650f8) bounce: [0x000000002fe6d0b0, 0x000000002fe6d0f8, 0x000000002fe6d0f8) Post relocation: addr: 0x000000002fe6d0b0 memsz: 0x0000000000000048 filesz: 0x0000000000000048 it's not compressed! [ 0x000000002fe6d0b0, 000000002fe6d0f8, 0x000000002fe6d0f8) <- 00000000fff15a38 Loaded segments Jumping to boot code at 10008c entry = 0x0010008c lb_start = 0x00200000 lb_size = 0x000fc000 adjust = 0x2fc08000 buffer = 0x2fe08000 elf_boot_notes = 0x002318d0 adjusted_boot_notes = 0x2fe398d0
INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} ---
Issuing SOFT_RESET...
-----Original Message----- From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Bao, Zheng Sent: Wednesday, September 16, 2009 10:56 AM To: Patrick Georgi Cc: coreboot@coreboot.org Subject: Re: [coreboot] r4633 building error of serengeti_cheetah_fam10
It was fixed.
Zheng
-----Original Message----- From: Patrick Georgi [mailto:patrick@georgi-clan.de] Sent: Tuesday, September 15, 2009 4:26 PM To: Bao, Zheng Cc: coreboot@coreboot.org Subject: Re: [coreboot] r4633 building error of serengeti_cheetah_fam10
Am Dienstag, den 15.09.2009, 11:00 +0800 schrieb Bao, Zheng:
./cbfs/cbfstool ./coreboot.rom add-payload ../payload.elf fallback/payload
make: *** [coreboot.rom] Segmentation fault
r4634 fixes segmentation faults when the file cannot be found. "../payload.elf" is suspicious - are you sure that is the right path?
If you're certain that this file should exist at that place, and if the segmentation fault still occurs with r4634, some more information is necessary: - which payload is this (so I can try to reproduce it, a copy of the payload binary would help the most) - is your build machine 32bit or 64bit?
Regards, Patrick
can you recommend a fam10 board that I could try to get and test on?
ron
Also, is there any way at all to test this under simnow?
ron
I use the fam10+RS780+SB7x0. That is why I doubt it is my problem.
Anyone who has the Serengeti_cheetah could try it. If it is ok, I will check my board and code.
Zheng
-----Original Message----- From: ron minnich [mailto:rminnich@gmail.com] Sent: Wednesday, September 16, 2009 1:53 PM To: Bao, Zheng Cc: Patrick Georgi; coreboot@coreboot.org Subject: Re: [coreboot] r4633 building error of serengeti_cheetah_fam10
can you recommend a fam10 board that I could try to get and test on?
ron
Am Mittwoch, den 16.09.2009, 13:37 +0800 schrieb Bao, Zheng:
The latest filo crashes if CBFS is enabled.
Just to make sure, this is FILO 0.6, the one that uses libpayload?
FILO 0.5 (without libpayload) wasn't tested for a loooong time.
Can you guys test it?
Could you provide the filo binary (filo.elf) somewhere for testing?
Regards, Patrick
It is Filo 0.6 with libpayload.
The attached file is the binary.
With Ron's patch "fix cbfstool malloc arena corruption", the SOFT_RESET is still there.
Zheng
-----Original Message----- From: Patrick Georgi [mailto:patrick@georgi-clan.de] Sent: Wednesday, September 16, 2009 4:22 PM To: Bao, Zheng Cc: coreboot@coreboot.org Subject: RE: [coreboot] r4633 building error of serengeti_cheetah_fam10
Am Mittwoch, den 16.09.2009, 13:37 +0800 schrieb Bao, Zheng:
The latest filo crashes if CBFS is enabled.
Just to make sure, this is FILO 0.6, the one that uses libpayload?
FILO 0.5 (without libpayload) wasn't tested for a loooong time.
Can you guys test it?
Could you provide the filo binary (filo.elf) somewhere for testing?
Regards, Patrick
Am Donnerstag, den 17.09.2009, 10:21 +0800 schrieb Bao, Zheng:
It is Filo 0.6 with libpayload.
The attached file is the binary.
With Ron's patch "fix cbfstool malloc arena corruption", the SOFT_RESET is still there.
I could reproduce the issue and will work on fixing it.
As a workaround, you can set RAMBASE to 4mb (it is at 2mb now), so coreboot_ram doesn't overlap with the payload (which has a .bss section reaching well to 2.5mb or so), or set it to 1mb (as is the case for most other boards), so the payload and the overlap region are aligned.
Regards, Patrick
-
Bao, Zheng -
Patrick Georgi -
ron minnich