This is a proposal for cpu startup on v3. It is motivated by the needs of SMP. The idea is that we introduce cpu phases to parallel the device phases. Because, on modern CPUs, we can dynamically probe pretty much everything, we don't use the device tree for CPUs; that was always a point of confusion on v2 anyway. Rather, in this example, we define cpu_phase1 and cpu_phase 6 (for example) and define weak symbols for them. These functions can be over-ridden by platform or cpu functions.
Here's the patch. Comments welcome.
ron Index: lib/stage2.c =================================================================== --- lib/stage2.c (revision 1143) +++ lib/stage2.c (working copy) @@ -28,6 +28,18 @@ #include <device/device.h> #include <tables.h>
+void __attribute__((weak)) unsigned int cpu_phase1(unsigned int coldboot, + struct sys_info *sysinfo) +{ + printk(BIOS_SPEW, "cpu_phase1: nothing to do\n"); +} + +void __attribute__((weak)) unsigned int cpu_phase6(unsigned int coldboot, + struct sys_info *sysinfo) +{ + printk(BIOS_SPEW, "cpu_phase6: nothing to do\n"); +} + /** * Main function of the DRAM part of coreboot. * @@ -44,8 +56,10 @@ void *stage2(void) { void *mbi; + struct sys_info *sysinfo = &(global_vars()->sys_info);
post_code(POST_STAGE2_BEGIN); + cpu_phase1(is_coldboot(), sysinfo); dev_init();
/* Phase 1 was console init and making printk work. Both functions are @@ -85,6 +99,11 @@ dev_phase6(); show_all_devs(BIOS_DEBUG, "After phase 6.");
+ /* final cleanup: do any remaining CPU setup. This can include memory + * init, or not, depending on the CPU; it may have been done in phase 1. + */ + cpu_phase6(is_coldboot(), sysinfo); + /* Write tables to pass information to the payloads. */ post_code(POST_STAGE2_WRITE_TABLES); mbi = write_tables();
ron minnich wrote:
cpu_phase1 and cpu_phase 6 (for example)
Please call it cpu_phase2 instead. Then:
Acked-by: Peter Stuge peter@stuge.se
On Fri, Mar 6, 2009 at 12:41 PM, Peter Stuge peter@stuge.se wrote:
ron minnich wrote:
cpu_phase1 and cpu_phase 6 (for example)
Please call it cpu_phase2 instead. Then:
are you sure? this is cpu code in stage2, phase1. Why phase2?
ron
ron minnich wrote:
On Fri, Mar 6, 2009 at 12:41 PM, Peter Stuge peter@stuge.se wrote:
ron minnich wrote:
cpu_phase1 and cpu_phase 6 (for example)
Please call it cpu_phase2 instead. Then:
are you sure? this is cpu code in stage2, phase1. Why phase2?
cpu_phase1 and cpu_phase2 was my idea. If they are indeed running completely independent of other stage2_phases. Maybe I misunderstood?
//Peter
On Fri, Mar 6, 2009 at 12:41 PM, Peter Stuge peter@stuge.se wrote:
ron minnich wrote:
cpu_phase1 and cpu_phase 6 (for example)
Please call it cpu_phase2 instead. Then:
now I see. You want cpu_phase6 to be called cpu_phase2?
Here is why I did not. I want to leave open the possibility that hardware creates a need for other phases. However, I'm not picky on this.
ron
ron minnich wrote:
cpu_phase1 and cpu_phase 6 (for example)
Please call it cpu_phase2 instead. Then:
now I see. You want cpu_phase6 to be called cpu_phase2?
Yes, exactly! :)
Here is why I did not. I want to leave open the possibility that hardware creates a need for other phases. However, I'm not picky on this.
While it is nice to plan ahead a little I would prefer if we just changed the numbering.
This needs to be done for some non-CPU stages/phases too. I think we should just do it.
//Peter
On Fri, Mar 6, 2009 at 3:29 PM, Peter Stuge peter@stuge.se wrote:
ron minnich wrote:
cpu_phase1 and cpu_phase 6 (for example)
Please call it cpu_phase2 instead. Then:
now I see. You want cpu_phase6 to be called cpu_phase2?
Yes, exactly! :)
OK, I will test this change tonight and if it all works I will be posting final diffs this weekend. With any luck by "final diffs" I will mean "first working real SMP hardware in v3". We'll see.
ron
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Peter Stuge -
ron minnich