ron minnich wrote:
I don't think we can assume that an open, unlicensed instruction set guarantees open, unlicensed, blob-free CPUs and platforms.
This is of course absolutely accurate.
But a freely licensed ISA and implementation(s) thereof are *one step* in the right direction, and a significant one.
RISC-V is not so much a guarantee of anything as it is a potential enabler of something.
The fabulous thing about RISC-V is what makes ARM successful; there can and will be multiple different silicon vendors, offering products with many different features and tradeoffs.
Some can be top performance but proprietary. Some can be transparent/open but slower.
There is market for both.
//Peter
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On 09/07/2017 10:11 AM, Peter Stuge wrote:
ron minnich wrote:
I don't think we can assume that an open, unlicensed instruction set guarantees open, unlicensed, blob-free CPUs and platforms.
This is of course absolutely accurate.
But a freely licensed ISA and implementation(s) thereof are *one step* in the right direction, and a significant one.
RISC-V is not so much a guarantee of anything as it is a potential enabler of something.
The fabulous thing about RISC-V is what makes ARM successful; there can and will be multiple different silicon vendors, offering products with many different features and tradeoffs.
Some can be top performance but proprietary. Some can be transparent/open but slower.
We already have this (think cheap ARM SoCs vs. a Xeon). In practice it means that if you want to use a computer for real work (such as developing libre software) you have to go proprietary, which is not what I think we want to see here.
OpenPOWER is the first attempt to change this that we have seen in a long time. I'm honestly surprised at the overall community betting on a long shot (RISC-V) vs. using what's available and open right now (POWER9); could anyone shed some light on these decision making processes? An open ISA and core design does not guarantee open silicon, and in fact one could argue that it will mean any performance improvements end up highly locked under NDA and similar to avoid competitors coming online and ruining tens of millions of dollars of investment for even one SoC improvement.
- -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 (direct line) +1 (512) 690-0200 (switchboard) https://www.raptorengineering.com
On Thu, Sep 7, 2017 at 11:03 AM Timothy Pearson < tpearson@raptorengineering.com> wrote:
could anyone shed some light on these decision making processes? An open ISA and core design does not guarantee open silicon, and in fact one could argue that it will mean any performance improvements end up highly locked under NDA and similar to avoid competitors coming online and ruining tens of millions of dollars of investment for even one SoC improvement.
Exactly. The open ISA can go both ways: pushing toward "value adds" that lock up a platform, instead of going the way we might hope, so vendors have competitive advantage. Look at page 47 of "Volume II: RISC-V Privileged Architectures V1.10" -- it basically allows a vendor to recreate SMM as it exists today, creating regions of memory irrevocably hidden from kernel. And there are certain things you can't access on riscv without an M-mode trap, which means that you can't escape the need for code in M mode.
RISCV vendors can create SMM. We need to encourage creation of a world in which they do not. But just claiming that "riscv is open so there won't be anything proprietary" is being a bit unrealistic in my view.
So what about Power? The problem I keep hearing is that power competes in the server space with x86, and not well enough. It's one of too slow, too power hungry, or too expensive right now to compete well. I am hoping that Raptor is going to show us power done right :-)
ron
Am 07.09.2017 20:03 schrieb "Timothy Pearson" < tpearson@raptorengineering.com>:
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On 09/07/2017 10:11 AM, Peter Stuge wrote:
ron minnich wrote:
I don't think we can assume that an open, unlicensed instruction set guarantees open, unlicensed, blob-free CPUs and platforms.
This is of course absolutely accurate.
But a freely licensed ISA and implementation(s) thereof are *one step* in the right direction, and a significant one.
RISC-V is not so much a guarantee of anything as it is a potential enabler of something.
The fabulous thing about RISC-V is what makes ARM successful; there can and will be multiple different silicon vendors, offering products with many different features and tradeoffs.
Some can be top performance but proprietary. Some can be transparent/open but slower.
We already have this (think cheap ARM SoCs vs. a Xeon). In practice it means that if you want to use a computer for real work (such as developing libre software) you have to go proprietary, which is not what I think we want to see here.
OpenPOWER is the first attempt to change this that we have seen in a long time. I'm honestly surprised at the overall community betting on a long shot (RISC-V) vs. using what's available and open right now (POWER9); could anyone shed some light on these decision making processes?
There is no coherent decision making process.
open ISA and core design does not guarantee open silicon, and in fact one could argue that it will mean any performance improvements end up highly locked under NDA and similar to avoid competitors coming online and ruining tens of millions of dollars of investment for even one SoC improvement.
- -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 (direct line) +1 (512) 690-0200 (switchboard) https://www.raptorengineering.com
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Patrick Georgi -
Peter Stuge -
ron minnich -
Timothy Pearson