Bay trail and SATA legacy IDE mode

[Berth-Olof Bergman]

Hi all,

Has anyone run a Bay Trail SOC in SATA legacy IDE mode?
It doesn’t work on my boards, even though I have identical settings of the PCI configuration space as AMI and Phoenix BIOS.
The port works, but the IRQs are wrong polarity. Thus when issuing a command, I don’t get an interrupt.
If I read the IDE status register (alternate or main) I get an interrupt. As reading the IDE status register, negates interrupt, I get the high level edge as the polarity is inverted.

Can you verify if IDE legacy mode works for Bay Trail with correct?

Best regards,

B-O Bergman
Winzent Technologies

[Stojsavljevic, Zoran]

Hello Patrick, Marc,

Long-time no see, no talk... I need your help here.

Here we have an interesting situation, since my best knowledge of FSP + Coreboot + SeaBIOS is limited... I am on the other side of the Galaxy now, for quite a (long) time. :)

But still... I have some limited knowledge of Coreboot from 15 months ago, and I am trying to understand if Coreboot x86 code has some influence on the SATA IDE mode. From what I am reading... There is a possibility!

The silicon is BYT SoC, ATOM. The boot time to OS bootloader is around 300 ms.

My best understanding how this enumeration works for SATA is that all SATA are put in default AHCI mode. But some people (As Berth) must have SATA interfaces in IDE mode.

What I know from what I see, what I understand... The Coreboot shown in stages is the following:
- bootblock
- romstage
- ramstage
- payload

So let us magnify the one, important for this case: ramstage! In this stage the following is happening (among others) - Tables initialized: ACPI,..., IRQ Routing, etc.

PCIe discovery is done... And, FSP 3rd call NotifyPhaseEntry () API is called twice.

Let me magnify all of these... As my best understanding is! Let us concentrate to the next: DEVICETREE.CB code!

I see that some devices are in the format: device pci 2.0 on end - 0.2.0 IDE interface... BIOS like!

I also see that some devices are defined in Coreboot directory: northbridge/intel/...

Since I am not sure where SATA IDE code is, for BYT... Could you, please, navigate me? Not sure where these definition are?! I need pointer to source code for BYT SATA IDE, if possible (pointer to Coreboot source code directories)?

If this is NOT hidden in NotifyPhaseEntry ()... You will tell me, hopefully.

Thank you,
Zoran Stojsavljevic

-----Original Message-----
From: Berth-Olof Bergman [mailto:[e-mail]] 
Sent: Friday, February 06, 2015 10:07 AM
To: [e-mail]
Subject: Bay trail and SATA legacy IDE mode

Hi all,

Has anyone run a Bay Trail SOC in SATA legacy IDE mode?
It doesn’t work on my boards, even though I have identical settings of the PCI configuration space as AMI and Phoenix BIOS.
The port works, but the IRQs are wrong polarity. Thus when issuing a command, I don’t get an interrupt.
If I read the IDE status register (alternate or main) I get an interrupt. As reading the IDE status register, negates interrupt, I get the high level edge as the polarity is inverted.

Can you verify if IDE legacy mode works for Bay Trail with correct?

Best regards,

B-O Bergman
Winzent Technologies

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