[commit] r6273 - in trunk/src: cpu/amd/car cpu/intel/car cpu/intel/model_106cx cpu/intel/model_6ex cpu/intel/model_6fx cpu/via/car include/cpu/x86

[repository service]

Author: stepan
Date: Wed Jan 19 07:54:42 2011
New Revision: 6273
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6273

Log:
Revert r5902 to make code more readable again. At least three people like to
have this go away again.

Signed-off-by: Stefan Reinauer 
Acked-by: Rudolf Marek                                                                           
Acked-by: Kevin O'Connor

Deleted:
   trunk/src/include/cpu/x86/car.h
Modified:
   trunk/src/cpu/amd/car/cache_as_ram.inc
   trunk/src/cpu/intel/car/cache_as_ram.inc
   trunk/src/cpu/intel/model_106cx/cache_as_ram.inc
   trunk/src/cpu/intel/model_6ex/cache_as_ram.inc
   trunk/src/cpu/intel/model_6fx/cache_as_ram.inc
   trunk/src/cpu/via/car/cache_as_ram.inc

Modified: trunk/src/cpu/amd/car/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/amd/car/cache_as_ram.inc	Wed Jan 19 07:32:35 2011	(r6272)
+++ trunk/src/cpu/amd/car/cache_as_ram.inc	Wed Jan 19 07:54:42 2011	(r6273)
@@ -18,7 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

-#include <cpu/x86/car.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/mtrr.h>

@@ -46,7 +45,8 @@
  *   xmm3: Backup EBX
  */

-	save_bist_result()
+	/* Save the BIST result. */
+	movl	%eax, %ebp

/*
     * For normal part %ebx already contain cpu_init_detected
@@ -56,7 +56,10 @@
 cache_as_ram_setup:
    post_code(0xa0)

-	enable_sse()
+	/* Enable SSE. */
+	movl	%cr4, %eax
+	orl	$(3 << 9), %eax
+	movl	%eax, %cr4

/* Figure out the CPU family. */
    cvtsi2sd %ebx, %xmm3
@@ -321,7 +324,10 @@

post_code(0xa1)

-	enable_cache()
+	/* Enable cache. */
+	movl	%cr0, %eax
+	andl	$(~((1 << 30) | (1 << 29))), %eax
+	movl	%eax, %cr0

jmp_if_k8(fam10_end_part1)

@@ -403,9 +409,13 @@

post_code(0xa5)

-	disable_sse()
+	/* Disable SSE. */
+	movl	%cr4, %eax
+	andl	$~(3 << 9), %eax
+	movl	%eax, %cr4

-	restore_bist_result()
+	/* Restore the BIST result. */
+	movl	%ebp, %eax

/* We need to set EBP? No need. */
    movl	%esp, %ebp

Modified: trunk/src/cpu/intel/car/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/intel/car/cache_as_ram.inc	Wed Jan 19 07:32:35 2011	(r6272)
+++ trunk/src/cpu/intel/car/cache_as_ram.inc	Wed Jan 19 07:54:42 2011	(r6273)
@@ -21,7 +21,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

-#include <cpu/x86/car.h>
 #include <cpu/x86/stack.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/lapic_def.h>
@@ -29,7 +28,8 @@
 #define CacheSize		CONFIG_DCACHE_RAM_SIZE
 #define CacheBase		(0xd0000 - CacheSize)

-	save_bist_result()
+	/* Save the BIST result. */
+	movl	%eax, %ebp

CacheAsRam:
    /* Check whether the processor has HT capability. */
@@ -257,7 +257,10 @@
    wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */

-	enable_cache()
+	/* Enable cache. */
+	movl	%cr0, %eax
+	andl	$(~((1 << 30) | (1 << 29))), %eax
+	movl	%eax, %cr0

/* Read the range with lodsl. */
    movl	$CacheBase, %esi
@@ -318,7 +321,8 @@
    movl	$(CacheBase + CacheSize - 4), %eax
    movl	%eax, %esp
 lout:
-	restore_bist_result()
+	/* Restore the BIST result. */
+	movl	%ebp, %eax

/* We need to set EBP? No need. */
    movl	%esp, %ebp
@@ -327,7 +331,10 @@

/* We don't need CAR from now on. */

-	disable_cache()
+	/* Disable cache. */
+	movl	%cr0, %eax
+	orl	$(1 << 30), %eax
+	movl	%eax, %cr0

/* Clear sth. */
    movl	$MTRRfix4K_C8000_MSR, %ecx
@@ -349,7 +356,10 @@
    movl	$0x00000800, %eax /* Enable variable and disable fixed MTRRs. */
    wrmsr

-	enable_cache();
+	/* Enable cache. */
+	movl	%cr0, %eax
+	andl	$(~((1 << 30) | (1 << 29))), %eax
+	movl	%eax, %cr0

/* Clear boot_complete flag. */
    xorl	%ebp, %ebp

Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/intel/model_106cx/cache_as_ram.inc	Wed Jan 19 07:32:35 2011	(r6272)
+++ trunk/src/cpu/intel/model_106cx/cache_as_ram.inc	Wed Jan 19 07:54:42 2011	(r6273)
@@ -18,14 +18,14 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

-#include <cpu/x86/car.h>
 #include <cpu/x86/stack.h>
 #include <cpu/x86/mtrr.h>

#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE

-	save_bist_result()
+	/* Save the BIST result. */
+	movl	%eax, %ebp

cache_as_ram:
    post_code(0x20)
@@ -66,12 +66,19 @@
    xorl	%edx, %edx
    wrmsr

-	enable_mtrr()
+	/* Enable MTRR. */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	orl	$(1 << 11), %eax
+	wrmsr

-	enable_l2_cache()
+	/* Enable L2 cache. */
+	movl	$0x11e, %ecx
+	rdmsr
+	orl	$(1 << 8), %eax
+	wrmsr

/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
-	/* TODO: enable_cache()? But that doesn't have "invd". */
         movl	%cr0, %eax
    andl	$(~((1 << 30) | (1 << 29))), %eax
    invd
@@ -86,7 +93,9 @@
    rep	stosl

/* Enable Cache-as-RAM mode by disabling cache. */
-	disable_cache()
+	movl	%cr0, %eax
+	orl	$(1 << 30), %eax
+	movl	%eax, %cr0

#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
    /* Enable cache for our code in Flash because we do XIP here */
@@ -112,7 +121,10 @@
    wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */

-	enable_cache()
+	/* Enable cache. */
+	movl	%cr0, %eax
+	andl	$(~((1 << 30) | (1 << 29))), %eax
+	movl	%eax, %cr0

/* Set up the stack pointer. */
 #if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1)
@@ -123,8 +135,8 @@
 #endif
    movl	%eax, %esp

-	restore_bist_result()
-
+	/* Restore the BIST result. */
+	movl	%ebp, %eax
    movl	%esp, %ebp
    pushl	%eax

@@ -137,11 +149,18 @@

post_code(0x30)

-	disable_cache()
+	/* Disable cache. */
+	movl	%cr0, %eax
+	orl	$(1 << 30), %eax
+	movl	%eax, %cr0

post_code(0x31)

-	disable_mtrr()
+	/* Disable MTRR. */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	andl	$(~(1 << 11)), %eax
+	wrmsr

post_code(0x31)

@@ -161,11 +180,17 @@

post_code(0x33)

-	enable_cache()
+	/* Enable cache. */
+	movl	%cr0, %eax
+	andl	$~((1 << 30) | (1 << 29)), %eax
+	movl	%eax, %cr0

post_code(0x36)

-	disable_cache()
+	/* Disable cache. */
+	movl	%cr0, %eax
+	orl	$(1 << 30), %eax
+	movl	%eax, %cr0

post_code(0x38)

@@ -182,11 +207,17 @@
    post_code(0x39)

/* And enable cache again after setting MTRRs. */
-	enable_cache()
+	movl	%cr0, %eax
+	andl	$~((1 << 30) | (1 << 29)), %eax
+	movl	%eax, %cr0

post_code(0x3a)

-	enable_mtrr()
+	/* Enable MTRR. */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	orl	$(1 << 11), %eax
+	wrmsr

post_code(0x3b)

Modified: trunk/src/cpu/intel/model_6ex/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/intel/model_6ex/cache_as_ram.inc	Wed Jan 19 07:32:35 2011	(r6272)
+++ trunk/src/cpu/intel/model_6ex/cache_as_ram.inc	Wed Jan 19 07:54:42 2011	(r6273)
@@ -18,14 +18,14 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

-#include <cpu/x86/car.h>
 #include <cpu/x86/stack.h>
 #include <cpu/x86/mtrr.h>

#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE

-	save_bist_result()
+	/* Save the BIST result. */
+	movl	%eax, %ebp

cache_as_ram:
    post_code(0x20)
@@ -66,12 +66,19 @@
    movl	$0x0000000f, %edx
    wrmsr

-	enable_mtrr()
+	/* Enable MTRR. */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	orl	$(1 << 11), %eax
+	wrmsr

-	enable_l2_cache()
+	/* Enable L2 cache. */
+	movl	$0x11e, %ecx
+	rdmsr
+	orl	$(1 << 8), %eax
+	wrmsr

/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
-	/* TODO: enable_cache()? But that doesn't have "invd". */
         movl	%cr0, %eax
    andl	$(~((1 << 30) | (1 << 29))), %eax
    invd
@@ -86,7 +93,9 @@
    rep	stosl

/* Enable Cache-as-RAM mode by disabling cache. */
-	disable_cache()
+	movl	%cr0, %eax
+	orl	$(1 << 30), %eax
+	movl	%eax, %cr0

#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
    /* Enable cache for our code in Flash because we do XIP here */
@@ -112,7 +121,10 @@
    wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */

-	enable_cache()
+	/* Enable cache. */
+	movl	%cr0, %eax
+	andl	$(~((1 << 30) | (1 << 29))), %eax
+	movl	%eax, %cr0

/* Set up the stack pointer. */
 #if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1)
@@ -123,8 +135,8 @@
 #endif
    movl	%eax, %esp

-	restore_bist_result()
-
+	/* Restore the BIST result. */
+	movl	%ebp, %eax
    movl	%esp, %ebp
    pushl	%eax

@@ -137,11 +149,18 @@

post_code(0x30)

-	disable_cache()
+	/* Disable cache. */
+	movl	%cr0, %eax
+	orl	$(1 << 30), %eax
+	movl	%eax, %cr0

post_code(0x31)

-	disable_mtrr()
+	/* Disable MTRR. */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	andl	$(~(1 << 11)), %eax
+	wrmsr

post_code(0x31)

@@ -161,11 +180,17 @@

post_code(0x33)

-	enable_cache()
+	/* Enable cache. */
+	movl	%cr0, %eax
+	andl	$~((1 << 30) | (1 << 29)), %eax
+	movl	%eax, %cr0

post_code(0x36)

-	disable_cache()
+	/* Disable cache. */
+	movl	%cr0, %eax
+	orl	$(1 << 30), %eax
+	movl	%eax, %cr0

post_code(0x38)

@@ -182,11 +207,17 @@
    post_code(0x39)

/* And enable cache again after setting MTRRs. */
-	enable_cache()
+	movl	%cr0, %eax
+	andl	$~((1 << 30) | (1 << 29)), %eax
+	movl	%eax, %cr0

post_code(0x3a)

-	enable_mtrr()
+	/* Enable MTRR. */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	orl	$(1 << 11), %eax
+	wrmsr

post_code(0x3b)

Modified: trunk/src/cpu/intel/model_6fx/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/intel/model_6fx/cache_as_ram.inc	Wed Jan 19 07:32:35 2011	(r6272)
+++ trunk/src/cpu/intel/model_6fx/cache_as_ram.inc	Wed Jan 19 07:54:42 2011	(r6273)
@@ -18,14 +18,14 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

-#include <cpu/x86/car.h>
 #include <cpu/x86/stack.h>
 #include <cpu/x86/mtrr.h>

#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE

-	save_bist_result()
+	/* Save the BIST result. */
+	movl	%eax, %ebp

cache_as_ram:
    post_code(0x20)
@@ -73,12 +73,19 @@
    movl	$0x0000000f, %edx
    wrmsr

-	enable_mtrr()
+	/* Enable MTRR. */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	orl	$(1 << 11), %eax
+	wrmsr

-	enable_l2_cache()
+	/* Enable L2 cache. */
+	movl	$0x11e, %ecx
+	rdmsr
+	orl	$(1 << 8), %eax
+	wrmsr

/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
-	/* TODO: enable_cache()? But that doesn't have "invd". */
         movl	%cr0, %eax
    andl	$(~((1 << 30) | (1 << 29))), %eax
    invd
@@ -93,7 +100,9 @@
    rep	stosl

/* Enable Cache-as-RAM mode by disabling cache. */
-	disable_cache()
+	movl	%cr0, %eax
+	orl	$(1 << 30), %eax
+	movl	%eax, %cr0

#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
    /* Enable cache for our code in Flash because we do XIP here */
@@ -119,7 +128,10 @@
    wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */

-	enable_cache()
+	/* Enable cache. */
+	movl	%cr0, %eax
+	andl	$(~((1 << 30) | (1 << 29))), %eax
+	movl	%eax, %cr0

/* Set up the stack pointer. */
 #if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1)
@@ -130,8 +142,8 @@
 #endif
    movl	%eax, %esp

-	restore_bist_result()
-
+	/* Restore the BIST result. */
+	movl	%ebp, %eax
    movl	%esp, %ebp
    pushl	%eax

@@ -144,11 +156,18 @@

post_code(0x30)

-	disable_cache()
+	/* Disable cache. */
+	movl	%cr0, %eax
+	orl	$(1 << 30), %eax
+	movl	%eax, %cr0

post_code(0x31)

-	disable_mtrr()
+	/* Disable MTRR. */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	andl	$(~(1 << 11)), %eax
+	wrmsr

post_code(0x31)

@@ -168,11 +187,17 @@

post_code(0x33)

-	enable_cache()
+	/* Enable cache. */
+	movl	%cr0, %eax
+	andl	$~((1 << 30) | (1 << 29)), %eax
+	movl	%eax, %cr0

post_code(0x36)

-	disable_cache()
+	/* Disable cache. */
+	movl	%cr0, %eax
+	orl	$(1 << 30), %eax
+	movl	%eax, %cr0

post_code(0x38)

@@ -189,11 +214,17 @@
    post_code(0x39)

/* And enable cache again after setting MTRRs. */
-	enable_cache()
+	movl	%cr0, %eax
+	andl	$~((1 << 30) | (1 << 29)), %eax
+	movl	%eax, %cr0

post_code(0x3a)

-	enable_mtrr()
+	/* Enable MTRR. */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	orl	$(1 << 11), %eax
+	wrmsr

post_code(0x3b)

Modified: trunk/src/cpu/via/car/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/via/car/cache_as_ram.inc	Wed Jan 19 07:32:35 2011	(r6272)
+++ trunk/src/cpu/via/car/cache_as_ram.inc	Wed Jan 19 07:54:42 2011	(r6273)
@@ -25,18 +25,21 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

-#include <cpu/x86/car.h>
 #include <cpu/x86/stack.h>
 #include <cpu/x86/mtrr.h>

#define CacheSize		CONFIG_DCACHE_RAM_SIZE
 #define CacheBase		CONFIG_DCACHE_RAM_BASE

-	save_bist_result()
+	/* Save the BIST result. */
+	movl	%eax, %ebp

CacheAsRam:

-	disable_cache()
+	/* Disable cache. */
+	movl	%cr0, %eax
+	orl	$(1 << 30), %eax
+	movl	%eax, %cr0
    invd

/* Set the default memory type and enable fixed and variable MTRRs. */
@@ -139,7 +142,10 @@
    movl	$(MTRRdefTypeEn), %eax
    wrmsr

-	enable_cache()
+	/* Enable cache. */
+	movl	%cr0, %eax
+	andl	$(~((1 << 30) | (1 << 29))), %eax
+	movl	%eax, %cr0

/* Read the range with lodsl. */
    cld
@@ -195,7 +201,8 @@
    jne	stackerr
 #endif

-	restore_bist_result()
+	/* Restore the BIST result. */
+	movl	%ebp, %eax

/* We need to set EBP? No need. */
    movl	%esp, %ebp
@@ -210,7 +217,10 @@

/* We don't need CAR from now on. */

-	disable_cache()
+	/* Disable cache. */
+	movl	%cr0, %eax
+	orl	$(1 << 30), %eax
+	movl	%eax, %cr0

/* Set the default memory type and enable variable MTRRs. */
    /* TODO: Or also enable fixed MTRRs? Bug in the code? */
@@ -242,7 +252,10 @@
    movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
    wrmsr

-	enable_cache()
+	/* Enable cache. */
+	movl	%cr0, %eax
+	andl	$(~((1 << 30) | (1 << 29))), %eax
+	movl	%eax, %cr0
    invd

/* Clear boot_complete flag. */