I'm trying out Coreboot on a Thinkpad T60p. I followed the instructions at https://github.com/bibanon/Coreboot-ThinkPads/wiki/ThinkPad-T60p until I got the flashing part. There it wasn't clear where the lenovobios_firstflash and lenovobios_secondflash scripts were to be found. On IRC, someone pointed me to https://github.com/rabcyr/libreboot/blob/master/lenovobios_firstflash. I used that and got what seems like a failure[1]. A few minutes after this, the laptop decided to go to sleep and I couldn't wake it. I rebooted and evidently somehow Coreboot and SeaBIOS took.
Now I suppose I'm at the stage where I do the second flashing. In the meantime, the trackpoint stick and buttons won't work anymore and there's an intermittent high-pitched whine from the left side of the keyboard.
Did I actually succeed in flashing my T60p? Did I do anything wrong? How do I fix the trackpoint and get rid of the whine?
[1] $ sudo ./lenovobios_firstflash ~/coreboot/build/coreboot.rom
if [[ $EUID -ne 0 ]]; then echo "This script must be run as root" exit 1 fi if (( $# != 1 )); then echo "Usage: ./lenovobios_firstflash yourrom.rom" echo "usage: ./lenovobios_firstflash path/to/yourrom.rom" echo "You need to specify exactly 1 file" exit 1 fi Usage: ./lenovobios_firstflash yourrom.rom usage: ./lenovobios_firstflash path/to/yourrom.rom You need to specify exactly 1 file dave@osiris:~/libreboot_util$ sudo ./lenovobios_firstflash ~/coreboot/build/coreboot.rom
if [[ $EUID -ne 0 ]]; then echo "This script must be run as root" exit 1 fi if (( $# != 1 )); then echo "Usage: ./lenovobios_firstflash yourrom.rom" echo "usage: ./lenovobios_firstflash path/to/yourrom.rom" echo "You need to specify exactly 1 file" exit 1 fi if [ ! -f $1 ]; then echo "File not found!" exit 1 fi
bucts="unknown" flashromsst="unknown" flashrommacronix="unknown" if [ -f "DEBLOB" ]; then bucts="./bucts/bucts" flashromsst="./flashrom/flashrom_lenovobios_sst" flashrommacronix="./flashrom/flashrom_lenovobios_macronix" elif [ $(uname -i) = "i686" ] || [ $(uname -m) = "i686" ]; then bucts="./bucts/i686/bucts" flashromsst="./flashrom/i686/flashrom_lenovobios_sst" flashrommacronix="./flashrom/i686/flashrom_lenovobios_macronix" elif [ $(uname -i) = "x86_64" ] || [ $(uname -m) = "x86_64" ]; then bucts="./bucts/x86_64/bucts" flashromsst="./flashrom/x86_64/flashrom_lenovobios_sst" flashrommacronix="./flashrom/x86_64/flashrom_lenovobios_macronix" else echo "This script must be run on an i686 or x86_64 host. x86_64 is recommended." exit 1 fi uname -i) uname -i uname -m) uname -m
# Set bucts # this means we are working in src if [ ! -f "$bucts" ]; then echo "BUCTS failed. Make sure BUC.TS is 1, or else you will brick your machine. ABORTING so as to protect against bricking the machine." exit 1 fi
$(echo $bucts) 1 echo $bucts) echo $bucts bucts utility version 'withoutgit' Using LPC bridge 8086:27b9 at 0000:1f.00 Current BUC.TS=0 - 128kb address range 0xFFFE0000-0xFFFFFFFF is untranslated Updated BUC.TS=1 - 64kb address ranges at 0xFFFE0000 and 0xFFFF0000 are swapped
$(echo $flashromsst) -p internal -w $1 echo $flashromsst) echo $flashromsst flashrom v0.9.8-unknown on Linux 3.2.0-4-686-pae (i686) flashrom is free software, get the source code at http://www.flashrom.org
Calibrating delay loop... OK. Found chipset "Intel ICH7M". Enabling flash write... WARNING: SPI Configuration Lockdown activated. OK. Found SST flash chip "SST25VF016B" (2048 kB, SPI) mapped at physical address 0xffe00000. Reading old flash chip contents... done. Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0 Reading current flash chip contents... done. Looking for another erase function. spi_block_erase_52 failed during command execution at address 0x0 Reading current flash chip contents... done. Looking for another erase function. Transaction error! spi_block_erase_d8 failed during command execution at address 0x1f0000 Reading current flash chip contents... done. Looking for another erase function. spi_chip_erase_60 failed during command execution Reading current flash chip contents... done. Looking for another erase function. spi_chip_erase_c7 failed during command execution Looking for another erase function. No usable erase functions left. FAILED! Uh oh. Erase/write failed. Checking if anything has changed. Reading current flash chip contents... done. Apparently at least some data has changed. Your flash chip is in an unknown state. Get help on IRC at chat.freenode.net (channel #flashrom) or mail flashrom@flashrom.org with the subject "FAILED: <your board name>"! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! $(echo $flashrommacronix) -p internal -w $1 echo $flashrommacronix) echo $flashrommacronix flashrom v0.9.8-unknown on Linux 3.2.0-4-686-pae (i686) flashrom is free software, get the source code at http://www.flashrom.org
Calibrating delay loop... OK. Found chipset "Intel ICH7M". Enabling flash write... WARNING: SPI Configuration Lockdown activated. OK. No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically.
David Griffith wrote:
lenovobios_firstflash and lenovobios_secondflash scripts
Please do not confuse coreboot with libreboot. Instructions for/about libreboot are specific to that project, and nothing that the coreboot community can support you with.
Did I actually succeed in flashing my T60p?
The first flash was successful, as you are clearly using coreboot. :)
It's important that you flash again. Now that you have coreboot just run flashrom to write the coreboot.rom. Set the BUC.TS bit appropriately, otherwise your machine will not boot anymore after NVRAM battery outage.
I wrote pretty clear step-by-step instructions for all this for the X60 quite some time ago. I hope they are still available somewhere.
Did I do anything wrong?
Not really, only that you used instructions and tools that apply to libreboot and expected them to also suit coreboot.
How do I fix the trackpoint
AFAIK this is resolved by adding a delay to SeaBIOS. The coreboot build system used to do so automatically, but maybe that has been broken, or maybe it never was there for the T60.
and get rid of the whine?
Noone knows. What is known is that it is related to switching between various power saving states and that you can do various things to work around it.
One is to add idle=halt to the kernel command line. This will significantly increase power consumption and make the machine run significantly hotter. Another is to restrict which C-states the CPU can enter. Same drawbacks. Another is to blacklist uhci_hcd which causes constant wakeups, every ms, drawback you can not plug low- and full speed USB devices directly into the mainboard, but only via a high speed hub with TT. You'll still hear odd noise without uhci_hcd but not constantly like now.
Please research this problem and provide the project with a proper fix. It might involve researching undocumented power saving properties of the 945 platform. Thank you.
//Peter
On Thu, 12 May 2016, Peter Stuge wrote:
David Griffith wrote:
lenovobios_firstflash and lenovobios_secondflash scripts
Please do not confuse coreboot with libreboot. Instructions for/about libreboot are specific to that project, and nothing that the coreboot community can support you with.
I didn't confuse the two. I was just following the first hit I got when searching for "coreboot thinkpad t60p"
Did I actually succeed in flashing my T60p?
The first flash was successful, as you are clearly using coreboot. :)
It's important that you flash again. Now that you have coreboot just run flashrom to write the coreboot.rom. Set the BUC.TS bit appropriately, otherwise your machine will not boot anymore after NVRAM battery outage.
I did the flash again and the result after rebooting is a long beep followed by two short beeps. According to what I find with Google, the laptop is bricked and I need to open it up to get at the boot flash chip and flash it with a bus pirate.
I wrote pretty clear step-by-step instructions for all this for the X60 quite some time ago. I hope they are still available somewhere.
Did the instructions resemble this? https://www.coreboot.org/Board:lenovo/x60/Installation
Did I do anything wrong?
Not really, only that you used instructions and tools that apply to libreboot and expected them to also suit coreboot.
How do I fix the trackpoint
AFAIK this is resolved by adding a delay to SeaBIOS. The coreboot build system used to do so automatically, but maybe that has been broken, or maybe it never was there for the T60.
Where is/was this delay?
and get rid of the whine?
Noone knows. What is known is that it is related to switching between various power saving states and that you can do various things to work around it.
One is to add idle=halt to the kernel command line. This will significantly increase power consumption and make the machine run significantly hotter. Another is to restrict which C-states the CPU can enter. Same drawbacks. Another is to blacklist uhci_hcd which causes constant wakeups, every ms, drawback you can not plug low- and full speed USB devices directly into the mainboard, but only via a high speed hub with TT. You'll still hear odd noise without uhci_hcd but not constantly like now.
Please research this problem and provide the project with a proper fix. It might involve researching undocumented power saving properties of the 945 platform. Thank you.
I'll see what I can do. In https://www.coreboot.org/pipermail/coreboot/2014-June/078099.html you suggested clever use of an oscilloscope. Precisely where and how would you suggest probing?
Has anyone given thought to including OpenBIOS as an option in the Payload menu of menuconfig?
Hi,
David Griffith wrote:
The first flash was successful, as you are clearly using coreboot. :)
It's important that you flash again. Now that you have coreboot just run flashrom to write the coreboot.rom. Set the BUC.TS bit appropriately, otherwise your machine will not boot anymore after NVRAM battery outage.
I did the flash again and the result after rebooting is a long beep followed by two short beeps.
So you flashed but did not set BUC.TS appropriately.
According to what I find with Google, the laptop is bricked and I need to open it up to get at the boot flash chip and flash it with a bus pirate.
You can try removing power and NVRAM battery from the board first.
Leave the board completely unpowered, no charger, no main battery and no NVRAM battery, for half a minute or so. Then connect everything again.
It might work, but on the other hand the beeping suggests that your top 64k is still the factory BIOS bootblock, in which case BUC.TS will be set=0, and then removing the NVRAM battery doesn't help, because that only resets from 1 to 0.
If your top 64k is still the factory BIOS bootblock then something went wrong when you flashed now. Upstream flashrom will have output an error message. I would not recommend using anything else.
I wrote pretty clear step-by-step instructions for all this for the X60 quite some time ago. I hope they are still available somewhere.
Did the instructions resemble this? https://www.coreboot.org/Board:lenovo/x60/Installation
Yes, just that some descriptions are wrong.
The commands are still correct though, and older simpler content is there.
I also find it annoyingly confusing to link to random binaries from libreboot.org.
How do I fix the trackpoint
AFAIK this is resolved by adding a delay to SeaBIOS. The coreboot build system used to do so automatically, but maybe that has been broken, or maybe it never was there for the T60.
Where is/was this delay?
git grep SEABIOS_PS2_TIMEOUT
and get rid of the whine?
Please research this problem and provide the project with a proper fix.
I'll see what I can do. In https://www.coreboot.org/pipermail/coreboot/2014-June/078099.html you suggested clever use of an oscilloscope. Precisely where and how would you suggest probing?
I can't tell you. The hard part is not to take a probe to the mainboard, but to study the circuitry, understand it, find out what is happening why and then construct a fix. I haven't.
//Peter
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David Griffith -
Peter Stuge