On 29.04.2008 05:55, ron minnich wrote:
If somebody could ack this I can close out the recent
Sure, but see below.
---------- Forwarded message ----------
From: ron minnich <rminnich(a)gmail.com>
Date: Fri, Apr 18, 2008 at 10:09 PM
Subject: Re: DBE62 v3 strangeness since v3 rev 649
To: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>
Cc: Coreboot <coreboot(a)coreboot.org>
On Tue, Apr 15, 2008 at 2:52 PM, Carl-Daniel Hailfinger
this one is for you: Your commit 649 had a few probably unintended side
- set_delay_control thinks zero DIMMs are installed because
SPD_PRIMARY_SDRAM_WIDTH does not exist in the SPD table.
- Due to that, the GLCP_DELAY_CONTROLS msr is set to 0.
Please confirm that you really wanted these settings.
This mistake arose out of my attempt to clean up the namings of things
in the original initram. It had names from two sources.
This patch cleans up that error, and is my attempt at cleaning up the
issue in device/device.c, which I actually don't understand.
That's the big problem. I have no idea whether it is allowed to have
bus->dev==NULL at that point in time. If it is not allowed, we should
add a big fat warning. If it is allowed, your fix is absolutely correct.
This patch allows me to almost boot a Plan 9 kernel
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>