On Mon, Feb 10, 2014 at 11:59 AM, David Hubbard < david.c.hubbard+coreboot@gmail.com> wrote:
On Mon, Feb 10, 2014 at 12:16 AM, HacKurx hackurx@gmail.com wrote:
Please double check IDSOPT_IDS_ENABLED.
I have first-hand experience with Rudolf's suggestion to use that
#define, I
have an F2A85-M as well. With IDSOPT_IDS_ENABLED, the serial output is significantly longer. I suspect the build system does not catch the
change
since it's not in menuconfig.
Perhaps try 'make clean' followed by all the normal build steps?
I tried several times but I still get the same result. I tried to start with clean git, and I've already used "make clean" to no avail. If in doubt, do not hesitate to create a rom for me that I test.
So the output now that I can get without this: coreboot-4.0-5454-g400c05c-dirty vendredi 7 février 2014, 09:25:15 (UTC+0100) starting... POST: 0x34 BSP Family_Model: 00610f31 cpu_init_detectedx = 00000000 POST: 0x37 agesawrapper_amdinitreset
Very odd. I had hoped it was something easy. I wonder what differs for Richland (as Idwer said) so that it doesn't work. My best understanding of Richland (A10-6800K) is that the memory controller has higher rated speeds but should work with Trinity AGESA code, since the Trinity AGESA code already had the ability to overclock to 2133 MHz DDR3.
It seems the problem is getting a good debug log with IDSOPT_IDS_ENABLED, and that is baffling. I've attached a coreboot image, but please check the config and use cbfstool for payloads *before* flashing it.
David
Here is the .config I used. Also, this is a pretty old version of coreboot (7bb29d72ab89c300fa899a8cf39803ae8f101ff4).
The email with the rom attached is too big for the coreboot list, but HacKurx, please let me know if you try out the rom.
David
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David Hubbard