[v2] r4335 - in trunk/coreboot-v2: src/console src/cpu/amd/dualcore src/cpu/amd/model_fxx src/cpu/amd/quadcore src/cpu/intel/hyperthreading src/include/console src/include/pc80 src/mainboard/amd/dbm690t src/mainboard/amd/pistachio src/mainboard/amd/serengeti_cheetah src/mainboard/amd/serengeti_cheetah_fam10 src/mainboard/arima/hdama src/mainboard/asus/a8n_e src/mainboard/asus/a8v-e_se src/mainboard/asus/m2v-mx_se src/mainboard/broadcom/blast src/mainboard/dell/s1850 src/mainboard/gigabyte/ga_2761
Author: libv Date: 2009-06-03 16:19:33 +0200 (Wed, 03 Jun 2009) New Revision: 4335
Modified: trunk/coreboot-v2/src/console/console.c trunk/coreboot-v2/src/console/printk.c trunk/coreboot-v2/src/console/uart8250_console.c trunk/coreboot-v2/src/cpu/amd/dualcore/amd_sibling.c trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_init.c trunk/coreboot-v2/src/cpu/amd/quadcore/amd_sibling.c trunk/coreboot-v2/src/cpu/intel/hyperthreading/intel_sibling.c trunk/coreboot-v2/src/include/console/console.h trunk/coreboot-v2/src/include/pc80/mc146818rtc.h trunk/coreboot-v2/src/mainboard/amd/dbm690t/cmos.layout trunk/coreboot-v2/src/mainboard/amd/pistachio/cmos.layout trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cmos.layout trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout trunk/coreboot-v2/src/mainboard/arima/hdama/cmos.layout trunk/coreboot-v2/src/mainboard/asus/a8n_e/cmos.layout trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cmos.layout trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cmos.layout trunk/coreboot-v2/src/mainboard/broadcom/blast/cmos.layout trunk/coreboot-v2/src/mainboard/dell/s1850/cmos.layout trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/cmos.layout trunk/coreboot-v2/src/mainboard/hp/dl145_g3/cmos.layout trunk/coreboot-v2/src/mainboard/ibm/e325/cmos.layout trunk/coreboot-v2/src/mainboard/ibm/e326/cmos.layout trunk/coreboot-v2/src/mainboard/intel/jarrell/cmos.layout trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/cmos.layout trunk/coreboot-v2/src/mainboard/iwill/dk8s2/cmos.layout trunk/coreboot-v2/src/mainboard/iwill/dk8x/cmos.layout trunk/coreboot-v2/src/mainboard/msi/ms7135/cmos.layout trunk/coreboot-v2/src/mainboard/msi/ms7260/cmos.layout trunk/coreboot-v2/src/mainboard/msi/ms9185/cmos.layout trunk/coreboot-v2/src/mainboard/msi/ms9282/cmos.layout trunk/coreboot-v2/src/mainboard/newisys/khepri/cmos.layout trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/cmos.layout trunk/coreboot-v2/src/mainboard/sunw/ultra40/cmos.layout trunk/coreboot-v2/src/mainboard/supermicro/h8dme/cmos.layout trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/cmos.layout trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/cmos.layout trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/cmos.layout trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/cmos.layout trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/cmos.layout trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/cmos.layout trunk/coreboot-v2/src/mainboard/technexion/tim8690/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2735/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2850/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2875/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2880/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2881/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2882/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2885/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2891/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2892/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2895/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2912/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s4880/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s4882/cmos.layout trunk/coreboot-v2/src/northbridge/amd/amdfam10/misc_control.c trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c trunk/coreboot-v2/src/northbridge/amd/amdk8/misc_control.c trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c trunk/coreboot-v2/src/pc80/mc146818rtc.c trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_acpi.c trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_lpc.c trunk/coreboot-v2/src/southbridge/amd/amd8131/amd8131_bridge.c trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sm.c trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_lpc.c trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_lpc.c trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_lpc.c trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c trunk/coreboot-v2/src/southbridge/intel/pxhd/pxhd_bridge.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c trunk/coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c trunk/coreboot-v2/src/superio/winbond/w83627ehg/superio.c trunk/coreboot-v2/src/superio/winbond/w83627hf/superio.c trunk/coreboot-v2/util/options/build_opt_tbl.c Log: Revert "CMOS: Add set_option and rework get_option."
This reverts commit eb7bb49eb5b48c39baf7a256b7c74e23e3da5660.
Stepan pointed out that "s" means string, which makes the following statement in this commit message invalid: "Since we either have reserved space (which we shouldn't do anything with in these two functions), an enum or a hexadecimal value, unsigned int seemed like the way to go."
Signed-off-by: Luc Verhaegen libv@skynet.be Acked-by: Luc Verhaegen libv@skynet.be
Modified: trunk/coreboot-v2/src/console/console.c =================================================================== --- trunk/coreboot-v2/src/console/console.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/console/console.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -14,10 +14,9 @@ void console_init(void) { struct console_driver *driver; - - if (get_option("debug_level", &console_loglevel)) - console_loglevel = DEFAULT_CONSOLE_LOGLEVEL; - + if(get_option(&console_loglevel, "debug_level")) + console_loglevel=DEFAULT_CONSOLE_LOGLEVEL; + for(driver = console_drivers; driver < econsole_drivers; driver++) { if (!driver->init) continue;
Modified: trunk/coreboot-v2/src/console/printk.c =================================================================== --- trunk/coreboot-v2/src/console/printk.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/console/printk.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -9,9 +9,18 @@ #include <smp/spinlock.h> #include <console/console.h>
+/* printk's without a loglevel use this.. */ +#define DEFAULT_MESSAGE_LOGLEVEL 4 /* BIOS_WARNING */ + +/* We show everything that is MORE important than this.. */ +#define MINIMUM_CONSOLE_LOGLEVEL 1 /* Minimum loglevel we let people use */ + /* Keep together for sysctl support */
-unsigned int console_loglevel = DEFAULT_CONSOLE_LOGLEVEL; +int console_loglevel = DEFAULT_CONSOLE_LOGLEVEL; +int default_message_loglevel = DEFAULT_MESSAGE_LOGLEVEL; +int minimum_console_loglevel = MINIMUM_CONSOLE_LOGLEVEL; +int default_console_loglevel = DEFAULT_CONSOLE_LOGLEVEL;
void display(char*); extern int vtxprintf(void (*)(unsigned char), const char *, va_list);
Modified: trunk/coreboot-v2/src/console/uart8250_console.c =================================================================== --- trunk/coreboot-v2/src/console/uart8250_console.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/console/uart8250_console.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -29,10 +29,10 @@ static void ttyS0_init(void) { static const unsigned char div[8]={1,2,3,6,12,24,48,96}; - unsigned int b_index=0; + int b_index=0; unsigned int divisor=TTYS0_DIV;
- if(!get_option("baud_rate", &b_index)) { + if(get_option(&b_index,"baud_rate")==0) { divisor=div[b_index]; } uart8250_init(TTYS0_BASE, divisor, TTYS0_LCS);
Modified: trunk/coreboot-v2/src/cpu/amd/dualcore/amd_sibling.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/dualcore/amd_sibling.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/cpu/amd/dualcore/amd_sibling.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -14,7 +14,7 @@ #include <cpu/amd/amdk8_sysconf.h>
static int first_time = 1; -static uint32_t disable_siblings = !CONFIG_LOGICAL_CPUS; +static int disable_siblings = !CONFIG_LOGICAL_CPUS;
#include "dualcore_id.c"
@@ -62,7 +62,7 @@ unsigned nb_cfg_54; int bsp_apic_id = lapicid(); // bsp apicid
- get_option("dual_core", &disable_siblings); + get_option(&disable_siblings, "dual_core");
//get the nodes number dev = dev_find_slot(0, PCI_DEVFN(0x18,0)); @@ -127,7 +127,7 @@ /* On the bootstrap processor see if I want sibling cpus enabled */ if (first_time) { first_time = 0; - get_option("dual_core", &disable_siblings); + get_option(&disable_siblings, "dual_core"); } result = cpuid(0x80000008); /* See how many sibling cpus we have */
Modified: trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_init.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_init.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_init.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -248,7 +248,7 @@ struct mtrr_state mtrr_state;
device_t f1_dev, f2_dev, f3_dev; - uint32_t enable_scrubbing; + int enable_scrubbing; uint32_t dcl;
f1_dev = dev_find_slot(0, PCI_DEVFN(0x18 + node_id, 1)); @@ -266,7 +266,7 @@
/* See if we scrubbing should be enabled */ enable_scrubbing = 1; - get_option("hw_scrubber", &enable_scrubbing); + get_option(&enable_scrubbing, "hw_scrubber");
/* Enable cache scrubbing at the lowest possible rate */ if (enable_scrubbing) {
Modified: trunk/coreboot-v2/src/cpu/amd/quadcore/amd_sibling.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/quadcore/amd_sibling.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/cpu/amd/quadcore/amd_sibling.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -82,7 +82,7 @@
u32 disable_siblings = !CONFIG_LOGICAL_CPUS;
- get_option("quad_core", &disable_siblings); + get_option(&disable_siblings, "quad_core");
siblings = get_max_siblings(sysconf.nodes);
Modified: trunk/coreboot-v2/src/cpu/intel/hyperthreading/intel_sibling.c =================================================================== --- trunk/coreboot-v2/src/cpu/intel/hyperthreading/intel_sibling.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/cpu/intel/hyperthreading/intel_sibling.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -7,7 +7,7 @@ #include <smp/spinlock.h>
static int first_time = 1; -static uint32_t disable_siblings = !CONFIG_LOGICAL_CPUS; +static int disable_siblings = !CONFIG_LOGICAL_CPUS;
void intel_sibling_init(device_t cpu) { @@ -17,7 +17,7 @@ /* On the bootstrap processor see if I want sibling cpus enabled */ if (first_time) { first_time = 0; - get_option("hyper_threading", &disable_siblings); + get_option(&disable_siblings, "hyper_threading"); } result = cpuid(1); /* Is hyperthreading supported */
Modified: trunk/coreboot-v2/src/include/console/console.h =================================================================== --- trunk/coreboot-v2/src/include/console/console.h 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/include/console/console.h 2009-06-03 14:19:33 UTC (rev 4335) @@ -26,7 +26,7 @@ extern struct console_driver console_drivers[]; extern struct console_driver econsole_drivers[];
-extern unsigned int console_loglevel; +extern int console_loglevel; int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));
#define printk_emerg(fmt, arg...) do_printk(BIOS_EMERG ,fmt, ##arg)
Modified: trunk/coreboot-v2/src/include/pc80/mc146818rtc.h =================================================================== --- trunk/coreboot-v2/src/include/pc80/mc146818rtc.h 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/include/pc80/mc146818rtc.h 2009-06-03 14:19:33 UTC (rev 4335) @@ -94,9 +94,11 @@
#if !defined(ASSEMBLY) void rtc_init(int invalid); - -int get_option(char *name, unsigned int *value); -int set_option(char *name, unsigned int value); +#if USE_OPTION_TABLE == 1 +int get_option(void *dest, char *name); +#else +static inline int get_option(void *dest, char *name) { return -2; } #endif +#endif
#endif /* PC80_MC146818RTC_H */
Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -64,7 +64,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory
Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -64,7 +64,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1
Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1
Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory
Modified: trunk/coreboot-v2/src/mainboard/arima/hdama/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/arima/hdama/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/arima/hdama/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1
Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -42,7 +42,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu - 728 256 r 0 user_data + 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1
Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1
Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1
Modified: trunk/coreboot-v2/src/mainboard/broadcom/blast/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/broadcom/blast/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/broadcom/blast/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1
Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/dell/s1850/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/dell/s1850/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -37,7 +37,7 @@ 424 4 e 7 boot_third 428 4 h 0 boot_index 432 8 h 0 boot_countdown -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved_memory
Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -64,7 +64,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory
Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -64,7 +64,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1
Modified: trunk/coreboot-v2/src/mainboard/hp/dl145_g3/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/hp/dl145_g3/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/hp/dl145_g3/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory
Modified: trunk/coreboot-v2/src/mainboard/ibm/e325/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e325/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/ibm/e325/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1
Modified: trunk/coreboot-v2/src/mainboard/ibm/e326/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e326/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/ibm/e326/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1
Modified: trunk/coreboot-v2/src/mainboard/intel/jarrell/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/jarrell/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/intel/jarrell/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -39,7 +39,7 @@ 424 4 e 7 boot_third 428 4 h 0 boot_index 432 8 h 0 boot_countdown -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved_memory
Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1
Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8s2/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8s2/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8s2/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1
Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8x/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8x/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8x/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1
Modified: trunk/coreboot-v2/src/mainboard/msi/ms7135/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7135/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/msi/ms7135/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory
Modified: trunk/coreboot-v2/src/mainboard/msi/ms7260/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7260/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/msi/ms7260/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -65,7 +65,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory
Modified: trunk/coreboot-v2/src/mainboard/msi/ms9185/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9185/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/msi/ms9185/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory
Modified: trunk/coreboot-v2/src/mainboard/msi/ms9282/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9282/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/msi/ms9282/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved_memory
Modified: trunk/coreboot-v2/src/mainboard/newisys/khepri/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/newisys/khepri/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/newisys/khepri/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1
Modified: trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -64,7 +64,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory
Modified: trunk/coreboot-v2/src/mainboard/sunw/ultra40/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/sunw/ultra40/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory
Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -64,7 +64,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1
Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -64,7 +64,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1
Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -37,7 +37,7 @@ 424 4 e 7 boot_third 428 4 h 0 boot_index 432 8 h 0 boot_countdown -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved_memory
Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -37,7 +37,7 @@ 424 4 e 7 boot_third 428 4 h 0 boot_index 432 8 h 0 boot_countdown -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved_memory
Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -37,7 +37,7 @@ 424 4 e 7 boot_third 428 4 h 0 boot_index 432 8 h 0 boot_countdown -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved_memory
Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -37,7 +37,7 @@ 424 4 e 7 boot_third 428 4 h 0 boot_index 432 8 h 0 boot_countdown -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved_memory
Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -37,7 +37,7 @@ 424 4 e 7 boot_third 428 4 h 0 boot_index 432 8 h 0 boot_countdown -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved_memory
Modified: trunk/coreboot-v2/src/mainboard/technexion/tim8690/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim8690/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/technexion/tim8690/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -64,7 +64,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2735/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2735/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/tyan/s2735/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -41,7 +41,7 @@ 432 8 h 0 boot_countdown #440 4 e 9 slow_cpu 444 1 e 1 nmi -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2850/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2850/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/tyan/s2850/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2875/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2875/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/tyan/s2875/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2880/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2880/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/tyan/s2880/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2881/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2881/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/tyan/s2881/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2882/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2882/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/tyan/s2882/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2885/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2885/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/tyan/s2885/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -64,7 +64,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -64,7 +64,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory
Modified: trunk/coreboot-v2/src/mainboard/tyan/s4880/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4880/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/tyan/s4880/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory
Modified: trunk/coreboot-v2/src/mainboard/tyan/s4882/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4882/cmos.layout 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/mainboard/tyan/s4882/cmos.layout 2009-06-03 14:19:33 UTC (rev 4335) @@ -43,7 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -728 256 r 0 user_data +728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 reserved_memory1
Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/misc_control.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdfam10/misc_control.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/misc_control.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -64,7 +64,7 @@ }
iommu = 1; - get_option("iommu", &iommu); + get_option(&iommu, "iommu");
if (iommu) { /* Add a Gart apeture resource */
Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -1258,7 +1258,7 @@ unsigned nb_cfg_54; unsigned siblings; int cores_found; - uint32_t disable_siblings; + int disable_siblings; unsigned ApicIdCoreIdSize;
nb_cfg_54 = 0; @@ -1271,7 +1271,7 @@
disable_siblings = !CONFIG_LOGICAL_CPUS; #if CONFIG_LOGICAL_CPUS == 1 - get_option("quad_core", &disable_siblings); + get_option(&disable_siblings, "quad_core"); #endif
// for pre_e0, nb_cfg_54 can not be set, ( even set, when you read it
Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/misc_control.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/misc_control.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/misc_control.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -48,7 +48,7 @@ }
iommu = 1; - get_option("iommu", &iommu); + get_option(&iommu, "iommu");
if (iommu) { /* Add a Gart apeture resource */
Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -1177,7 +1177,7 @@ unsigned nb_cfg_54; unsigned siblings; int e0_later_single_core; - uint32_t disable_siblings; + int disable_siblings;
nb_cfg_54 = 0; sysconf.enabled_apic_ext_id = 0; @@ -1190,7 +1190,7 @@
disable_siblings = !CONFIG_LOGICAL_CPUS; #if CONFIG_LOGICAL_CPUS == 1 - get_option("dual_core", &disable_siblings); + get_option(&disable_siblings, "dual_core"); #endif
// for pre_e0, nb_cfg_54 can not be set, ( even set, when you read it still be 0)
Modified: trunk/coreboot-v2/src/pc80/mc146818rtc.c =================================================================== --- trunk/coreboot-v2/src/pc80/mc146818rtc.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/pc80/mc146818rtc.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -197,69 +197,41 @@
#if USE_OPTION_TABLE == 1 -/* - * Functions to save/return values stored in the 256byte cmos. - * - * To be able to use space maximally we want to only store as many bits as - * needed, and not be limited by byte boundaries. We therefor clamp the size - * down to an unsigned int. Since the values that we are allowed to touch are - * either an enum or a hexadecimal value, this size should suit most purposes. - * - * These two functions are doing bitshifting, and are therefor a bit - * nontrivial. To understand these operations, first read the ones outside the - * loop. The ones inside the loop are just adding i to the same calculations, - * with the shift twice inverted, as negative shifts aren't nice. - */ -static unsigned int -get_cmos_value(int bit, int length) +/* This routine returns the value of the requested bits + input bit = bit count from the beginning of the cmos image + length = number of bits to include in the value + ret = a character pointer to where the value is to be returned + output the value placed in ret + returns 0 = successful, -1 = an error occurred +*/ +static int get_cmos_value(unsigned long bit, unsigned long length, void *vret) { - unsigned int tmp; - int i; + unsigned char *ret; + unsigned long byte,byte_bit; + unsigned long i; + unsigned char uchar;
- /* negative left shift --> right shift */ - tmp = cmos_read(bit / 8) >> (bit % 8); - - for (i = 1; (8 * i) < ((bit % 8) + length); i++) - tmp |= cmos_read((bit / 8) + i) << ((8 * i) - (bit % 8)); - - /* 1 << 32 - 1 isn't cool inside an int */ - if (length != 32) - tmp &= (1 << length) - 1; - - return tmp; -} - -static void -set_cmos_value(int bit, int length, unsigned int value) -{ - unsigned int mask; - unsigned char cmos; - int i; - - /* 1 << 32 - 1 isn't cool inside an int */ - if (length != 32) - mask = (1 << length) - 1; - else - mask = -1; - - value &= mask; - - /* negative right shifts --> left shifts */ - cmos = cmos_read(bit / 8); - cmos &= ~(mask << (bit % 8)); - cmos |= value << (bit % 8); - cmos_write(cmos, bit / 8); - - for (i = 1; (8 * i) < ((bit % 8) + length); i++) { - cmos = cmos_read((bit / 8) + i); - cmos &= ~(mask >> ((8 * i) - (bit % 8))); - cmos |= value >> ((8 * i) - (bit % 8)); - cmos_write(cmos, (bit / 8) + i); + /* The table is checked when it is built to ensure all + values are valid. */ + ret = vret; + byte=bit/8; /* find the byte where the data starts */ + byte_bit=bit%8; /* find the bit in the byte where the data starts */ + if(length<9) { /* one byte or less */ + uchar = cmos_read(byte); /* load the byte */ + uchar >>= byte_bit; /* shift the bits to byte align */ + /* clear unspecified bits */ + ret[0] = uchar & ((1 << length) -1); } + else { /* more that one byte so transfer the whole bytes */ + for(i=0;length;i++,length-=8,byte++) { + /* load the byte */ + ret[i]=cmos_read(byte); + } + } + return 0; }
-int -get_option(char *name, unsigned int *value) +int get_option(void *dest, char *name) { extern struct cmos_option_table option_table; struct cmos_option_table *ct; @@ -269,7 +241,7 @@
/* Figure out how long name is */ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - + /* find the requested entry record */ ct=&option_table; ce=(struct cmos_entries*)((unsigned char *)ct + ct->header_length); @@ -284,72 +256,12 @@ printk_err("ERROR: No cmos option '%s'\n", name); return(-2); } - - if (ce->length > 32) { - printk_err("ERROR: cmos option '%s' is too large.\n", name); - return -3; - } - - - *value = get_cmos_value(ce->bit, ce->length); - + + if(get_cmos_value(ce->bit, ce->length, dest)) + return(-3); if(!rtc_checksum_valid(LB_CKS_RANGE_START, - LB_CKS_RANGE_END,LB_CKS_LOC)) + LB_CKS_RANGE_END,LB_CKS_LOC)) return(-4); return(0); } - -int -set_option(char *name, unsigned int value) -{ - extern struct cmos_option_table option_table; - struct cmos_option_table *ct; - struct cmos_entries *ce; - size_t namelen; - int found = 0; - - /* Figure out how long name is */ - namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - - /* find the requested entry record */ - ct = &option_table; - ce = (struct cmos_entries*) ((unsigned char *) ct + ct->header_length); - - for(;ce->tag==LB_TAG_OPTION; - ce=(struct cmos_entries*)((unsigned char *)ce + ce->size)) { - if (memcmp(ce->name, name, namelen) == 0) { - found=1; - break; - } - } - - if (!found) { - printk_err("ERROR: Unknown cmos option '%s'\n", name); - return(-2); - } - - if (ce->length > 32) { - printk_err("ERROR: cmos option '%s' is too large.\n", name); - return -3; - } - - set_cmos_value(ce->bit, ce->length, value); - - /* We should not update the checksum here. */ - - return 0; -} -#else -int -get_option(char *name, unsigned int *value) -{ - return -2; -} - -int -set_option(char *name, unsigned int value) -{ - return -2; -} - #endif /* USE_OPTION_TABLE */
Modified: trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_acpi.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_acpi.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_acpi.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -76,7 +76,7 @@ uint16_t word; uint16_t pm10_bar; uint32_t dword; - uint32_t on; + int on;
#if 0 printk_debug("ACPI: disabling NMI watchdog.. "); @@ -113,7 +113,7 @@ /* power on after power fail */ on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - get_option("power_on_after_fail", &on); + get_option(&on, "power_on_after_fail"); byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); byte &= ~0x40; if (!on) { @@ -130,7 +130,7 @@ /* Throttle the CPU speed down for testing */ on = SLOW_CPU_OFF; - get_option("slow_cpu", &on); + get_option(&on, "slow_cpu"); if(on) { pm10_bar = (pci_read_config16(dev, 0x58)&0xff00); outl(((on<<1)+0x10) ,(pm10_bar + 0x10));
Modified: trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_lpc.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_lpc.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -108,7 +108,7 @@ static void lpc_init(struct device *dev) { uint8_t byte; - uint32_t nmi_option; + int nmi_option;
/* IO APIC initialization */ byte = pci_read_config8(dev, 0x4B); @@ -142,7 +142,7 @@ byte |= (1 << 6); /* clear LPCERR */ pci_write_config8(dev, 0x40, byte); nmi_option = NMI_OFF; - get_option("nmi", &nmi_option); + get_option(&nmi_option, "nmi"); if (nmi_option) { byte |= (1 << 7); /* set NMI */ pci_write_config8(dev, 0x40, byte);
Modified: trunk/coreboot-v2/src/southbridge/amd/amd8131/amd8131_bridge.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/amd8131/amd8131_bridge.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/southbridge/amd/amd8131/amd8131_bridge.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -278,7 +278,7 @@ uint32_t dword; uint16_t word; uint8_t byte; - uint32_t nmi_option; + int nmi_option;
/* Enable memory write and invalidate ??? */ byte = pci_read_config8(dev, 0x04); @@ -323,7 +323,7 @@ /* NMI enable */ nmi_option = NMI_OFF; - get_option("nmi", &nmi_option); + get_option(&nmi_option, "nmi"); if(nmi_option) { dword = pci_read_config32(dev, 0x44); dword |= (1<<0);
Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sm.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sm.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_sm.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -165,7 +165,7 @@
/* power after power fail */ on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - get_option("power_on_after_fail", &on); + get_option(&on, "power_on_after_fail"); byte = pm_ioread(0x74); byte &= ~0x03; if (on) { @@ -226,7 +226,7 @@ byte = inb(0x70); /* RTC70 */ byte_old = byte; nmi_option = NMI_OFF; - get_option("nmi", &nmi_option); + get_option(&nmi_option, "nmi"); if (nmi_option) { byte &= ~(1 << 7); /* set NMI */ printk_info("++++++++++set NMI+++++\n");
Modified: trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c =================================================================== --- trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -23,7 +23,7 @@ { uint8_t byte; uint8_t byte_old; - uint32_t nmi_option; + int nmi_option;
uint32_t dword;
@@ -31,8 +31,8 @@ byte = inb(0x70); // RTC70 byte_old = byte; nmi_option = NMI_OFF; - get_option("nmi", &nmi_option); - if (nmi_option) { + get_option(&nmi_option, "nmi"); + if (nmi_option) { byte &= ~(1 << 7); /* set NMI */ } else { byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
Modified: trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_lpc.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_lpc.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -277,7 +277,7 @@ { uint8_t byte; uint32_t value; - uint32_t pwr_on=MAINBOARD_POWER_ON_AFTER_FAIL; + int pwr_on=MAINBOARD_POWER_ON_AFTER_FAIL;
/* sata settings */ pci_write_config32(dev, 0x58, 0x00001181); @@ -326,7 +326,7 @@
esb6300_enable_lpc(dev);
- get_option("power_on_after_fail", &pwr_on); + get_option(&pwr_on, "power_on_after_fail"); byte = pci_read_config8(dev, 0xa4); byte &= 0xfe; if (!pwr_on) {
Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -297,7 +297,7 @@ static void lpc_init(struct device *dev) { u8 byte; - uint32_t pwr_on = MAINBOARD_POWER_ON_AFTER_FAIL; + int pwr_on = MAINBOARD_POWER_ON_AFTER_FAIL;
setup_ioapic(dev);
@@ -306,7 +306,7 @@
i3100_enable_serial_irqs(dev);
- get_option("power_on_after_fail", &pwr_on); + get_option(&pwr_on, "power_on_after_fail"); byte = pci_read_config8(dev, 0xa4); byte &= 0xfe; if (!pwr_on) {
Modified: trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_lpc.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_lpc.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -88,7 +88,7 @@ { uint32_t dword; int rtc_failed; - uint32_t pwr_on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; uint8_t pmcon3 = pci_read_config8(dev, GEN_PMCON_3);
rtc_failed = pmcon3 & RTC_BATTERY_DEAD; @@ -99,7 +99,7 @@ pmcon3 &= ~RTC_POWER_FAILED; }
- get_option("power_on_after_fail", &pwr_on); + get_option(&pwr_on, "power_on_after_fail"); pmcon3 &= ~SLEEP_AFTER_POWER_FAIL; if (!pwr_on) { pmcon3 |= SLEEP_AFTER_POWER_FAIL; @@ -158,7 +158,7 @@ { uint8_t byte; int pwr_on=-1; - uint32_t nmi_option; + int nmi_option;
/* IO APIC initialization */ i82801ca_enable_ioapic(dev); @@ -186,7 +186,7 @@ outb(byte, 0x61); byte = inb(0x70); nmi_option = NMI_OFF; - get_option("nmi", &nmi_option); + get_option(&nmi_option, "nmi"); if (nmi_option) { byte &= ~(1 << 7); /* set NMI */ outb(byte, 0x70);
Modified: trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -119,7 +119,7 @@ { uint8_t byte; int pwr_on=-1; - uint32_t nmi_option; + int nmi_option;
/* IO APIC initialization */ i82801dbm_enable_ioapic(dev); @@ -159,7 +159,7 @@ outb(byte, 0x61); byte = inb(0x70); nmi_option = NMI_OFF; - get_option("nmi", &nmi_option); + get_option(&nmi_option, "nmi"); if (nmi_option) { byte &= ~(1 << 7); /* set NMI */ outb(byte, 0x70);
Modified: trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_lpc.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_lpc.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -283,7 +283,7 @@ { uint8_t byte; uint32_t value; - uint32_t pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
/* IO APIC initialization */ value = pci_read_config32(dev, 0xd0); @@ -303,7 +303,7 @@ /* Clear SATA to non raid */ pci_write_config8(dev, 0xae, 0x00);
- get_option("power_on_after_fail", &pwr_on); + get_option(&pwr_on, "power_on_after_fail"); byte = pci_read_config8(dev, 0xa4); byte &= 0xfe; if (!pwr_on) {
Modified: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -185,14 +185,14 @@ u8 reg8; u16 reg16;
- uint32_t pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - uint32_t nmi_option; + int pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int nmi_option;
/* Which state do we want to goto after g3 (power restored)? * 0 == S0 Full On * 1 == S5 Soft Off */ - get_option("power_on_after_fail", &pwr_on); + get_option(&pwr_on, "power_on_after_fail"); reg8 = pci_read_config8(dev, GEN_PMCON_3); reg8 &= 0xfe; if (pwr_on) { @@ -216,7 +216,7 @@
reg8 = inb(0x70); nmi_option = NMI_OFF; - get_option("nmi", &nmi_option); + get_option(&nmi_option, "nmi"); if (nmi_option) { printk_info ("NMI sources enabled.\n"); reg8 &= ~(1 << 7); /* Set NMI. */
Modified: trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -180,7 +180,7 @@ { uint8_t byte; int pwr_on = -1; - uint32_t nmi_option; + int nmi_option;
/* power after power fail */ /* FIXME this doesn't work! */ @@ -199,7 +199,7 @@ byte = inb(0x70);
nmi_option = NMI_OFF; - get_option("nmi", &nmi_option); + get_option(&nmi_option, "nmi"); if (nmi_option) { byte &= ~(1 << 7); /* Set NMI. */ outb(byte, 0x70);
Modified: trunk/coreboot-v2/src/southbridge/intel/pxhd/pxhd_bridge.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/pxhd/pxhd_bridge.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/southbridge/intel/pxhd/pxhd_bridge.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -38,12 +38,12 @@
static unsigned int pxhd_scan_bridge(device_t dev, unsigned int max) { - uint32_t bus_100Mhz = 0; + int bus_100Mhz = 0;
dev->link[0].dev = dev; dev->links = 1;
- get_option("pxhd_bus_speed_100", &bus_100Mhz); + get_option(&bus_100Mhz, "pxhd_bus_speed_100"); if(bus_100Mhz) { uint16_t word;
@@ -66,7 +66,7 @@ uint32_t dword; uint16_t word; uint8_t byte; - uint32_t nmi_option; + int nmi_option;
/* Bridge control ISA enable */ pci_write_config8(dev, 0x3e, 0x07); @@ -115,7 +115,7 @@ /* NMI enable */ nmi_option = NMI_OFF; - get_option("nmi", &nmi_option); + get_option(&nmi_option, "nmi"); if(nmi_option) { dword = pci_read_config32(dev, 0x44); dword |= (1<<0);
Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -179,7 +179,7 @@ static void lpc_init(device_t dev) { uint8_t byte, byte_old; - uint32_t on, nmi_option; + int on, nmi_option;
lpc_common_init(dev);
@@ -199,7 +199,7 @@
/* power after power fail */ on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - get_option("power_on_after_fail", &on); + get_option(&on, "power_on_after_fail"); byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); byte &= ~0x40; if (!on) @@ -209,7 +209,7 @@
/* Throttle the CPU speed down for testing. */ on = SLOW_CPU_OFF; - get_option("slow_cpu", &on); + get_option(&on, "slow_cpu"); if (on) { uint16_t pm10_bar; uint32_t dword; @@ -238,7 +238,7 @@ byte = inb(0x70); /* RTC70 */ byte_old = byte; nmi_option = NMI_OFF; - get_option("nmi", &nmi_option); + get_option(&nmi_option, "nmi"); if (nmi_option) { byte &= ~(1 << 7); /* Set NMI. */ } else {
Modified: trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -170,8 +170,8 @@ { uint8_t byte; uint8_t byte_old; - uint32_t on; - uint32_t nmi_option; + int on; + int nmi_option;
lpc_common_init(dev, 1);
@@ -184,7 +184,7 @@
#if 1 on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - get_option("power_on_after_fail", &on); + get_option(&on, "power_on_after_fail"); byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); byte &= ~0x40; if (!on) { @@ -195,7 +195,7 @@ #endif /* Throttle the CPU speed down for testing */ on = SLOW_CPU_OFF; - get_option("slow_cpu", &on); + get_option(&on, "slow_cpu"); if(on) { uint16_t pm10_bar; uint32_t dword; @@ -225,7 +225,7 @@ byte = inb(0x70); // RTC70 byte_old = byte; nmi_option = NMI_OFF; - get_option("nmi", &nmi_option); + get_option(&nmi_option, "nmi"); if (nmi_option) { byte &= ~(1 << 7); /* set NMI */ } else {
Modified: trunk/coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -167,8 +167,8 @@ { uint8_t byte; uint8_t byte_old; - uint32_t on; - uint32_t nmi_option; + int on; + int nmi_option;
printk_debug("LPC_INIT -------->\n"); init_pc_keyboard(0x60, 0x64, 0); @@ -180,7 +180,7 @@
on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - get_option("power_on_after_fail", &on); + get_option(&on, "power_on_after_fail"); byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); byte &= ~0x40; if (!on) { @@ -191,7 +191,7 @@
/* Throttle the CPU speed down for testing */ on = SLOW_CPU_OFF; - get_option("slow_cpu", &on); + get_option(&on, "slow_cpu"); if(on) { uint16_t pm10_bar; uint32_t dword; @@ -213,7 +213,7 @@ byte = inb(0x70); // RTC70 byte_old = byte; nmi_option = NMI_OFF; - get_option("nmi", &nmi_option); + get_option(&nmi_option, "nmi"); if (nmi_option) { byte &= ~(1 << 7); /* set NMI */ } else {
Modified: trunk/coreboot-v2/src/superio/winbond/w83627ehg/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/winbond/w83627ehg/superio.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/superio/winbond/w83627ehg/superio.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -69,9 +69,9 @@ static void init_acpi(device_t dev) { uint8_t value = 0x20; - uint32_t power_on = 1; + int power_on = 1;
- get_option("power_on_after_fail", &power_on); + get_option(&power_on, "power_on_after_fail"); pnp_enter_ext_func_mode(dev); pnp_write_index(dev->path.pnp.port, 7, 0x0a); value = pnp_read_config(dev, 0xe4);
Modified: trunk/coreboot-v2/src/superio/winbond/w83627hf/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/winbond/w83627hf/superio.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/src/superio/winbond/w83627hf/superio.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -52,9 +52,9 @@ static void init_acpi(device_t dev) { uint8_t value = 0x20; - uint32_t power_on = 1; + int power_on = 1;
- get_option("power_on_after_fail", &power_on); + get_option(&power_on, "power_on_after_fail"); pnp_enter_ext_func_mode(dev); pnp_write_index(dev->path.pnp.port,7,0x0a); value = pnp_read_config(dev, 0xE4);
Modified: trunk/coreboot-v2/util/options/build_opt_tbl.c =================================================================== --- trunk/coreboot-v2/util/options/build_opt_tbl.c 2009-06-03 14:19:20 UTC (rev 4334) +++ trunk/coreboot-v2/util/options/build_opt_tbl.c 2009-06-03 14:19:33 UTC (rev 4335) @@ -17,52 +17,85 @@
static unsigned char cmos_table[4096];
+/* This array is used to isolate bits that are to be changed in a byte */ +static unsigned char clip[9]={0,1,3,7,0x0f,0x1f,0x3f,0x7f,0xff}; + + /* This routine loops through the entried and tests if any of the fields overlap input entry_start = the memory pointer to the start of the entries. entry_end = the byte past the entries. output none if there is an overlap, the routine exits, other wise it returns. */ - void test_for_entry_overlaps(void *entry_start, void *entry_end) { + int ptr; char *cptr; - struct cmos_entries *ce = NULL; + int buffer_bit_size; + int offset; + int byte; + int byte_length; + struct cmos_entries *ce; unsigned char test[CMOS_IMAGE_BUFFER_SIZE]; - int i; + unsigned char set;
- memset(test, 0, CMOS_IMAGE_BUFFER_SIZE); + /* calculate the size of the cmos buffer in bits */ + buffer_bit_size=(CMOS_IMAGE_BUFFER_SIZE*8); + /* clear the temporary test buffer */ + for(ptr=0; ptr < CMOS_IMAGE_BUFFER_SIZE; ptr++) + test[ptr]=0;
- for (cptr = entry_start; cptr < (char *)entry_end; cptr += ce->size) { - ce = (struct cmos_entries *)cptr; - - /* Only reserved space can be larger than 32bits */ - if ((ce->length > 32) && (ce->config != 'r')) { - fprintf(stderr, "Error: Entry %s is longer than" - " 32bits.\n", ce->name); - exit(1); - } - + /* loop through each entry in the table testing for errors */ + for(cptr = entry_start; cptr < (char *)entry_end; cptr += ce->size) { + ce=(struct cmos_entries *)cptr; /* test if entry goes past the end of the buffer */ - if ((ce->bit + ce->length) > (CMOS_IMAGE_BUFFER_SIZE * 8)) { - fprintf(stderr, "Error: Entry %s exceeds CMOS" - " space.\n", ce->name); + if((ce->bit+ce->length)>buffer_bit_size) { + printf("Error - Entry %s start bit + length must be less than %d\n", + ce->name,buffer_bit_size); exit(1); } - - /* see whether our bits were marked before */ - for (i = ce->bit; i < (ce->bit + ce->length); i++) - if (test[i / 8] & (0x01 << (i % 8))) { - printf("Error: Entry %s overlaps at bit %d.\n", - ce->name, i); + byte=ce->bit/8; + offset=ce->bit%8; + byte_length=ce->length/8; + if(byte_length) { /* entry is 8 bits long or more */ + if(offset) { /* if 8 bits or more long, it must be byte aligned */ + printf("Error - Entry %s length over 8 must be byte aligned\n", + ce->name); exit(1); } - - /* now mark our bits */ - for (i = ce->bit; i < (ce->bit + ce->length); i++) - test[i / 8] |= 0x01 << (i % 8); - + /* test if entries 8 or more in length are even bytes */ + if(ce->length%8){ + printf("Error - Entry %s length over 8 must be a multiple of 8\n", + ce->name); + exit(1); + } + /* test if any of the bits have been previously used */ + for(;byte_length;byte_length--,byte++) { + if(test[byte]) { + printf("Error - Entry %s uses same bits previously used\n", + ce->name); + exit(1); + } + test[byte]=clip[8]; /* set the bits defined in test */ + } + } else { + /* test if bits overlap byte boundaries */ + if(ce->length>(8-offset)) { + printf("Error - Entry %s length overlaps a byte boundry\n", + ce->name); + exit(1); + } + /* test for bits previously used */ + set=(clip[ce->length]<<offset); + if(test[byte]&set) { + printf("Error - Entry %s uses same bits previously used\n", + ce->name); + exit(1); + } + test[byte]|=set; /* set the bits defined in test */ + } } + return; }
/* This routine displays the usage options */ @@ -103,14 +136,48 @@ return value; }
+static int is_ident_digit(int c) +{ + int result; + switch(c) { + case '0': case '1': case '2': case '3': + case '4': case '5': case '6': case '7': + case '8': case '9': + result = 1; + break; + default: + result = 0; + break; + } + return result; +} + static int is_ident_nondigit(int c) { - if (((c >= 'A') && (c <='Z')) || - ((c >= 'a') && (c <='z')) || - (c == '_')) - return 1; - else - return 0; + int result; + switch(c) { + case 'A': case 'B': case 'C': case 'D': + case 'E': case 'F': case 'G': case 'H': + case 'I': case 'J': case 'K': case 'L': + case 'M': case 'N': case 'O': case 'P': + case 'Q': case 'R': case 'S': case 'T': + case 'U': case 'V': case 'W': case 'X': + case 'Y': case 'Z': + case 'a': case 'b': case 'c': case 'd': + case 'e': case 'f': case 'g': case 'h': + case 'i': case 'j': case 'k': case 'l': + case 'm': case 'n': case 'o': case 'p': + case 'q': case 'r': case 's': case 't': + case 'u': case 'v': case 'w': case 'x': + case 'y': case 'z': + case '_': + result = 1; + break; + default: + result = 0; + break; + } + return result; }
static int is_ident(char *str) @@ -123,7 +190,7 @@ do { str++; ch = *str; - } while(ch && (is_ident_nondigit(ch) || isdigit(ch))); + } while(ch && (is_ident_nondigit(ch) || (is_ident_digit(ch)))); result = (ch == '\0'); } return result; @@ -316,7 +383,7 @@ c_enums->config_id=strtol(&line[ptr],(char**)NULL,10); for(;(line[ptr]!=' ')&&(line[ptr]!='\t');ptr++); for(;(line[ptr]==' ')||(line[ptr]=='\t');ptr++); - c_enums->value = strtoul(&line[ptr],(char**)NULL,0); + c_enums->value=strtol(&line[ptr],(char**)NULL,10); for(;(line[ptr]!=' ')&&(line[ptr]!='\t');ptr++); for(;(line[ptr]==' ')||(line[ptr]=='\t');ptr++); for(cnt=0;(line[ptr]!='\n')&&(cnt<31);ptr++,cnt++)
-
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