The controversial decision but the console output is not connected directly to the processor but to the superio Nuvoton. I did not find any settings to enable LPC (LPC_EN) for the Atom C2000 to. In atom-c2000-microserver-datasheet-334978.pdf I found register LPCC (LPC control register). This register includes LPC_CLKOUT1. As far as I understood, the nuvoton uses this signal.
LPC Clock Enabling
The LPC clock signal, LPC_CLKOUT1, is enabled or disabled by the software through the 32-bit LPCC register at offset 84h in the configuration space at bus 0, device 31 (decimal), function 0. The LPC clock signal, LPC_CLKOUT0, is always enabled. It also has an enable/disable bit in the 32-bit LPCC register at offset 84h, but the bit is read-only and always set to enable LPC_CLKOUT0.
I did not see any signals on the oscilloscope. I tried to enable it by adding a function to the coreboot-4.9/src/southbridge/intel/fsp_rangeley/lpc.c file:
/* Tutn on LPC_CLK1 for nuvoton IBASE = 0x50 ILB_LPCC = 0x84 (LPC_CLCOUT[0:1]) */
static void soc_enable_lpc_clk1(struct device *dev) { u32 reg32 = 0; u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0x0f); reg32 = read32(ilb_base + ILB_LPCC); write32(ilb_base + ILB_LPCC, (reg32 | 0x3)); }
Clock signals LPC_CLKOUT1 appeared, but it did not help. Super io does not appear in Linux. What else you need to configure in LPC controller and(or) in Nuvotone so that the device can be seen in Linux?
What utility can I get it with?
You can also compare the register banks of PCI 0:1f.0.
сб, 18 мая 2019 г. в 14:36, Shreesh Chhabbi schhabbi@ircona.com:
Hi,
Is the serial port where you are trying to capture logs, coming out of Nuvoton controller or the Atom Processor? If serial port is coming out of Nuvoton: Usually the controller connected on LPC to the main processor is accessed via IO ports. Controller needs to have code change to support this. If you have Intel CRB's reference code for main processor and controller, you could look for supported commands to EC. I have encountered post code print on the seven segment displays via EC from main processor. But serial console is always directly from main processor. If serial port is coming out of main processor: The UART controller is seen as a PCI device to the CPU. You need to enumerate this and initialize and use it for dumping bytes onto serial console (available in Intel CRB reference code usually).
Thanks, Shreesh Chhabbi Sr. Software Engineer Ircona (www.ircona.com)
-----Original Message----- From: dponamorev@gmail.com dponamorev@gmail.com Sent: Friday 17 May 2019 16:02 To: coreboot@coreboot.org Subject: [coreboot] How to add NUVOTON NCT6776F support with serial port logic enabled ???
There is a Lanner FW-7573 platform based on the Intel Rangeley Atom C2000 series processor. To work with the Serial port in this platform, the NUVOTON NCT6776F chip is connected via the LPC bus to the processor. I just can’t get Serial port working for debuging. I take as a basis intel littleplains board. I tried to add NCT6776F support following the example of other boards - without success. There is no output to the console, and in Linux, the superiotool program does not see the NCT6776F.
On the official version of the BIOS I loaded linux OS and took a dump. (superiotool r => Found Nuvoton NCT6776F/D (C) (id=0xc333) at 0x4e) )
How to add NUVOTON NCT6776F support with serial port logic enabled ???
in devicetree.cb I add:
device pci 1f.0 on # LPC bridge chip superio/nuvoton/nct6776 device pnp 4e.0 off end #Floppy device pnp 4e.1 off end # Parallel port device pnp 4e.2 on # COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end device pnp 4e.3 off end # COM2, IR device pnp 4e.5 off end # Keyboard device pnp 4e.6 off end # CIR device pnp 4e.7 off end # GPIO6 device pnp 4e.107 off end # GPIO7 device pnp 4e.207 off end # GPIO8 device pnp 4e.307 off end # GPIO9 device pnp 4e.8 off end # WDT device pnp 4e.108 off end # GPIO0 device pnp 4e.208 off end # GPIOA device pnp 4e.308 off end # GPIOBASE device pnp 4e.109 off end # GPIO1 device pnp 4e.209 off end # GPIO2 device pnp 4e.309 off end # GPIO3 device pnp 4e.409 off end # GPIO4 device pnp 4e.509 off end # GPIO5 device pnp 4e.609 off end # GPIO6 device pnp 4e.709 off end # GPIO7 device pnp 4e.a on end # ACPI device pnp 4e.b off end # HWM, front pannel LED device pnp 4e.d off end # VID device pnp 4e.e off end # CIR WAKE-UP device pnp 4e.f off end # GPIO device pnp 4e.14 off end # SVID device pnp 4e.16 off end # Deep sleep device pnp 4e.17 off end # GPIOA end end # LPC bridge
In superio.asl i add:
#undef SUPERIO_DEV #undef SUPERIO_PNP_BASE
#define SUPERIO_DEV SIO0 #define SUPERIO_PNP_BASE 0x4e #define NCT6776_SHOW_PP #define NCT6776_SHOW_SP1 #define NCT6776_SHOW_KBC #define NCT6776_SHOW_HWM #define NCT6776_SHOW_GPIO
#include <superio/nuvoton/nct6776/acpi/superio.asl>
in romstage.c add function mainboard_config_superio:
void mainboard_config_superio(void) { /* Enable UART */ nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
/* Select SIO pin states. */ As in Dump........ pnp_write_config(GLOBAL_DEV, 0x13, 0xff); pnp_write_config(GLOBAL_DEV, 0x14, 0xff); pnp_write_config(GLOBAL_DEV, 0x1b, 0x53); pnp_write_config(GLOBAL_DEV, 0x1c, 0x80); pnp_write_config(GLOBAL_DEV, 0x24, 0x24); pnp_write_config(GLOBAL_DEV, 0x27, 0xc0); pnp_write_config(GLOBAL_DEV, 0x2b, 0x03); pnp_write_config(GLOBAL_DEV, 0x2a, 0x00); pnp_write_config(GLOBAL_DEV, 0x2c, 0x80); /* Power RAM in S3. */ //pnp_set_logical_device(ACPI_DEV); //pnp_write_config(ACPI_DEV, 0xe4, 0x10); pnp_set_logical_device(SERIAL_DEV); nuvoton_pnp_exit_conf_state(GLOBAL_DEV); nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); }
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Usually LPC_CLKOUTx signals are programmed to native function, so that controller inside SOC generates the clock required. FSP code for LPC is stable enough to configure LPC controller registers to generate clocks. Did you verify configuration of all LPC gpios? They should be programmed to modes as recommended in EDS/data sheet.
Thanks, Shreesh Chhabbi Sr. Software Engineer Ircona (www.ircona.comhttp://www.ircona.com)
From: Дмитрий Понаморев dponamorev@gmail.com Sent: Wednesday 22 May 2019 16:08 To: Shreesh Chhabbi schhabbi@ircona.com Cc: coreboot@coreboot.org Subject: Re: [coreboot] How to add NUVOTON NCT6776F support with serial port logic enabled ???
The controversial decision but the console output is not connected directly to the processor but to the superio Nuvoton. I did not find any settings to enable LPC (LPC_EN) for the Atom C2000 to. In atom-c2000-microserver-datasheet-334978.pdf I found register LPCC (LPC control register). This register includes LPC_CLKOUT1. As far as I understood, the nuvoton uses this signal.
LPC Clock Enabling The LPC clock signal, LPC_CLKOUT1, is enabled or disabled by the software through the 32-bit LPCC register at offset 84h in the configuration space at bus 0, device 31 (decimal), function 0. The LPC clock signal, LPC_CLKOUT0, is always enabled. It also has an enable/disable bit in the 32-bit LPCC register at offset 84h, but the bit is read-only and always set to enable LPC_CLKOUT0.
I did not see any signals on the oscilloscope. I tried to enable it by adding a function to the coreboot-4.9/src/southbridge/intel/fsp_rangeley/lpc.c file:
/* Tutn on LPC_CLK1 for nuvoton IBASE = 0x50 ILB_LPCC = 0x84 (LPC_CLCOUT[0:1]) */
static void soc_enable_lpc_clk1(struct device *dev) { u32 reg32 = 0; u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0x0f); reg32 = read32(ilb_base + ILB_LPCC); write32(ilb_base + ILB_LPCC, (reg32 | 0x3)); }
Clock signals LPC_CLKOUT1 appeared, but it did not help. Super io does not appear in Linux. What else you need to configure in LPC controller and(or) in Nuvotone so that the device can be seen in Linux?
What utility can I get it with? You can also compare the register banks of PCI 0:1f.0.
сб, 18 мая 2019 г. в 14:36, Shreesh Chhabbi <schhabbi@ircona.commailto:schhabbi@ircona.com>: Hi,
Is the serial port where you are trying to capture logs, coming out of Nuvoton controller or the Atom Processor? If serial port is coming out of Nuvoton: Usually the controller connected on LPC to the main processor is accessed via IO ports. Controller needs to have code change to support this. If you have Intel CRB's reference code for main processor and controller, you could look for supported commands to EC. I have encountered post code print on the seven segment displays via EC from main processor. But serial console is always directly from main processor. If serial port is coming out of main processor: The UART controller is seen as a PCI device to the CPU. You need to enumerate this and initialize and use it for dumping bytes onto serial console (available in Intel CRB reference code usually).
Thanks, Shreesh Chhabbi Sr. Software Engineer Ircona (www.ircona.comhttp://www.ircona.com)
-----Original Message----- From: dponamorev@gmail.commailto:dponamorev@gmail.com <dponamorev@gmail.commailto:dponamorev@gmail.com> Sent: Friday 17 May 2019 16:02 To: coreboot@coreboot.orgmailto:coreboot@coreboot.org Subject: [coreboot] How to add NUVOTON NCT6776F support with serial port logic enabled ???
There is a Lanner FW-7573 platform based on the Intel Rangeley Atom C2000 series processor. To work with the Serial port in this platform, the NUVOTON NCT6776F chip is connected via the LPC bus to the processor. I just can’t get Serial port working for debuging. I take as a basis intel littleplains board. I tried to add NCT6776F support following the example of other boards - without success. There is no output to the console, and in Linux, the superiotool program does not see the NCT6776F.
On the official version of the BIOS I loaded linux OS and took a dump. (superiotool r => Found Nuvoton NCT6776F/D (C) (id=0xc333) at 0x4e) )
How to add NUVOTON NCT6776F support with serial port logic enabled ???
in devicetree.cb I add:
device pci 1f.0 on # LPC bridge chip superio/nuvoton/nct6776 device pnp 4e.0 off end # Floppy device pnp 4e.1 off end # Parallel port device pnp 4e.2 on # COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end device pnp 4e.3 off end # COM2, IR device pnp 4e.5 off end # Keyboard device pnp 4e.6 off end # CIR device pnp 4e.7 off end # GPIO6 device pnp 4e.107 off end # GPIO7 device pnp 4e.207 off end # GPIO8 device pnp 4e.307 off end # GPIO9 device pnp 4e.8 off end # WDT device pnp 4e.108 off end # GPIO0 device pnp 4e.208 off end # GPIOA device pnp 4e.308 off end # GPIOBASE device pnp 4e.109 off end # GPIO1 device pnp 4e.209 off end # GPIO2 device pnp 4e.309 off end # GPIO3 device pnp 4e.409 off end # GPIO4 device pnp 4e.509 off end # GPIO5 device pnp 4e.609 off end # GPIO6 device pnp 4e.709 off end # GPIO7 device pnp 4e.a on end # ACPI device pnp 4e.b off end # HWM, front pannel LED device pnp 4e.d off end # VID device pnp 4e.e off end # CIR WAKE-UP device pnp 4e.f off end # GPIO device pnp 4e.14 off end # SVID device pnp 4e.16 off end # Deep sleep device pnp 4e.17 off end # GPIOA end end # LPC bridge
In superio.asl i add:
#undef SUPERIO_DEV #undef SUPERIO_PNP_BASE
#define SUPERIO_DEV SIO0 #define SUPERIO_PNP_BASE 0x4e #define NCT6776_SHOW_PP #define NCT6776_SHOW_SP1 #define NCT6776_SHOW_KBC #define NCT6776_SHOW_HWM #define NCT6776_SHOW_GPIO
#include <superio/nuvoton/nct6776/acpi/superio.asl>
in romstage.c add function mainboard_config_superio:
void mainboard_config_superio(void) { /* Enable UART */ nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
/* Select SIO pin states. */ As in Dump........ pnp_write_config(GLOBAL_DEV, 0x13, 0xff); pnp_write_config(GLOBAL_DEV, 0x14, 0xff); pnp_write_config(GLOBAL_DEV, 0x1b, 0x53); pnp_write_config(GLOBAL_DEV, 0x1c, 0x80); pnp_write_config(GLOBAL_DEV, 0x24, 0x24); pnp_write_config(GLOBAL_DEV, 0x27, 0xc0); pnp_write_config(GLOBAL_DEV, 0x2b, 0x03); pnp_write_config(GLOBAL_DEV, 0x2a, 0x00); pnp_write_config(GLOBAL_DEV, 0x2c, 0x80);
/* Power RAM in S3. */ //pnp_set_logical_device(ACPI_DEV); //pnp_write_config(ACPI_DEV, 0xe4, 0x10);
pnp_set_logical_device(SERIAL_DEV);
nuvoton_pnp_exit_conf_state(GLOBAL_DEV);
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } _______________________________________________ coreboot mailing list -- coreboot@coreboot.orgmailto:coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.orgmailto:coreboot-leave@coreboot.org
On Wed, May 22, 2019 at 6:14 PM Дмитрий Понаморев dponamorev@gmail.com wrote:
The controversial decision but the console output is not connected directly to the processor but to the superio Nuvoton. I did not find any settings to enable LPC (LPC_EN) for the Atom C2000 to. In atom-c2000-microserver-datasheet-334978.pdf I found register LPCC (LPC control register). This register includes LPC_CLKOUT1. As far as I understood, the nuvoton uses this signal.
Okay then. The paragraphs of datasheet you should be interested are:
24.2.4 about the LPC routing rules. It says anything not positively decoded by SOC integrated peripherals will be routed to LPC.
20.2 and 20.3 to disable the SoC's integrated UART devices. When enabled, they would positively decode 0x3f8 and 0x2f8 (bases) and prevent those from being routed to LPC controller.
If you previously did not have LPC_CLK running for the Nuvoton part in your coreboot build, it explains why util/superiotool did not detect Nuvoton. If you did not do so already, run that tool again. Hopefully you see something on 0x4e now.
SuperIOs typically have another clock input pin (either 24 MHz or 48 MHz) for the baud generator of the UARTs. If you get that Nuvoton detected, and disable SoC UARTs, and still have no serial output, I would trace the source for that clock next.
Regards, Kyösti
Thank for help!
The LPC_CLKOUT1 clock signal appeared but there is no nuvoton chip detected in linux.
I could not turn off the SOC UART yet. With my changes, the system does not start well (stops at post code 0x46, 0x47).
/*Disabled SOC UART1 & UART2*/ u32 reg32; reg32 = pci_read_config32(SOC_LPC_DEV /*(0,1f,0)*/, UART_CONT /*0x80*/); reg32 = reg32 & (~0x3); pci_write_config32(SOC_LPC_DEV, UART_CONT, reg32);
And the most important thing is that the Nuvoton System Clock (48 MHz for the baud generator of the UARTs) is missing. IDT clock synthesizer (9VRS4420DKLFT) is responsible for the formation of this clock. This clock synthesizer provides reference clocks for I/O interfaces, SATA, USB, Gbe and PCI Express. At the initial moment of time, the clock synthesizer is initialized via the SMB bus (I can see it with an oscilloscope). But no 48 MHz clock for Nuvoton. Nuvoton System Clock, use the USB_48M_2X contact of 9VRS4420DKLFT, which is normally not used.
How can I change the IDT clock synthesizer (9VRS4420DKLFT) settings in coreboot? Rather, where can I make changes in coreboot to properly configure IDT clock synthesizer (9VRS4420DKLFT)?
Best Regards, Dmitry Ponamorev
ср, 22 мая 2019 г. в 21:46, Kyösti Mälkki kyosti.malkki@gmail.com:
On Wed, May 22, 2019 at 6:14 PM Дмитрий Понаморев dponamorev@gmail.com wrote:
The controversial decision but the console output is not connected
directly to the processor but to the superio Nuvoton.
I did not find any settings to enable LPC (LPC_EN) for the Atom C2000 to. In atom-c2000-microserver-datasheet-334978.pdf I found register LPCC
(LPC control register).
This register includes LPC_CLKOUT1. As far as I understood, the nuvoton
uses this signal.
Okay then. The paragraphs of datasheet you should be interested are:
24.2.4 about the LPC routing rules. It says anything not positively decoded by SOC integrated peripherals will be routed to LPC.
20.2 and 20.3 to disable the SoC's integrated UART devices. When enabled, they would positively decode 0x3f8 and 0x2f8 (bases) and prevent those from being routed to LPC controller.
If you previously did not have LPC_CLK running for the Nuvoton part in your coreboot build, it explains why util/superiotool did not detect Nuvoton. If you did not do so already, run that tool again. Hopefully you see something on 0x4e now.
SuperIOs typically have another clock input pin (either 24 MHz or 48 MHz) for the baud generator of the UARTs. If you get that Nuvoton detected, and disable SoC UARTs, and still have no serial output, I would trace the source for that clock next.
Regards, Kyösti
On Fri, May 24, 2019 at 5:23 PM Дмитрий Понаморев dponamorev@gmail.com wrote:
Thank for help!
The LPC_CLKOUT1 clock signal appeared but there is no nuvoton chip detected in linux.
Well couple things you need to check in the hardware then:
Probe the LPC FRAME signal or use a logic analyzer to see if there is any LPC activity while you run util/superiotool. Check from Nuvoton datasheet if it requires LPC CLK to be present before its RESET signal is de-asserted. Check if Nuvoton has otherwise a sane power-up sequence (Vcc, Vstb rise-up vs RESET pins).
I could not turn off the SOC UART yet. With my changes, the system does not start well (stops at post code 0x46, 0x47).
Disable coreboot console output to serial port for now. When neither UART is present, it might just be hitting transmit timeout for every single character, making it boot ridiculously slow. If you can boot to OS, you can still read the logs with util/cbmem.
And the most important thing is that the Nuvoton System Clock (48 MHz for the baud generator of the UARTs) is missing.
This may be preventing util/superiotool from detecting the chip. I think I have seen some SIO parts respond to ID queries even without this clock if LPC CLK is present.
How can I change the IDT clock synthesizer (9VRS4420DKLFT) settings in coreboot? Rather, where can I make changes in coreboot to properly configure IDT clock synthesizer (9VRS4420DKLFT)?
Grep the source for smbus_block_write. There is drivers/ck505 and lenovo/x201 that you can use as base for your modifications. Sometimes these IDT datasheets are hard to get and you may need to capture the correct commands from SMBus signals or with utilities from i2c-tools package after booting with OEM firmware.
Kyösti
-
Kyösti Mälkki -
Shreesh Chhabbi -
Дмитрий Понаморев