Thank for help!
The LPC_CLKOUT1 clock signal appeared but there is no nuvoton chip detected in linux.
I could not turn off the SOC UART yet. With my changes, the system does not start well (stops at post code 0x46, 0x47).
/*Disabled SOC UART1 & UART2*/
u32 reg32;
reg32 = pci_read_config32(SOC_LPC_DEV /*(0,1f,0)*/, UART_CONT /*0x80*/);
reg32 = reg32 & (~0x3);
pci_write_config32(SOC_LPC_DEV, UART_CONT, reg32);
And the most important thing is that the Nuvoton System Clock (48 MHz for the baud generator of the UARTs) is missing.
IDT clock synthesizer (9VRS4420DKLFT) is responsible for the formation of this clock. This clock synthesizer provides reference clocks for I/O interfaces, SATA, USB, Gbe and PCI Express.
At the initial moment of time, the clock synthesizer is initialized via the SMB bus (I can see it with an oscilloscope). But no 48 MHz clock for Nuvoton.
Nuvoton System Clock, use the USB_48M_2X contact of 9VRS4420DKLFT, which is normally not used.
How can I change the IDT clock synthesizer (9VRS4420DKLFT) settings in coreboot? Rather, where can I make changes in coreboot to properly configure IDT clock synthesizer (9VRS4420DKLFT)?
Best Regards,
Dmitry Ponamorev