Hello Marc,
in the meantime I debugged my Ubuntu restart problem a little bit further.
The issue seems to be hardware dependant because the Persimmon platform with T56N APU and A55E Hudson works fine and a similar platform (Qseven card) with T40E APU and Hudson A50E does not. I can use nearly the same coreboot build.
Things getting strange in the file .../f14/Proc/Mem/NB/ON/mndcton.c function MemNStitchMemoryON
if ((MemNGetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + q) & 7) == 0) { HERE WE FAIL!!, BFCSBaseAddr0Reg is not zero!!
This leads later to
PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader); HERE ALL ENDS!!!
And here ends all with no memory.
On Persimmon BFCSBaseAddr0Reg is zero so we are getting in the IF branch and things going on.
BOOLEAN MemNStitchMemoryON ( IN OUT MEM_NB_BLOCK *NBPtr ) { UINT32 NxtCSBase; UINT32 CurCSBase; UINT32 CsSize; UINT32 BiggestBank; UINT8 p; UINT8 q; UINT8 BiggestDimm; DIE_STRUCT *MCTPtr; DCT_STRUCT *DCTPtr; MCTPtr = NBPtr->MCTPtr; DCTPtr = NBPtr->DCTPtr;
DCTPtr->Timings.CsEnabled = 0; NxtCSBase = 0; for (p = 0; p < MAX_CS_PER_CHANNEL_ON; p++) { BiggestBank = 0; BiggestDimm = 0; for (q = 0; q < MAX_CS_PER_CHANNEL_ON; q++) { printk(BIOS_DEBUG, "q = %x, Timings.CsPresent = %x, Timings.CsTestFail = %x\n", q, DCTPtr->Timings.CsPresent, DCTPtr->Timings.CsTestFail); //kamod if (((DCTPtr->Timings.CsPresent & ~DCTPtr->Timings.CsTestFail) & ((UINT16)1 << q)) != 0) { printk(BIOS_DEBUG, "1st IF is true \n"); //kamod if ((MemNGetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + q) & 7) == 0) { HERE WE FAIL!!, BFCSBaseAddr0Reg is not zero // (CSEnable|Spare==1)bank is not enabled yet printk(BIOS_DEBUG, "2nd IF is true \n"); //kamod CsSize = MemNGetBitFieldNb (NBPtr, BFCSMask0Reg + (q >> 1)); printk(BIOS_DEBUG, "CsSize = %x \n", CsSize); //kamod if (CsSize != 0) { CsSize += ((UINT32)1 << 19); CsSize &= 0xFFF80000; } if (CsSize > BiggestBank) { BiggestBank = CsSize; BiggestDimm = q; } } } }
if (BiggestBank != 0) { CurCSBase = NxtCSBase; CurCSBase |= ((UINT32)1 << BFCSEnable); NxtCSBase += BiggestBank; if ((BiggestDimm & 1) != 0) { if ((DCTPtr->Timings.DimmMirrorPresent & (1 << (BiggestDimm >> 1))) != 0) { CurCSBase |= ((UINT32)1 << BFOnDimmMirror); } } MemNSetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + BiggestDimm, CurCSBase); DCTPtr->Timings.CsEnabled |= (1 << BiggestDimm); } if ((DCTPtr->Timings.CsTestFail & ((UINT16)1 << p)) != 0) { MemNSetBitFieldNb (NBPtr, (BFCSBaseAddr0Reg + p), (UINT32)1 << BFTestFail); } }
if (NxtCSBase != 0) { DCTPtr->Timings.DctMemSize = NxtCSBase >> 8; // Scale base address from [39:8] to [47:16] NBPtr->MCTPtr->NodeMemSize += NBPtr->DCTPtr->Timings.DctMemSize; NBPtr->MCTPtr->NodeSysLimit = NBPtr->MCTPtr->NodeMemSize - 1; } else { printk(BIOS_DEBUG, "NxtCSBase = %x \n", NxtCSBase); //kamod PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader); HERE ALL ENDS!!! SetMemError (AGESA_FATAL, MCTPtr); }
return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); }
What I have done was to change the way Ubuntu restarts. If I set reboot=acpi restart works.
Thanks
Wolfgang
-----Ursprüngliche Nachricht----- Von: coreboot-bounces+wmkamp=datakamp.de@coreboot.org [mailto:coreboot-bounces+wmkamp=datakamp.de@coreboot.org] Im Auftrag von Wolfgang Kamp - datakamp Gesendet: Mittwoch, 25. Januar 2012 17:24 An: coreboot@coreboot.org Betreff: Re: [coreboot] Change in coreboot[master]: Inagua: Synchronize AMD/inagua mainboard.
Hello Marc,
my debugging shows that SPD reading is ok after Warmstart. This can not be the problem. The error check reports 7 errors when system hangs. Is there a problem with cache as RAM? Is the buffer of SPD data corrupt? I don't know what code here really does. Have you an idea what I can do next?
mmflow.c
//---------------------------------------------------------------- // Check for errors and return //---------------------------------------------------------------- AGESA_TESTPOINT (TpProcMemEnd, &MemPtr->StdHeader); for (Die = 0; Die < DieCount; Die++) { if (NBPtr[Die].MCTPtr->ErrCode > Retval) { Retval = NBPtr[Die].MCTPtr->ErrCode; } } printk(BIOS_DEBUG, "TpProcMemEnd Retval = 0x%x \n", Retval); return Retval; }
Regards,
Wolfgang
-----Ursprüngliche Nachricht----- Von: Marc Jones [mailto:marcj303@gmail.com] Gesendet: Dienstag, 24. Januar 2012 19:15 An: Wolfgang Kamp - datakamp Cc: coreboot@coreboot.org Betreff: Re: [coreboot] Change in coreboot[master]: Inagua: Synchronize AMD/inagua mainboard.
On Tue, Jan 24, 2012 at 5:38 AM, Wolfgang Kamp - datakamp wmkamp@datakamp.de wrote:
The sb800 is accessible, it is fetching rom and initializing devices that it sees:
sb800_enable() PCI: 00:11.0 [1002/4390] enabled sb800_enable() PCI: 00:12.0 [1002/4397] ops PCI: 00:12.0 [1002/4397] enabled sb800_enable() PCI: Static device PCI: 00:12.1 not found, disabling it. sb800_enable() PCI: 00:12.2 [1002/4396] ops PCI: 00:12.2 [1002/4396] enabled sb800_enable() PCI: 00:13.0 [1002/4397] ops PCI: 00:13.0 [1002/4397] enabled sb800_enable() PCI: Static device PCI: 00:13.1 not found, disabling it. sb800_enable() PCI: 00:13.2 [1002/4396] ops PCI: 00:13.2 [1002/4396] enabled sb800_enable() sm_init(). . PCI: 00:14.0 [1002/4385] enabled sb800_enable() PCI: Static device PCI: 00:14.1 not found, disabling it. sb800_enable() hda enabled PCI: 00:14.2 [1002/4383] ops PCI: 00:14.2 [1002/4383] enabled
!4.0 is the smbus device, so that is enabled. I think that you need to see what in the spd read fails. Also, see if you can read it earlier in the init. There could be a different device setting that causes the problem. Check that te SMbus enable is set as expected. Check that the PM registers that set the iobase are accessible.
Marc
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Wolfgang Kamp - datakamp