答复: 答复: Cache On and ECC clear

[YhLu]

Eric,

It seems it's all right in mtrr setting. Except 0x201 and 0x203 setting in
earlymtrr.inc should set 0xff for msr.hi intead of 0xf

Before mtrr processing for clearing

Normal mode
0000=0x0000000000000006
0001=0x000000fffff00800
0002=0x00000000fffe8006
0003=0x000000fffffe8800

Fallback mode
0000=0x0000000000000006
0001=0x000000fffff00800
0002=0x00000000fffd0006
0003=0x000000fffffe8800

after mtrr processing for clearing,

Normal mode
0000=0x0000000000000001
0001=0x000000fffff00800
0002=0x00000000fffe8006
0003=0x000000fffffe8800

Fallback mode
0000=0x0000000000000001
0001=0x000000fffff00800
0002=0x00000000fffd0006
0003=0x000000fffffe8800

-----邮件原件-----
发件人: [e-mail] [mailto:[e-mail]] 
发送时间: 2004年3月29日 17:18
收件人: YhLu
抄送: ron minnich; Li-Ta Lo; LinuxBIOS
主题: Re: 答复: Cache On and ECC clear

YhLu  writes:
> Eric,
>
> I verified the exchange the cpufixup after the cache_on...mtrr_check in

cpu.
> c for S2882.
>
> Found one interesting thing
> In fallback mode, it does not pause after "Clearing LinuxBIOS memory "
>
> and "Copying LinuxBIOS to ram".
> 2. In normal node, it does pause after the "Clearing" and "Copying" ( 5s

and
> 4s).
>
> What could cause that?

So we are talking about quantities all within the first 1MB of ram...

This sounds like something is goofy with the mtrrs.  At least that
is the usual suspect when something is running slowly.

Eric

答复: 答复: Cache On and ECC clear

YhLu  writes:
> Eric,
>
> It seems it's all right in mtrr setting. Except 0x201 and 0x203 setting in
> earlymtrr.inc should set 0xff for msr.hi intead of 0xf
>
> Before mtrr processing for clearing

Hmm.  Assuming 0000 == 0x200, 0001 == 0x201 etc.  So
you have to base and mask pairs.
> Normal mode
> 0000=0x0000000000000006
> 0001=0x000000fffff00800
> 0002=0x00000000fffe8006

This is a base address 4GB - 96K
> 0003=0x000000fffffe8800

This is a size and it tries to be 96K.
  It is actually something like 32K.
> Fallback mode
> 0000=0x0000000000000006
> 0001=0x000000fffff00800
> 0002=0x00000000fffd0006

This is a base address 4GB - 160K
> 0003=0x000000fffffe8800

This is a size aand it tries to be 96K.
  It is actually something like 32K.

So somehow you got at non power of 2 size into XIP_ROM_SIZE.  So much less
of your code is cached than you would expect.  So instruction fetches take
a very long time.  And loops are slow.

The comments from my HDAMA Config.lb 
## XIP_ROM_SIZE must be a power of 2.
## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE

It looks like these needs to be enforced, somehow so build time mistakes
don't happen. Perhaps:
#if ((XIP_ROM_BASE % XIP_ROM_SIZE) != 0) || ((XIP_ROM_SIZE & (XIP_ROM_SIZE - 1)) != 0)
#error XIP_ROM_SIZE must be a power of 2 and XIP_ROM_BASE must be a multiple of it
#endif

Eric