Patch set updated for coreboot: 42a0258 Add support for RAM-less multi-processor init

[Kyösti Mälkki]

Kyösti Mälkki ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/454

-gerrit

commit 42a025844124f7dcb4d6de8eb1f99cd2fd8f71f4
Author: Kyösti Mälkki 
Date:   Tue Feb 14 10:39:17 2012 +0200

Add support for RAM-less multi-processor init

For a hyper-threading processor, enabling cache requires that both the
    BSP and AP CPU clear CR0.CD (Cache Disable) bit. For a Cache-As-Ram
    implementation, partial multi-processor initialisation precedes
    raminit and AP CPUs' 16bit entry must be run from ROM.

The AP CPU can only start execute real-mode code at a 4kB aligned
    address below 1MB. The protected mode entry code for AP is identical
    with the BSP code, which is already located at the top of bootblock.
    This patch takes the simplest approach and aligns the bootblock
    16 bit entry at highest possible 4kB boundary below 1MB.

The symbol ap_sipi_vector is tested to match CONFIG_AP_SIPI_VECTOR
    used by the CAR code in romstage. Adress is not expected to ever
    change, but if it does, link will fail.

Change-Id: I82e4edbf208c9ba863f51a64e50cd92871c528ef
    Signed-off-by: Kyösti Mälkki 
---
 src/arch/x86/init/ldscript_failover.lb |   13 +++++++++----
 src/cpu/Kconfig                        |    6 ++++++
 2 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/src/arch/x86/init/ldscript_failover.lb b/src/arch/x86/init/ldscript_failover.lb
index 83e5eb3..61c3d2a 100644
--- a/src/arch/x86/init/ldscript_failover.lb
+++ b/src/arch/x86/init/ldscript_failover.lb
@@ -29,17 +29,18 @@ MEMORY {
 TARGET(binary)
 SECTIONS
 {
-	/* Align .rom to next 4 byte boundary so no pad byte appears
-	 * between _rom and _start.
+	/* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs
+	 * with Startup IPI message without RAM.
     */
    .bogus ROMLOC_MIN : {
-		. = ALIGN(4);
+		. = ALIGN(4096);
    	ROMLOC = .;
    } >rom = 0xff

/* This section might be better named .setup */
    .rom ROMLOC : {
    	_rom = .;
+		ap_sipi_vector = .;
    	*(.rom.text);
    	*(.rom.data);
    	*(.rom.data.*);
@@ -51,7 +52,11 @@ SECTIONS
     * may cause the total size of a section to change when the start
     * address gets applied.
     */
-	ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16);
+	ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - 4096;
+
+	/* Post-check proper SIPI vector. */
+	_bogus = ASSERT(((ap_sipi_vector & 0x0fff) == 0x0), "Bad SIPI vector alignment");
+	_bogus = ASSERT((ap_sipi_vector == CONFIG_AP_SIPI_VECTOR), "Address mismatch on AP_SIPI_VECTOR");

/DISCARD/ : {
    	*(.comment)
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig
index d576873..601f443 100644
--- a/src/cpu/Kconfig
+++ b/src/cpu/Kconfig
@@ -38,6 +38,12 @@ config SMP
      This option is used to enable certain functions to make coreboot
      work correctly on symmetric multi processor (SMP) systems.

+config AP_SIPI_VECTOR
+	hex
+	default 0xfffff000
+	help
+	  This must equal address of ap_sipi_vector from bootblock build.
+	  	  
 config	MMX
    bool
    help