Author: rminnich Date: 2007-06-15 17:33:50 +0200 (Fri, 15 Jun 2007) New Revision: 354
Added: LinuxBIOSv3/include/post_code.h LinuxBIOSv3/mainboard/amd/norwich/initram.c Modified: LinuxBIOSv3/mainboard/amd/norwich/Kconfig LinuxBIOSv3/mainboard/amd/norwich/Makefile LinuxBIOSv3/southbridge/amd/cs5536/cs5536.h Log: OK, this includes all the mods that should give you a compileable initram. Gets errors as we don't have ram support yet, working that now.
Signed-off-by: Ronald G. Minnich rminnich@gmail.com Acked-by: Stefan Reinauer stepan@coresystems.de
Added: LinuxBIOSv3/include/post_code.h =================================================================== --- LinuxBIOSv3/include/post_code.h (rev 0) +++ LinuxBIOSv3/include/post_code.h 2007-06-15 15:33:50 UTC (rev 354) @@ -0,0 +1,21 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Ronald G. Minnich rminnich@gmail.com + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define POST_START_OF_MAIN (0x01)
Modified: LinuxBIOSv3/mainboard/amd/norwich/Kconfig =================================================================== --- LinuxBIOSv3/mainboard/amd/norwich/Kconfig 2007-06-14 20:00:58 UTC (rev 353) +++ LinuxBIOSv3/mainboard/amd/norwich/Kconfig 2007-06-15 15:33:50 UTC (rev 354) @@ -40,3 +40,6 @@ help Mainboard specific PCI subsystem device ID.
+ + +
Modified: LinuxBIOSv3/mainboard/amd/norwich/Makefile =================================================================== --- LinuxBIOSv3/mainboard/amd/norwich/Makefile 2007-06-14 20:00:58 UTC (rev 353) +++ LinuxBIOSv3/mainboard/amd/norwich/Makefile 2007-06-15 15:33:50 UTC (rev 354) @@ -19,31 +19,24 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-# -# VPD or SIP ROM or ... how does NVIDIA call it? -# Some space to cope with dirty southbridge tricks. -# Do we want to put our own stuff there, too? -# - $(obj)/linuxbios.vpd: $(Q)printf " BUILD DUMMY VPD\n" $(Q)dd if=/dev/zero of=$(obj)/linuxbios.vpd bs=256 count=1 $(SILENT)
-# -# This is going to be the init RAM code. -# -# The initram file is always uncompressed. It belongs into the mainboard -# directory and is built from what was auto.c in v2. -# -# It should probably be renamed, as it does more than initram. -# auto.c is a bit too meaningless though. -# - -$(obj)/linuxbios.initram: $(obj)/stage0.init $(obj)/stage0.o $(obj)/mainboard/$(MAINBOARDDIR)/initram.o +INITRAM_OBJ=$(obj)/stage0.init $(obj)/stage0.o $(obj)/mainboard/$(MAINBOARDDIR)/initram.o \ + $(obj)/northbridge/amd/geodelx/raminit.o \ + $(obj)/southbridge/amd/cs5536/smbus_initram.o \ + $(obj)/southbridge/amd/cs5536/cs5536_early_setup.o\ + $(obj)/arch/x86/geodelx.o +$(obj)/linuxbios.initram: $(INITRAM_OBJ) $(Q)# initram links against stage0 $(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n" $(Q)$(LD) -R $(obj)/stage0.o -Ttext 0x80000 \ $(obj)/mainboard/$(MAINBOARDDIR)/initram.o \ + $(obj)/northbridge/amd/geodelx/raminit.o \ + $(obj)/southbridge/amd/cs5536/smbus_initram.o \ + $(obj)/southbridge/amd/cs5536/cs5536_early_setup.o\ + $(obj)/arch/x86/geodelx.o\ --entry=main -o $(obj)/linuxbios.initram.o $(Q)printf " OBJCOPY $(subst $(shell pwd)/,,$(@))\n" $(Q)$(OBJCOPY) -O binary $(obj)/linuxbios.initram.o \ @@ -76,7 +69,7 @@
STAGE2_MAINBOARD_OBJ = mainboard.o vga.o
-STAGE2_CHIPSET_OBJ = +STAGE2_CHIPSET_OBJ =
$(obj)/mainboard/$(MAINBOARDDIR)/%.o: $(src)/mainboard/$(MAINBOARDDIR)/%.c $(Q)mkdir -p $(obj)/mainboard/$(MAINBOARDDIR)
Added: LinuxBIOSv3/mainboard/amd/norwich/initram.c =================================================================== --- LinuxBIOSv3/mainboard/amd/norwich/initram.c (rev 0) +++ LinuxBIOSv3/mainboard/amd/norwich/initram.c 2007-06-15 15:33:50 UTC (rev 354) @@ -0,0 +1,93 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <post_code.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <msr.h> +#include <amd_geodelx.h> +#include <southbridge/amd/cs5536/cs5536.h> +#include <northbridge/amd/geodelx/raminit.h> + +#define MANUALCONF 0 /* Do automatic strapped PLL config */ +#define PLLMSRHI 0x00001490 /* manual settings for the PLL */ +#define PLLMSRLO 0x02000030 +#define DIMM0 ((u8) 0xA0) +#define DIMM1 ((u8) 0xA2) + + +/** + * Place holder in case we ever need it. Since this file is a + * template for other motherboards, we want this here and we want the + * call in the right place. + */ + +static void mb_gpio_init(void) +{ + /* Early mainboard specific GPIO setup */ +} + +/** + * main for initram for the amd norwich. It might seem that you + * could somehow do these functions in, e.g., the cpu code, but the + * order of operations and what those operations are is VERY strongly + * mainboard dependent. It's best to leave it in the mainboard code. + */ +int main(void) +{ + u8 smb_devices[] = { + DIMM0, DIMM1 + }; + + post_code(POST_START_OF_MAIN); + + system_preinit(); + geodelx_msr_init(); + + cs5536_early_setup(); + + /* NOTE: must do this AFTER the early_setup! + * it is counting on some early MSR setup + * for cs5536. + */ + /* We do this early for debug. + * real setup should done in chipset init via config.lb + */ + cs5536_setup_onchipuart(); + mb_gpio_init(); + uart_init(); + console_init(); + + pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO); + + cpu_reg_init(0, DIMM0, DIMM1); + + sdram_set_registers(); + sdram_set_spd_registers(DIMM0, DIMM1); + sdram_enable(DIMM0, DIMM1); + /* Check low memory */ + /*ram_check(0x00000000, 640*1024); */ + + return 0; +}
Modified: LinuxBIOSv3/southbridge/amd/cs5536/cs5536.h =================================================================== --- LinuxBIOSv3/southbridge/amd/cs5536/cs5536.h 2007-06-14 20:00:58 UTC (rev 353) +++ LinuxBIOSv3/southbridge/amd/cs5536/cs5536.h 2007-06-15 15:33:50 UTC (rev 354) @@ -441,4 +441,17 @@ #define FLASH_IO_128B 0x0000FF80 #define FLASH_IO_256B 0x0000FF00
+/* function prototypes */ +void cs5536_setup_extmsr(void); +void cs5536_setup_idsel(void); +void cs5536_usb_swapsif(void); +void cs5536_setup_iobase(void); +void cs5536_setup_power_button(void); +void cs5536_setup_smbus_gpio(void); +void cs5536_disable_internal_uart(void); +void cs5536_setup_cis_mode(void); +void cs5536_setup_onchipuart(void); +void cs5536_early_setup(void); + + #endif /* SOUTHBRIDGE_AMD_CS5536_CS5536_H */
-
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