Author: mjones Date: 2009-03-25 16:47:58 +0100 (Wed, 25 Mar 2009) New Revision: 4028
Added: trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000096.h trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_0100009f.h Log: The latest ucode patches for Family 10h:
9fh for RB/BL/DA Rev C; 96h for DR Rev B.
Signed-off-by: Zeng Bao zheng.bao@amd.com Acked-by: Marc Jones marcj303@gmail.com
Added: trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000096.h =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000096.h (rev 0) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000096.h 2009-03-25 15:47:58 UTC (rev 4028) @@ -0,0 +1,163 @@ +/* + ============================================================ + (c) Advanced Micro Devices, Inc., 2004-2009 + + The enclosed microcode is intended to be used with AMD + Microprocessors. You may copy, view and install the + enclosed microcode only for development and deployment of + firmware, BIOS, or operating system code for computer + systems that contain AMD processors. You are not + authorized to use the enclosed microcode for any other + purpose. + + THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR + IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO + WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, + TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES + ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + AMD does not assume any responsibility for any errors which + may appear in this microcode or any other related + information provided to you by AMD, or result from use of + this microcode. AMD is not obligated to furnish, support, + or make any further information, software, technical + information, know-how, or show-how available related to this + microcode. + + The microcode is provided with "RESTRICTED RIGHTS." Use, + duplication, or disclosure by the U.S. Government is subject + to the restrictions as set forth in FAR 52.227-14 and + DFAR252.227-7013, et seq., or its successor. Use of the + microcode by the U.S. Government constitutes + acknowledgement of AMD's proprietary rights in them. + ============================================================ +*/ + +0x08, 0x20, 0x05, 0x11, 0x96, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x00, +0x85, 0xd4, 0x2d, 0x6d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x20, 0x10, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0x70, 0x09, 0x00, 0x00, +0x49, 0x01, 0x00, 0x00, 0x8b, 0x01, 0x00, 0x00, 0xc1, 0x08, 0x00, 0x00, +0xff, 0xff, 0xff, 0xff, 0x56, 0x0f, 0x00, 0x00, 0x9e, 0x0b, 0x00, 0x00, +0x70, 0x0c, 0x00, 0x00, 0x2a, 0xff, 0xff, 0x29, 0xc3, 0x5f, 0xd0, 0xc1, +0xbd, 0xff, 0xff, 0xb3, 0x0f, 0xff, 0x7e, 0xfd, 0xf6, 0x1f, 0xf8, 0x57, +0x3c, 0xbc, 0x63, 0x2d, 0x80, 0x96, 0xd6, 0x00, 0xaa, 0xff, 0xef, 0xaf, +0xe0, 0xd1, 0x9f, 0x15, 0x57, 0xef, 0xff, 0xff, 0xea, 0x87, 0x7f, 0xbf, +0x03, 0xfa, 0x0f, 0xfc, 0xfc, 0x1f, 0xbe, 0xf5, 0x00, 0xe0, 0x4a, 0x4b, +0x7f, 0xc8, 0xff, 0xf7, 0xb4, 0xf8, 0xf0, 0x2f, 0xff, 0x1f, 0xc5, 0xfe, +0xc0, 0xcf, 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Added: trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_0100009f.h =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_0100009f.h (rev 0) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_0100009f.h 2009-03-25 15:47:58 UTC (rev 4028) @@ -0,0 +1,163 @@ +/* + ============================================================ + (c) Advanced Micro Devices, Inc., 2004-2009 + + The enclosed microcode is intended to be used with AMD + Microprocessors. You may copy, view and install the + enclosed microcode only for development and deployment of + firmware, BIOS, or operating system code for computer + systems that contain AMD processors. You are not + authorized to use the enclosed microcode for any other + purpose. + + THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR + IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO + WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, + TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES + ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + AMD does not assume any responsibility for any errors which + may appear in this microcode or any other related + information provided to you by AMD, or result from use of + this microcode. AMD is not obligated to furnish, support, + or make any further information, software, technical + information, know-how, or show-how available related to this + microcode. + + The microcode is provided with "RESTRICTED RIGHTS." Use, + duplication, or disclosure by the U.S. Government is subject + to the restrictions as set forth in FAR 52.227-14 and + DFAR252.227-7013, et seq., or its successor. Use of the + microcode by the U.S. Government constitutes + acknowledgement of AMD's proprietary rights in them. + ============================================================ +*/ + +0x08, 0x20, 0x17, 0x12, 0x9f, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x00, +0x8b, 0xb7, 0x4e, 0xd0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x62, 0x10, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0x9a, 0x0b, 0x00, 0x00, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0x6f, 0x58, 0x39, 0x00, 0x81, 0x3f, 0xa0, 0xd7, +0x04, 0x00, 0xfc, 0xb7, 0x0f, 0xff, 0x58, 0xf7, 0x72, 0xc0, 0xff, 0x6f, +0x3c, 0xfc, 0x03, 0xfc, 0xc0, 0x18, 0xd5, 0x00, 0x80, 0xff, 0x66, 0x3c, +0xeb, 0xc0, 0x9f, 0xd9, 0x4d, 0xee, 0xf8, 0xff, 0xff, 0x83, 0x7f, 0xa6, +0x07, 0xe8, 0xff, 0xff, 0xe8, 0x1f, 0xbe, 0xb5, 0x00, 0x60, 0x2f, 0x6a, +0x1f, 0xc0, 0x7f, 0xe0, 0xe0, 0xdf, 0xf0, 0x0f, 0x7f, 0x00, 0xff, 0x81, +0x80, 0x7f, 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svn＠coreboot.org