[PATCH] Set the register based on the ROMSIZE

[Bao, Zheng]

Set the register based on the ROMSIZE.

Signed-off-by: Zheng Bao

Index: src/southbridge/amd/sb600/Kconfig
===================================================================
--- src/southbridge/amd/sb600/Kconfig	(revision 6159)
+++ src/southbridge/amd/sb600/Kconfig	(working copy)
@@ -23,6 +23,11 @@
    select HAVE_USBDEBUG
    select TINY_BOOTBLOCK

+config BOOTBLOCK_SOUTHBRIDGE_INIT
+	string
+	default "southbridge/amd/sb600/bootblock.c"
+	depends on SOUTHBRIDGE_AMD_SB600
+
 config EHCI_BAR
    hex
    default 0xfef00000 if SOUTHBRIDGE_AMD_SB600
Index: src/southbridge/amd/sb600/bootblock.c
===================================================================
--- src/southbridge/amd/sb600/bootblock.c	(revision 6159)
+++ src/southbridge/amd/sb600/bootblock.c	(working copy)
@@ -59,7 +59,15 @@
     * 0xffe0(0000): 2MB
     * 0xffc0(0000): 4MB
     */
+	#if CONFIG_COREBOOT_ROMSIZE_KB_512 ||
CONFIG_COREBOOT_ROMSIZE_KB_256 || CONFIG_COREBOOT_ROMSIZE_KB_128
+	pci_write_config16(dev, 0x6c, 0xfff8); /* 512KB */
+	#elif CONFIG_COREBOOT_ROMSIZE_KB_1024
+	pci_write_config16(dev, 0x6c, 0xfff0); /* 1 MB */
+	#elif CONFIG_COREBOOT_ROMSIZE_KB_2048
+	pci_write_config16(dev, 0x6c, 0xffe0); /* 2 MB */
+	#elif CONFIG_COREBOOT_ROMSIZE_KB_4096
    pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */
+	#endif
    /* Enable LPC ROM range end at 0xffff(ffff). */
    pci_write_config16(dev, 0x6e, 0xffff);
 }
Index: src/southbridge/amd/sb700/Kconfig
===================================================================
--- src/southbridge/amd/sb700/Kconfig	(revision 6159)
+++ src/southbridge/amd/sb700/Kconfig	(working copy)
@@ -23,6 +23,11 @@
    select HAVE_USBDEBUG
    select TINY_BOOTBLOCK

+config BOOTBLOCK_SOUTHBRIDGE_INIT
+	string
+	default "southbridge/amd/sb700/bootblock.c"
+	depends on SOUTHBRIDGE_AMD_SB700
+
 config SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT
    bool
    default n
Index: src/southbridge/amd/sb700/bootblock.c
===================================================================
--- src/southbridge/amd/sb700/bootblock.c	(revision 6159)
+++ src/southbridge/amd/sb700/bootblock.c	(working copy)
@@ -28,7 +28,7 @@
  * Hardware should enable LPC ROM by pin straps. This function does not
  * handle the theoretically possible PCI ROM, FWH, or SPI ROM
configurations.
  *
- * The SB700 power-on default is to map 256K ROM space.
+ * The SB700 power-on default is to map 512K ROM space.
  *
  * Details: AMD SB700/710/750 BIOS Developer's Guide (BDG), Rev. 1.00,
  *          PN 43366_sb7xx_bdg_pub_1.00, June 2009, section 3.1, page
14.
@@ -57,8 +57,18 @@
     * Enable LPC ROM range start at:
     * 0xfff8(0000): 512KB
     * 0xfff0(0000): 1MB
+	 * 0xffe0(0000): 2MB
+	 * 0xffc0(0000): 4MB
     */
+	#if CONFIG_COREBOOT_ROMSIZE_KB_512 ||
CONFIG_COREBOOT_ROMSIZE_KB_256 || CONFIG_COREBOOT_ROMSIZE_KB_128
+	pci_write_config16(dev, 0x6c, 0xfff8); /* 512KB */
+	#elif CONFIG_COREBOOT_ROMSIZE_KB_1024
    pci_write_config16(dev, 0x6c, 0xfff0); /* 1 MB */
+	#elif CONFIG_COREBOOT_ROMSIZE_KB_2048
+	pci_write_config16(dev, 0x6c, 0xffe0); /* 2 MB */
+	#elif CONFIG_COREBOOT_ROMSIZE_KB_4096
+	pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */
+	#endif
    /* Enable LPC ROM range end at 0xffff(ffff). */
    pci_write_config16(dev, 0x6e, 0xffff);
 }

[Patrick Georgi]

Am 10.12.2010 13:02, schrieb Bao, Zheng:
> Set the register based on the ROMSIZE.
> @@ -57,8 +57,18 @@
>     * Enable LPC ROM range start at:
>     * 0xfff8(0000): 512KB
>     * 0xfff0(0000): 1MB
> * 0xffe0(0000): 2MB
> * 0xffc0(0000): 4MB
> */
> #if CONFIG_COREBOOT_ROMSIZE_KB_512 ||
>
> CONFIG_COREBOOT_ROMSIZE_KB_256 || CONFIG_COREBOOT_ROMSIZE_KB_128
> pci_write_config16(dev, 0x6c, 0xfff8); /* 512KB */
> #elif CONFIG_COREBOOT_ROMSIZE_KB_1024
> pci_write_config16(dev, 0x6c, 0xfff0); /* 1 MB */
> #elif CONFIG_COREBOOT_ROMSIZE_KB_2048
> pci_write_config16(dev, 0x6c, 0xffe0); /* 2 MB */
> #elif CONFIG_COREBOOT_ROMSIZE_KB_4096
> pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */
> #endif

How about
pci_write_config16(dev, 0x6c,
0x10000-(max(512,CONFIG_COREBOOT_ROMSIZE_KB)>>6));
instead?

Patrick

[Bao, Zheng]

I am not sure.
I think we need to leave the workload to compiler, instead of to the
machine running the coreboot and to the people.

Zheng
> -----Original Message-----
> From: [e-mail]

[mailto:[e-mail]]
> On Behalf Of Patrick Georgi
> Sent: Friday, December 10, 2010 8:10 PM
> To: [e-mail]
> Subject: Re: [coreboot] [PATCH] Set the register based on the ROMSIZE
>
> Am 10.12.2010 13:02, schrieb Bao, Zheng:
> > Set the register based on the ROMSIZE.
> > @@ -57,8 +57,18 @@
> >     * Enable LPC ROM range start at:
> >     * 0xfff8(0000): 512KB
> >     * 0xfff0(0000): 1MB
> > * 0xffe0(0000): 2MB
> > * 0xffc0(0000): 4MB
> > */
> > #if CONFIG_COREBOOT_ROMSIZE_KB_512 ||
> >
> > CONFIG_COREBOOT_ROMSIZE_KB_256 || CONFIG_COREBOOT_ROMSIZE_KB_128
> > pci_write_config16(dev, 0x6c, 0xfff8); /* 512KB */
> > #elif CONFIG_COREBOOT_ROMSIZE_KB_1024
> > pci_write_config16(dev, 0x6c, 0xfff0); /* 1 MB */
> > #elif CONFIG_COREBOOT_ROMSIZE_KB_2048
> > pci_write_config16(dev, 0x6c, 0xffe0); /* 2 MB */
> > #elif CONFIG_COREBOOT_ROMSIZE_KB_4096
> > pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */
> > #endif
>
> How about
> pci_write_config16(dev, 0x6c,
> 0x10000-(max(512,CONFIG_COREBOOT_ROMSIZE_KB)>>6));
> instead?
>
> Patrick

[Patrick Georgi]

Am 10.12.2010 13:29, schrieb Bao, Zheng:
> > How about
> > pci_write_config16(dev, 0x6c,
> > 0x10000-(max(512,CONFIG_COREBOOT_ROMSIZE_KB)>>6));
> > instead?
>
> I am not sure.
> I think we need to leave the workload to compiler, instead of to the
> machine running the coreboot and to the people.

Hmm.. The main problem might be that romcc is probably not capable of
resolving max(a,b) at compile time. Other than that, this is a rather
primitive compile time optimization.

Other than that, it's more a style question: lots of #ifdef/#elif
statements or a comparably opaque calculation as in the proposal?

Patrick

[Bao, Zheng]

My opinion is,
Use the calculation, and put the truth table in the comment, if it has
nothing to do with ROMCC.

Zheng
> -----Original Message-----
> From: coreboot-bounces+zheng.bao=[e-mail]

[mailto:coreboot-
> bounces+zheng.bao=[e-mail]] On Behalf Of Patrick Georgi
> Sent: Friday, December 10, 2010 8:58 PM
> To: [e-mail]
> Subject: Re: [coreboot] [PATCH] Set the register based on the ROMSIZE
>
> Am 10.12.2010 13:29, schrieb Bao, Zheng:
> > > How about
> > > pci_write_config16(dev, 0x6c,
> > > 0x10000-(max(512,CONFIG_COREBOOT_ROMSIZE_KB)>>6));
> > > instead?
> >
> > I am not sure.
> > I think we need to leave the workload to compiler, instead of to the
> > machine running the coreboot and to the people.
>
> Hmm.. The main problem might be that romcc is probably not capable of
> resolving max(a,b) at compile time. Other than that, this is a rather
> primitive compile time optimization.
>
> Other than that, it's more a style question: lots of #ifdef/#elif
> statements or a comparably opaque calculation as in the proposal?
>
> Patrick

[Scott Duplichan]

> @@ -57,8 +57,18 @@
>     * Enable LPC ROM range start at:
>     * 0xfff8(0000): 512KB
>     * 0xfff0(0000): 1MB
> * 0xffe0(0000): 2MB
> * 0xffc0(0000): 4MB
> */
> #if CONFIG_COREBOOT_ROMSIZE_KB_512 ||
>
> CONFIG_COREBOOT_ROMSIZE_KB_256 || CONFIG_COREBOOT_ROMSIZE_KB_128
> pci_write_config16(dev, 0x6c, 0xfff8); /* 512KB */
> #elif CONFIG_COREBOOT_ROMSIZE_KB_1024
> pci_write_config16(dev, 0x6c, 0xfff0); /* 1 MB */
> #elif CONFIG_COREBOOT_ROMSIZE_KB_2048
> pci_write_config16(dev, 0x6c, 0xffe0); /* 2 MB */
> #elif CONFIG_COREBOOT_ROMSIZE_KB_4096
> pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */
> #endif

]
]How about
]pci_write_config16(dev, 0x6c,
]0x10000-(max(512,CONFIG_COREBOOT_ROMSIZE_KB)>>6));
]instead?
]
]Patrick

Why not... 
pci_write_config16(dev, 0x6c,0x10000-(CONFIG_COREBOOT_ROMSIZE_KB>>6));
In other words, why apply special treatment to sizes < 512KB?
In any case, I think most readers of C code would find one of
these methods easier to follow than the preprocessor method.

Thanks,
Scott

[Peter Stuge]

Patrick Georgi wrote:
> > Set the register based on the ROMSIZE.

..
> How about
> pci_write_config16(dev, 0x6c,
> 0x10000-(max(512,CONFIG_COREBOOT_ROMSIZE_KB)>>6));
> instead?

I have a greater problem with this;

It assumes that one image will always go into one and the same size
of flash chip.

We can not support growing or shrinking of CBFS if we would like to,
and hotswapping flash chips with larger size does not work.

I would personally prefer using the largest possible value on all
chipsets.

//Peter

[Scott Duplichan]

Peter Stuge wrote:

]I have a greater problem with this;
]
]It assumes that one image will always go into one and the same size
]of flash chip.

I think I understand your concern. It is convenient to be able to 
use a bigger chip to test a smaller image. But limiting the decode
size will only block access to the usused portion of the chip, correct?

]We can not support growing or shrinking of CBFS if we would like to,
]and hotswapping flash chips with larger size does not work.

When hotswapping, shouldn't the flashing software set this register?

]I would personally prefer using the largest possible value on all
]chipsets.

Despite my comments above, I agree with this. Flashing software is 
likely going to expand the decode to 16MB in order to run a generic
chip detection algorithm, so it isn't safe to let coreboot or OS
use address in that range for MMIO. As long as this area is reserved,
why not just set the decode range for the whole area.

Thanks,
Scott

]
]//Peter

[Stefan Reinauer]

* Scott Duplichan  [101210 18:13]:
> Peter Stuge wrote:
>
> ]I have a greater problem with this;
> ]
> ]It assumes that one image will always go into one and the same size
> ]of flash chip.
>
> I think I understand your concern. It is convenient to be able to 
> use a bigger chip to test a smaller image. But limiting the decode
> size will only block access to the usused portion of the chip, correct?

One of the original design ideas of CBFS (or LAR in v3) was that we can
build a single image, with, say 256KB, and resize that same image later
on in case someone wants to put in fallback/normal, a linux kernel
payload or stuff like that.

Stefan

[PATCH] Set the register based on the ROMSIZE (Patch is updated)

[Bao, Zheng]

Set the ROMSIZE as 4MB.

Signed-off-by: Zheng Bao

Index: src/southbridge/amd/sb600/Kconfig
===================================================================
--- src/southbridge/amd/sb600/Kconfig	(revision 6169)
+++ src/southbridge/amd/sb600/Kconfig	(working copy)
@@ -23,6 +23,11 @@
    select HAVE_USBDEBUG
    select TINY_BOOTBLOCK

+config BOOTBLOCK_SOUTHBRIDGE_INIT
+	string
+	default "southbridge/amd/sb600/bootblock.c"
+	depends on SOUTHBRIDGE_AMD_SB600
+
 config EHCI_BAR
    hex
    default 0xfef00000 if SOUTHBRIDGE_AMD_SB600
Index: src/southbridge/amd/sb700/Kconfig
===================================================================
--- src/southbridge/amd/sb700/Kconfig	(revision 6169)
+++ src/southbridge/amd/sb700/Kconfig	(working copy)
@@ -23,6 +23,11 @@
    select HAVE_USBDEBUG
    select TINY_BOOTBLOCK

+config BOOTBLOCK_SOUTHBRIDGE_INIT
+	string
+	default "southbridge/amd/sb700/bootblock.c"
+	depends on SOUTHBRIDGE_AMD_SB700
+
 config SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT
    bool
    default n
Index: src/southbridge/amd/sb700/bootblock.c
===================================================================
--- src/southbridge/amd/sb700/bootblock.c	(revision 6169)
+++ src/southbridge/amd/sb700/bootblock.c	(working copy)
@@ -23,12 +23,12 @@
 #include <device/pci_ids.h>

/*
- * Enable 1MB (LPC) ROM access at 0xFFF00000 - 0xFFFFFFFF.
+ * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
  *
  * Hardware should enable LPC ROM by pin straps. This function does not
  * handle the theoretically possible PCI ROM, FWH, or SPI ROM
configurations.
  *
- * The SB700 power-on default is to map 256K ROM space.
+ * The SB700 power-on default is to map 512K ROM space.
  *
  * Details: AMD SB700/710/750 BIOS Developer's Guide (BDG), Rev. 1.00,
  *          PN 43366_sb7xx_bdg_pub_1.00, June 2009, section 3.1, page
14.
@@ -39,7 +39,7 @@
    device_t dev;

dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI,
-				PCI_DEVICE_ID_ATI_SB700_LPC), 0);
+				       PCI_DEVICE_ID_ATI_SB700_LPC), 0);

/* Decode variable LPC ROM address ranges 1 and 2. */
    reg8 = pci_read_config8(dev, 0x48);
@@ -57,8 +57,10 @@
     * Enable LPC ROM range start at:
     * 0xfff8(0000): 512KB
     * 0xfff0(0000): 1MB
+	 * 0xffe0(0000): 2MB
+	 * 0xffc0(0000): 4MB
     */
-	pci_write_config16(dev, 0x6c, 0xfff0); /* 1 MB */
+	pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */
    /* Enable LPC ROM range end at 0xffff(ffff). */
    pci_write_config16(dev, 0x6e, 0xffff);
 }
> -----Original Message-----
> From: [e-mail]

[mailto:[e-mail]]
> On Behalf Of Stefan Reinauer
> Sent: Saturday, December 11, 2010 2:48 AM
> To: Scott Duplichan
> Cc: 'Peter Stuge'; [e-mail]
> Subject: Re: [coreboot] [PATCH] Set the register based on the ROMSIZE
> Scott Duplichan  [101210 18:13]:
> > Peter Stuge wrote:
> >
> > ]I have a greater problem with this;
> > ]
> > ]It assumes that one image will always go into one and the same size
> > ]of flash chip.
> >
> > I think I understand your concern. It is convenient to be able to
> > use a bigger chip to test a smaller image. But limiting the decode
> > size will only block access to the usused portion of the chip,

correct?
> One of the original design ideas of CBFS (or LAR in v3) was that we

can
> build a single image, with, say 256KB, and resize that same image

later
> on in case someone wants to put in fallback/normal, a linux kernel
> payload or stuff like that.
>
> Stefan

[PATCH] Set the register based on the ROMSIZE (Patch is updated)

[Peter Stuge]

Bao, Zheng wrote:
> Set the ROMSIZE as 4MB.
>
> Signed-off-by: Zheng Bao

Thanks!

Acked-by: Peter Stuge

[PATCH] Set the register based on the ROMSIZE (Patch is updated)

[Uwe Hermann]

Hi,

On Mon, Dec 13, 2010 at 05:47:33PM +0800, Bao, Zheng wrote:
> +config BOOTBLOCK_SOUTHBRIDGE_INIT
> string
> default "southbridge/amd/sb600/bootblock.c"
> depends on SOUTHBRIDGE_AMD_SB600

[...]
> +config BOOTBLOCK_SOUTHBRIDGE_INIT
> string
> default "southbridge/amd/sb700/bootblock.c"
> depends on SOUTHBRIDGE_AMD_SB700

Thanks for adding these, looks like I forgot them in the TINY_BOOTBLOCK
patches.
> Enable 1MB (LPC) ROM access at 0xFFF00000 - 0xFFFFFFFF.
> Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
> Hardware should enable LPC ROM by pin straps. This function does not
> handle the theoretically possible PCI ROM, FWH, or SPI ROM
>
> configurations.
> The SB700 power-on default is to map 256K ROM space.
> The SB700 power-on default is to map 512K ROM space.

Nice! I guess these new values are correct, however I could not find
this specified in the SB700 datasheets (?) Is this undocumented or did
I not look in the right place?

The BKDG at
http://support.amd.com/us/Embedded_TechDocs/43366_sb7xx_bdg_pub_1.00.pdf
says:

"Upon system power on, the SB700 enables 256K ROM by default. The BIOS needs
to enable 512K ROM or up to 1M for LPC ROM, if required."

It also only mentions 512KB and 1MB configs (no mention of up to 4MB
being supported). Is the datasheet outdated maybe?

Thanks, Uwe.

[PATCH] Set the register based on the ROMSIZE (Patch is updated)

[Bao, Zheng]

I also start to be confused.

In the sb700 rrg, it says the default value of reg [0x14,3,0x6c] is
0xFFF8, which means 512K. But actually, I took a look at the real board
with a blank BIOS chip. The default value is 0xFFF0, which means 1MB.

I think we should believe the real thing other than the datasheet when
they conflict.

Zheng
> -----Original Message-----
> From: Uwe Hermann [mailto:[e-mail]]
> Sent: Tuesday, December 14, 2010 10:05 AM
> To: Bao, Zheng
> Cc: Stefan Reinauer; Scott Duplichan; Peter Stuge;

[e-mail]
> Subject: Re: [coreboot] [PATCH] Set the register based on the ROMSIZE
> (Patch is updated)
>
> Hi,
>
> On Mon, Dec 13, 2010 at 05:47:33PM +0800, Bao, Zheng wrote:
> > +config BOOTBLOCK_SOUTHBRIDGE_INIT
> > string
> > default "southbridge/amd/sb600/bootblock.c"
> > depends on SOUTHBRIDGE_AMD_SB600
>
> [...]
> > +config BOOTBLOCK_SOUTHBRIDGE_INIT
> > string
> > default "southbridge/amd/sb700/bootblock.c"
> > depends on SOUTHBRIDGE_AMD_SB700
>
> Thanks for adding these, looks like I forgot them in the

TINY_BOOTBLOCK
> patches.
> > Enable 1MB (LPC) ROM access at 0xFFF00000 - 0xFFFFFFFF.
> > Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
> > Hardware should enable LPC ROM by pin straps. This function does

not
> > handle the theoretically possible PCI ROM, FWH, or SPI ROM
> >
> > configurations.
> > The SB700 power-on default is to map 256K ROM space.
> > The SB700 power-on default is to map 512K ROM space.
>
> Nice! I guess these new values are correct, however I could not find
> this specified in the SB700 datasheets (?) Is this undocumented or did
> I not look in the right place?
>
> The BKDG at

http://support.amd.com/us/Embedded_TechDocs/43366_sb7xx_bdg_pub_1.00.pdf
> says:
>
> "Upon system power on, the SB700 enables 256K ROM by default. The BIOS
> needs
> to enable 512K ROM or up to 1M for LPC ROM, if required."
>
> It also only mentions 512KB and 1MB configs (no mention of up to 4MB
> being supported). Is the datasheet outdated maybe?
> Thanks, Uwe.
>
> http://hermann-uwe.de     | http://sigrok.org
> http://randomprojects.org | http://unmaintained-free-software.org

[PATCH] Set the register based on the ROMSIZE (Patch is updated)

[Scott Duplichan]

]I also start to be confused.

]In the sb700 rrg, it says the default value of reg [0x14,3,0x6c] is
]0xFFF8, which means 512K. But actually, I took a look at the real board
]with a blank BIOS chip. The default value is 0xFFF0, which means 1MB.

Yes, you are correct. The documentation is wrong. This creates a problem
when booting on simnow because simnow matches the documentation, and not
the real BIOS. When I build Mahogany or Kino for a 1MB flash chip, it
will run on real hardware but fail on simnow. I have to use a private 
patch or modify the 6C register manually to test Mahogany or Kino on simnow.

Thanks,
Scott

]I think we should believe the real thing other than the datasheet when
]they conflict.

]Zheng
> -----Original Message-----
> From: Uwe Hermann [mailto:[e-mail]]
> Sent: Tuesday, December 14, 2010 10:05 AM
> To: Bao, Zheng
> Cc: Stefan Reinauer; Scott Duplichan; Peter Stuge;

[e-mail]
> Subject: Re: [coreboot] [PATCH] Set the register based on the ROMSIZE
> (Patch is updated)
>
> Hi,
>
> On Mon, Dec 13, 2010 at 05:47:33PM +0800, Bao, Zheng wrote:
> > +config BOOTBLOCK_SOUTHBRIDGE_INIT
> > string
> > default "southbridge/amd/sb600/bootblock.c"
> > depends on SOUTHBRIDGE_AMD_SB600
>
> [...]
> > +config BOOTBLOCK_SOUTHBRIDGE_INIT
> > string
> > default "southbridge/amd/sb700/bootblock.c"
> > depends on SOUTHBRIDGE_AMD_SB700
>
> Thanks for adding these, looks like I forgot them in the

TINY_BOOTBLOCK
> patches.
> > Enable 1MB (LPC) ROM access at 0xFFF00000 - 0xFFFFFFFF.
> > Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
> > Hardware should enable LPC ROM by pin straps. This function does

not
> > handle the theoretically possible PCI ROM, FWH, or SPI ROM
> >
> > configurations.
> > The SB700 power-on default is to map 256K ROM space.
> > The SB700 power-on default is to map 512K ROM space.
>
> Nice! I guess these new values are correct, however I could not find
> this specified in the SB700 datasheets (?) Is this undocumented or did
> I not look in the right place?
>
> The BKDG at

http://support.amd.com/us/Embedded_TechDocs/43366_sb7xx_bdg_pub_1.00.pdf
> says:
>
> "Upon system power on, the SB700 enables 256K ROM by default. The BIOS
> needs
> to enable 512K ROM or up to 1M for LPC ROM, if required."
>
> It also only mentions 512KB and 1MB configs (no mention of up to 4MB
> being supported). Is the datasheet outdated maybe?

The sb700 rrg documentation for register 6C in function 3 indirectly
states 4GB and greater is supported. Some LPC flash chips (SST49LF004B)
locate their manufacturer and device ID code at FFBC0000, so decoding
this address must be supported.
developer.amd.com/assets/43009_sb7xx_rrg_pub_1.00.pdf

Thanks,
Scott
> Thanks, Uwe.
>
> http://hermann-uwe.de     | http://sigrok.org
> http://randomprojects.org | http://unmaintained-free-software.org

[Stefan Reinauer]

* Peter Stuge  [101210 17:54]:
> Patrick Georgi wrote:
> > > Set the register based on the ROMSIZE.
>
> ..
> > How about
> > pci_write_config16(dev, 0x6c,
> > 0x10000-(max(512,CONFIG_COREBOOT_ROMSIZE_KB)>>6));
> > instead?
>
> I have a greater problem with this;
>
> It assumes that one image will always go into one and the same size
> of flash chip.
>
> We can not support growing or shrinking of CBFS if we would like to,
> and hotswapping flash chips with larger size does not work.
>
> I would personally prefer using the largest possible value on all
> chipsets.

Yes, I agree with Peter... Is there a reason to not enable the biggest
possible area all the time?

Stefan