{0x1002, 0x4377, "ATI SB400", enable_flash_sb400}, // ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80)
After doing some review trying to get more info so I can work to implement ATI chipset support I believe there is a typo in the code. as shown above.
after doing much research I find the smbus is always at 0x1002, 0x4372 while the code is looking at 0x4377 could someone please explain this.
Thanks -Jory
{0x1002, 0x4377, "ATI SB400", enable_flash_sb400}, // ATI
Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80)
After doing some review trying to get more info so I can work to implement ATI chipset support I believe there is a typo in the code. as shown above.
after doing much research I find the smbus is always at 0x1002, 0x4372 while the code is looking at 0x4377 could someone please explain this.
1002:4377 is the ISA bridge, as the code comment indeed states.
What is confusing you?
Segher
* Jory A. Pratt geekypenguin@gmail.com [070121 20:29]:
{0x1002, 0x4377, "ATI SB400", enable_flash_sb400}, // ATI
Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80)
After doing some review trying to get more info so I can work to implement ATI chipset support I believe there is a typo in the code. as shown above.
after doing much research I find the smbus is always at 0x1002, 0x4372 while the code is looking at 0x4377 could someone please explain this.
Yes. Enabling flash writes requires touching the ISA bridge. You dont need the smbus for that task. What made you assume so?