Hi,
DRAM range verified.
Well the check is quite simple maybe it works for simple cases and fails for real usage. I guess you need to port something like http://pyropus.ca/software/memtester/ to ROMCC to romstage and try again. All it sounds like raminit problem.
Also I don't like couple of things btw. You never showed any of your code. You only ask sometimes too simple question without bothering too much with them. Please try hard before asking and try to learn new stuff. You have chosen quite difficult area, maybe you should try some simpler stuff first to get in touch better with C and common toolchains and after that get back here in here.
Thanks Rudolf
Done. Loading image. Searching for fallback/coreboot_ram Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (180224 bytes), entry @ 0x100000 Stage: done loading. Jumping to image.
On Tue, Feb 7, 2012 at 3:07 AM, Rudolf Marekr.marek@assembler.cz wrote:
Seems there is a case or two of possible infinite while() loops within the uart8250 serial console code. This is a wild guess, but the uart
Yeah I dont like that too. Maybe worth to do a timeout? Or Loop count? It is always better to boot than to have perfect serial output ;)
But in this case I would think memory is not 100% OK. Worth to check if 1M->3M is OK (this is where coreboot ramstage goes)
Thanks Rudolf
-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Rudolf, When i started to study Coreboot and BIOS , people always made me confused by nonsense words. I asked some useful questions but interpreted as simple.(now I have developed a project which can drive RAM, serial port and hard disk)
The managers of this project even do not accept their own mistakes. Now FILO can not be compiled and when i report it as the README of the filo is saying, the manager emails me and tells me that you are not a programmer!!
I thought i would be encouraged for that by a thank you. When i ask a question nobody talks about the details of the logic behind that except one person, Kyösti Mälkki.
Hey folks, what is going on here? If you are a master of Coreboot why we have unrelated simple answers?
On 2/7/12, Rudolf Marek r.marek@assembler.cz wrote:
Hi,
DRAM range verified.
Well the check is quite simple maybe it works for simple cases and fails for real usage. I guess you need to port something like http://pyropus.ca/software/memtester/ to ROMCC to romstage and try again. All it sounds like raminit problem.
Also I don't like couple of things btw. You never showed any of your code. You only ask sometimes too simple question without bothering too much with them. Please try hard before asking and try to learn new stuff. You have chosen quite difficult area, maybe you should try some simpler stuff first to get in touch better with C and common toolchains and after that get back here in here.
Thanks Rudolf
Done. Loading image. Searching for fallback/coreboot_ram Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (180224 bytes), entry @ 0x100000 Stage: done loading. Jumping to image.
On Tue, Feb 7, 2012 at 3:07 AM, Rudolf Marekr.marek@assembler.cz wrote:
Seems there is a case or two of possible infinite while() loops within the uart8250 serial console code. This is a wild guess, but the uart
Yeah I dont like that too. Maybe worth to do a timeout? Or Loop count? It is always better to boot than to have perfect serial output ;)
But in this case I would think memory is not 100% OK. Worth to check if 1M->3M is OK (this is where coreboot ramstage goes)
Thanks Rudolf
-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
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ali hagigat -
Rudolf Marek