Re: [coreboot] TPM device has gone missing

[Trammell Hudson]

On Mon, Dec 12, 2016 at 03:08:53PM -0600, Aaron Durbin via coreboot wrote:
> What about the SSDT? With the patch I think the device is in the SSDT
> -- not DSDT.

Whups, forgot to include it.  There is far less change:

--- ./no-tpm/SSDT.dsl	2016-12-12 17:23:51.314355365 -0500
+++ ./yes-tpm/SSDT.dsl	2016-12-12 17:24:08.694610389 -0500
@@ -5,13 +5,13 @@
  * 
  * Disassembling to symbolic ASL+ operators
  *
- * Disassembly of SSDT, Mon Dec 12 17:23:51 2016
+ * Disassembly of SSDT, Mon Dec 12 17:24:08 2016
  *
  * Original Table Header:
  *     Signature        "SSDT"
  *     Length           0x0000170D (5901)
  *     Revision         0x02
- *     Checksum         0xB4
+ *     Checksum         0x83
  *     OEM ID           "CORE  "
  *     OEM Table ID     "COREBOOT"
  *     OEM Revision     0x0000002A (42)
@@ -73,7 +73,7 @@
         Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
         {
             Memory32Fixed (ReadOnly,
-                0xBFEED000,         // Address Base
+                0xBFEF0000,         // Address Base
                 0x00008000,         // Address Length
                 )
         })

TPM device has gone missing

[Aaron Durbin]

On Mon, Dec 12, 2016 at 4:25 PM, Trammell Hudson  wrote:
> On Mon, Dec 12, 2016 at 03:08:53PM -0600, Aaron Durbin via coreboot wrote:
> > What about the SSDT? With the patch I think the device is in the SSDT
> > -- not DSDT.
>
> Whups, forgot to include it.  There is far less change:

So it looks like the acpi TPM device generation didn't run at all.

What I think you need to make this work is a acpi_name() callback that
returns the correct name for the device passed in. See
src/soc/intel/skylake/acpi.c for matching names in ASL with the ACPI
generator. "LPCB" is what you need to return for the LPC device. The
binding of that callback is a little tricky because of the seemingly
independent southbridge and northbridge code. The easiest way might be
to add two acpi_name() callbacks to the device_operations:

1. src/northbridge/intel/sandybridge/northbridge.c that handles the
dev->path.type == DEVICE_PATH_DOMAIN case and return "PCI0"
2. src/southbridge/intel/bd82x6x/lpc.c that returns LPCB.
> --- ./no-tpm/SSDT.dsl   2016-12-12 17:23:51.314355365 -0500
> +++ ./yes-tpm/SSDT.dsl  2016-12-12 17:24:08.694610389 -0500
> @@ -5,13 +5,13 @@
> Disassembling to symbolic ASL+ operators
> Disassembly of SSDT, Mon Dec 12 17:23:51 2016
> Disassembly of SSDT, Mon Dec 12 17:24:08 2016
> Original Table Header:
> Signature        "SSDT"
> Length           0x0000170D (5901)
> Revision         0x02
> Checksum         0xB4
> Checksum         0x83
> OEM ID           "CORE  "
> OEM Table ID     "COREBOOT"
> OEM Revision     0x0000002A (42)
>
> @@ -73,7 +73,7 @@
>          Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
>          {
>              Memory32Fixed (ReadOnly,
>            0xBFEED000,         // Address Base
>            0xBFEF0000,         // Address Base
>            0x00008000,         // Address Length
>            )
>    })