Patch: jetway j7f[24] target

[Alex Mauer]

Attached please find a patch to add a target for the Jetway j7f2 and
j7f4 motherboard series, corresponding with the previously-added mainboard.

It is a copy of the epia-cn target, with only COREBOOT_EXTRA_VERSION
changed.

Signed-off-by: Alex Mauer

Property changes on: targets/jetway/j7f24
___________________________________________________________________
Added: svn:mergeinfo

Index: targets/jetway/j7f24/Config.lb
===================================================================
--- targets/jetway/j7f24/Config.lb	(revision 0)
+++ targets/jetway/j7f24/Config.lb	(revision 0)
@@ -0,0 +1,45 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 VIA Technologies, Inc.
+## (Written by Aaron Lwe  for VIA)
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+target jetway-j7f24
+mainboard jetway/j7f24
+
+option MAXIMUM_CONSOLE_LOGLEVEL=8
+option DEFAULT_CONSOLE_LOGLEVEL=8
+option CONFIG_CONSOLE_SERIAL8250=1
+
+# coreboot C code runs at this location in RAM
+option _RAMBASE=0x00004000
+
+#
+# If space is allotted for a VGA BIOS,
+# generate the final ROM like this:
+# cat vgabios bochsbios coreboot.rom > coreboot.rom.final
+#
+#option ROM_SIZE = (512 * 1024) - (64 * 1024) - (64 * 1024)
+option ROM_SIZE = (512 * 1024)
+
+romimage "image"
+	option COREBOOT_EXTRA_VERSION = "-j7f24"
+	payload ../payload.elf
+end
+
+buildrom ./coreboot.rom ROM_SIZE "image"

[ron minnich]

Acked-by: Ronald G. Minnich

Thanks!

ron

[Corey Osgood]

Doesn't this also need the superio changed to the fintek f71805f?

-Corey

On Thu, Sep 11, 2008 at 12:16 PM, ron minnich  wrote:
> Acked-by: Ronald G. Minnich
>
> Thanks!
>
> ron

[Alex Mauer]

Corey Osgood wrote:
> Doesn't this also need the superio changed to the fintek f71805f?

No, this just the target dir, which references the previously-created
mainboard dir where the superio was changed.

-Alex Mauer "hawke"

[Corey Osgood]

Ah, alright. I'll try to test it out on my j7f2 this weekend.

Thanks,
Corey

On Thu, Sep 11, 2008 at 1:12 PM, Alex Mauer  wrote:
> Corey Osgood wrote:
> > Doesn't this also need the superio changed to the fintek f71805f?
>
> No, this just the target dir, which references the previously-created
> mainboard dir where the superio was changed.
>
> -Alex Mauer "hawke"

[Stefan Reinauer]

Alex Mauer wrote:
> Attached please find a patch to add a target for the Jetway j7f2 and
> j7f4 motherboard series, corresponding with the previously-added mainboard.
>
> It is a copy of the epia-cn target, with only COREBOOT_EXTRA_VERSION
> changed.
>
> Signed-off-by: Alex Mauer

Hmm... I'm getting this one:

[e-mail]
    SMTP error from remote mail server after RCPT TO::
    host mail.hawkesnest.net [68.78.212.101]: 550 5.1.1 :
    Recipient address rejected: User unknown in local recipient table

Alex, can you read this?