Hello jankeso,
in the process of writing a board enable procedure for your mainboard I stumbled upon the fact that the chip used to control the write enable line is most likely your Super I/O chip, which is a NSC PC87364. superiotool currently does not support dumping that chip, so I can not verify that indeed the GPIO port of the Super I/O chip is accessed (at address 0x80C). I attached a patch to dump the contents of that chip to this mail. Please apply that patch to current superiotool CVS sources (to be obtained from svn://coreboot.org/repos/trunk/util/superiotool) and attach the output to a reply to this mail or upload to paste.flashrom.org.
This mail has been cc'ed to the coreboot list for getting this patch included into superiotool. If something is wrong with that patch, please Cc: me, as I am not subscribed to the coreboot list. Thanks.
Regards, Michael Karcher
Hi Michael,
seems to me that the GPIO is accessed as you predicted. I attach the output of superiorool -deV.
Regards, Michal
2011/3/2 Michael Karcher flashrom@mkarcher.dialup.fu-berlin.de:
Hello jankeso,
in the process of writing a board enable procedure for your mainboard I stumbled upon the fact that the chip used to control the write enable line is most likely your Super I/O chip, which is a NSC PC87364. superiotool currently does not support dumping that chip, so I can not verify that indeed the GPIO port of the Super I/O chip is accessed (at address 0x80C). I attached a patch to dump the contents of that chip to this mail. Please apply that patch to current superiotool CVS sources (to be obtained from svn://coreboot.org/repos/trunk/util/superiotool) and attach the output to a reply to this mail or upload to paste.flashrom.org.
This mail has been cc'ed to the coreboot list for getting this patch included into superiotool. If something is wrong with that patch, please Cc: me, as I am not subscribed to the coreboot list. Thanks.
Regards, Michael Karcher
* Michael Karcher flashrom@mkarcher.dialup.fu-berlin.de [110302 23:30]:
Hello jankeso,
in the process of writing a board enable procedure for your mainboard I stumbled upon the fact that the chip used to control the write enable line is most likely your Super I/O chip, which is a NSC PC87364. superiotool currently does not support dumping that chip, so I can not verify that indeed the GPIO port of the Super I/O chip is accessed (at address 0x80C). I attached a patch to dump the contents of that chip to this mail. Please apply that patch to current superiotool CVS sources (to be obtained from svn://coreboot.org/repos/trunk/util/superiotool) and attach the output to a reply to this mail or upload to paste.flashrom.org.
This mail has been cc'ed to the coreboot list for getting this patch included into superiotool. If something is wrong with that patch, please Cc: me, as I am not subscribed to the coreboot list. Thanks.
Regards, Michael Karcher
Add National Semiconductors PC87364.
Signed-off-by: Michael Karcher flashrom@mkarcher.dialup.fu-berlin.de
Acked-by: Stefan Reinauer stefan.reinauer@coreboot.org
Auf 04.03.2011 04:49, Stefan Reinauer schrieb:
- Michael Karcher flashrom@mkarcher.dialup.fu-berlin.de [110302 23:30]:
Add National Semiconductors PC87364.
Signed-off-by: Michael Karcher flashrom@mkarcher.dialup.fu-berlin.de
Acked-by: Stefan Reinauer stefan.reinauer@coreboot.org
Michael, AFAIK the flashrom and coreboot repositories have the same user rights, so in theory you should be able to commit.
Regards, Carl-Daniel
Hello coreboot developers,
Add National Semiconductors PC87364. Signed-off-by: Michael Karcher flashrom@mkarcher.dialup.fu-berlin.de
Acked-by: Stefan Reinauer stefan.reinauer@coreboot.org
Michael, AFAIK the flashrom and coreboot repositories have the same user rights, so in theory you should be able to commit.
how would you like me to proceed? Technically I most likely have commit rights to that repo, but I never felt as coreboot developer and don't read the coreboot mailing list. Should I nevertheless commit myself or should I have some coreboot guy commit that patch?
Regards, Michael Karcher
On 03/06/2011 01:53 AM, Michael Karcher wrote:
Hello coreboot developers,
Add National Semiconductors PC87364. Signed-off-by: Michael Karcher flashrom@mkarcher.dialup.fu-berlin.de
Acked-by: Stefan Reinauer stefan.reinauer@coreboot.org
Michael, AFAIK the flashrom and coreboot repositories have the same user rights, so in theory you should be able to commit.
how would you like me to proceed? Technically I most likely have commit rights to that repo, but I never felt as coreboot developer and don't read the coreboot mailing list. Should I nevertheless commit myself or should I have some coreboot guy commit that patch?
It was acked by Stefan. I think you can confidently commit.
Alex
Dear Michael,
I am adding you back to CC.
Am Sonntag, den 06.03.2011, 16:01 +0200 schrieb Alex G.:
On 03/06/2011 01:53 AM, Michael Karcher wrote:
Add National Semiconductors PC87364. Signed-off-by: Michael Karcher flashrom@mkarcher.dialup.fu-berlin.de
Acked-by: Stefan Reinauer stefan.reinauer@coreboot.org
Michael, AFAIK the flashrom and coreboot repositories have the same user rights, so in theory you should be able to commit.
how would you like me to proceed? Technically I most likely have commit rights to that repo, but I never felt as coreboot developer and don't read the coreboot mailing list. Should I nevertheless commit myself or should I have some coreboot guy commit that patch?
It was acked by Stefan. I think you can confidently commit.
I would also say that you can commit.
And Michael, why not become a coreboot developer and port your motherboard. You would be warmly welcomed. ;-)
Thanks,
Paul
Auf 04.03.2011 20:22, Carl-Daniel Hailfinger schrieb:
Auf 04.03.2011 04:49, Stefan Reinauer schrieb:
- Michael Karcher flashrom@mkarcher.dialup.fu-berlin.de [110302 23:30]:
Add National Semiconductors PC87364.
Signed-off-by: Michael Karcher flashrom@mkarcher.dialup.fu-berlin.de
Acked-by: Stefan Reinauer stefan.reinauer@coreboot.org
Michael, AFAIK the flashrom and coreboot repositories have the same user rights, so in theory you should be able to commit.
Sorry about the confusion.
Thanks for your patch! Committed to the coreboot repo in revision 6433.
Regards, Carl-Daniel