Oops, I've attached the boot log of a previous failed attempt. This boot log should be the correct one.
On Thu, Aug 31, 2017 at 1:29 PM, Keith Hui buurin@gmail.com wrote:
On Wed, Aug 30, 2017 at 6:49 PM, Kyösti Mälkki kyosti.malkki@gmail.com wrote:
On Wed, Aug 30, 2017 at 11:39 PM, Keith Hui buurin@gmail.com wrote:
Hi guys,
I'm still hard at work over the venerable (even "almighty" at the time) 440BX and Slot 1 boards.
[1] https://review.coreboot.org/c/20977/
And now I'm stuck and thoroughly confused.
My current state is:
- cbmem_initialize_empty() failed to even start allocating the root
CBMEM entry. No indication why. I tried tracing the code path in the sources and still could not find out where exactly it failed. With enough fiddling I did get it to complain the way Aaron expected [1].
Please update your work in gerrit, showing all the actual code changes you try to boot with. This includes changes under mainboard/.
- Using the common Intel CPU cache_as_ram.inc, I can get through
mainboard romstage and memory init. If I just return a fixed CONFIG_TOPMEM in setup_stack_and_mtrrs() like what was done in cpu/intel/nehalem, it got past the point of POST_PREPARE_RAMSTAGE and then nothing.
All that setup_stack_and_mtrrs() is not really required for EARLY_CBMEM_INIT, leave all that as followup work. Use unmodified car/romstage_legacy.c and car/cache_as_ram.inc with that DCACHE_RAM_BASE fixed.
Disable CBMEM console and timestamps for the time being, as those eat a lot of your CAR allocation. Those may have smashed your stack in CAR to the extent of breaking raminit.
- Porting the postcar frame assembly from
cpu/intel/car/cache_as_ram_ht.inc results in a failure somewhere before loading ramstage and after
Push your modified source to gerrit if you want comments on that.
- If I try to run this build under QEMU, it fails with "Trying to
execute code outside RAM or ROM at 0x000a0000" in 440BX RAM init code after dumping the "before" northbridge config, so I can't correctly debug it this way either.
Just forget about using QEMU for the task at hand.
Kyösti
Thanks for the tips Kyösti. Nothing like hearing it from the source. :)
I've updated gerrit again following your tips. This update actually boots! Boot log attached.
For cache_as_ram.inc I just dropped CacheBase/CacheSize and have it use the Kconfig settings directly. I also increased the CAR size to 8k.
Q1: Would this qualify as cbmem in romstage?
Set up stack and MTRRs in cpu/intel/slot_1 cbmem_top() and associated top of RAM calculations go to nb/intel/i440bx.
Q2: Are these the right places for these codes? All Slot 1 boards currently in tree use 440BX and much of them seem unmaintained. I only have 3 of them (-LS, P3B-F, -DS) and I don't have a second matching P3 CPU to test the DS. So I want to see if I can initialize CBMEM in cpu/intel/slot_1, lest work wasted with all those other boards getting dropped past 4.8?
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Keith Hui