Patch set updated for coreboot: 90ccbbf i3100: add smbus_write_byte()

[Sven Schnelle]

Sven Schnelle ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1116

-gerrit

commit 90ccbbf58200298cdec3194bcae25a24de0c787b
Author: Sven Schnelle 
Date:   Wed Jun 20 14:54:08 2012 +0200

i3100: add smbus_write_byte()

Required for Supermicro X7DB8, which needs the FBDIMM clock generator
    setup during romstage.

Change-Id: I30ca8354087e851487aee0614595782131d4d9bc
    Signed-off-by: Sven Schnelle 
---
 src/southbridge/intel/i3100/early_smbus.c |    7 ++++-
 src/southbridge/intel/i3100/smbus.h       |   43 +++++++++++++++++++++++++++++
 2 files changed, 49 insertions(+), 1 deletions(-)

diff --git a/src/southbridge/intel/i3100/early_smbus.c b/src/southbridge/intel/i3100/early_smbus.c
index f3d4450..3908390 100644
--- a/src/southbridge/intel/i3100/early_smbus.c
+++ b/src/southbridge/intel/i3100/early_smbus.c
@@ -37,7 +37,12 @@ static void enable_smbus(void)
    outb(0, SMBUS_IO_BASE + SMBHSTCTL);
 }

-static int smbus_read_byte(u32 device, u32 address)
+static  __attribute__((unused)) int smbus_read_byte(u32 device, u32 address)
 {
    return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
+
+static __attribute__((unused)) int smbus_write_byte(unsigned device, u8 address, u8 data)
+{
+	return do_smbus_write_byte(SMBUS_IO_BASE, device, address, data);
+}
diff --git a/src/southbridge/intel/i3100/smbus.h b/src/southbridge/intel/i3100/smbus.h
index 7023a5b..6879f0b 100644
--- a/src/southbridge/intel/i3100/smbus.h
+++ b/src/southbridge/intel/i3100/smbus.h
@@ -110,3 +110,46 @@ static int do_smbus_read_byte(u32 smbus_io_base, u16 device, u8 address)
    }
    return byte;
 }
+
+static  __attribute__((unused)) int do_smbus_write_byte(unsigned smbus_base, unsigned device, unsigned address, unsigned data)
+{
+	unsigned char global_status_register;
+
+	if (smbus_wait_until_ready(smbus_base) < 0)
+		return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+
+	/* Setup transaction */
+	/* Disable interrupts */
+	outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
+	/* Set the device I'm talking too */
+	outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD);
+	/* Set the command/address... */
+	outb(address & 0xff, smbus_base + SMBHSTCMD);
+	/* Set up for a byte data read */
+	outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
+	     (smbus_base + SMBHSTCTL));
+	/* Clear any lingering errors, so the transaction will run */
+	outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
+
+	/* Clear the data byte... */
+	outb(data, smbus_base + SMBHSTDAT0);
+
+	/* Start the command */
+	outb((inb(smbus_base + SMBHSTCTL) | 0x40),
+	     smbus_base + SMBHSTCTL);
+
+	/* Poll for transaction completion */
+	if (smbus_wait_until_done(smbus_base) < 0)
+		return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
+
+	global_status_register = inb(smbus_base + SMBHSTSTAT);
+
+	/* Ignore the "In Use" status... */
+	global_status_register &= ~(3 << 5);
+
+	/* Read results of transaction */
+	if (global_status_register != (1 << 1))
+		return SMBUS_ERROR;
+
+	return 0;
+}