Eric,
The ht reset in auto.c seems not thoroughly.
And it will stuck at hard_reset in amdk8_scan_chains. ( at this time can not access 8111 yet).
Regards
YH
LinuxBIOS-1.1.62.0_Normal Tue Mar 23 17:33:50 PST 2004 starting... setting up resource map....done. 04 nodes initialized. ht reset -Ram1.00 XÀm1.01 Ram1.02 Ram1.03 Ram2.00 Ram2.01 Ram2.02 Ram2.03 Ram3 Initializing memory: done Initializing memory: done Initializing memory: done Initializing memory: done Clearing LinuxBIOS memory: done Ram4 Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.62.0_Normal Tue Mar 23 17:46:40 PST 2004 booting... Finding PCI configuration type. PCI: Using configuration type 1 Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Enumerating: AMD K8 Enumerating: AMD K8 Enumerating: AMD K8 Enumerating: AMD 8111 Enumerating: Winbond w83627hf Enumerating buses...PCI: pci_scan_bus for bus 0 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] ops PCI: 00:19.3 [1022/1103] enabled PCI: 00:1a.0 [1022/1100] enabled PCI: 00:1a.1 [1022/1101] enabled PCI: 00:1a.2 [1022/1102] enabled PCI: 00:1a.3 [1022/1103] ops PCI: 00:1a.3 [1022/1103] enabled PCI: 00:1b.0 [1022/1100] enabled PCI: 00:1b.1 [1022/1101] enabled PCI: 00:1b.2 [1022/1102] enabled PCI: 00:1b.3 [1022/1103] ops PCI: 00:1b.3 [1022/1103] enabled amdk8_scan_chains max: 0 starting... Hyper transport scan link: 1 max: 1 PCI: 01:01.0 [1022/7450] enabled next_unitid: 0003 PCI: 01:03.0 [1022/7460] enabled next_unitid: 0007 HyperT reset needed
YhLu YhLu@tyan.com writes:
Eric,
The ht reset in auto.c seems not thoroughly.
And it will stuck at hard_reset in amdk8_scan_chains. ( at this time can not access 8111 yet).
Correct. The early hypertransport initialization code is not complete in the 4P case. That incompleteness triggers the later fixups.
I could not test that case, and there were at least some small difficulties in that it was not obvious how the 4P case should be extended to work properly.
Why you are getting stuck in amdk8_scan_chains I do not currently understand yet. I suspect Stefan's suggestion of a delayed reset is the appropriate course to implement.
Eric
* Eric W. Biederman ebiederman@lnxi.com [040324 08:42]:
Correct. The early hypertransport initialization code is not complete in the 4P case. That incompleteness triggers the later fixups.
I assume you talk about the setup of the coherent devices.
I could not test that case, and there were at least some small difficulties in that it was not obvious how the 4P case should be extended to work properly.
Can you go a bit into detail, please?
Why you are getting stuck in amdk8_scan_chains I do not currently understand yet. I suspect Stefan's suggestion of a delayed reset is the appropriate course to implement.
Do you have an example situation that would cause the need for a late reset? It would sound clean to only touch this part of the system once and at one place. If this is possible, we safe looking at 50% of the involved code in case something goes wrong..
Stefan
Stefan Reinauer stepan@suse.de writes:
- Eric W. Biederman ebiederman@lnxi.com [040324 08:42]:
Correct. The early hypertransport initialization code is not complete in the 4P case. That incompleteness triggers the later fixups.
I assume you talk about the setup of the coherent devices.
Yes, I was. Although it should only be incomplete incoherent HT that would cause this.
I could not test that case, and there were at least some small difficulties in that it was not obvious how the 4P case should be extended to work properly.
Can you go a bit into detail, please?
Mostly I could not clearly see which links I needed to call optimize_connection() on.
Why you are getting stuck in amdk8_scan_chains I do not currently understand yet. I suspect Stefan's suggestion of a delayed reset is the appropriate course to implement.
Do you have an example situation that would cause the need for a late reset? It would sound clean to only touch this part of the system once and at one place. If this is possible, we safe looking at 50% of the involved code in case something goes wrong..
2 or more HT I/O chains that are not setup at boot time.
Eric
* Eric W. Biederman ebiederman@lnxi.com [040324 19:37]:
Mostly I could not clearly see which links I needed to call optimize_connection() on.
Ah. I think we can now safely get this information from generate_row.
Do you have an example situation that would cause the need for a late reset? It would sound clean to only touch this part of the system once and at one place. If this is possible, we safe looking at 50% of the involved code in case something goes wrong..
2 or more HT I/O chains that are not setup at boot time.
Does this imply that incoherent ht setup has to be called every time a new cpu is enabled, to see whether there are bridges connected to this cpu?
Stefan
-
ebiederman＠lnxi.com -
Stefan Reinauer -
YhLu