It seems the soft reset didn't rest the MB and ...
Ollie,
Can you check that in S2885? And I think if you changed the hard_reset and soft_reset to bus 1, it may not rest the ht.
Regards
Yinghai Lu
-----邮件原件----- 发件人: YhLu 发送时间: 2004年3月23日 19:22 收件人: ebiederman@lnxi.com; Stefan Reinauer; ron minnich 抄送: linuxbios@clustermatic.org 主题: S4882 support
Eric,
The ht reset in auto.c seems not thoroughly.
And it will stuck at hard_reset in amdk8_scan_chains. ( at this time can not access 8111 yet).
Regards
YH
LinuxBIOS-1.1.62.0_Normal Tue Mar 23 17:33:50 PST 2004 starting... setting up resource map....done. 04 nodes initialized. ht reset -Ram1.00 XÀm1.01 Ram1.02 Ram1.03 Ram2.00 Ram2.01 Ram2.02 Ram2.03 Ram3 Initializing memory: done Initializing memory: done Initializing memory: done Initializing memory: done Clearing LinuxBIOS memory: done Ram4 Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.62.0_Normal Tue Mar 23 17:46:40 PST 2004 booting... Finding PCI configuration type. PCI: Using configuration type 1 Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Enumerating: AMD K8 Enumerating: AMD K8 Enumerating: AMD K8 Enumerating: AMD 8111 Enumerating: Winbond w83627hf Enumerating buses...PCI: pci_scan_bus for bus 0 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] ops PCI: 00:19.3 [1022/1103] enabled PCI: 00:1a.0 [1022/1100] enabled PCI: 00:1a.1 [1022/1101] enabled PCI: 00:1a.2 [1022/1102] enabled PCI: 00:1a.3 [1022/1103] ops PCI: 00:1a.3 [1022/1103] enabled PCI: 00:1b.0 [1022/1100] enabled PCI: 00:1b.1 [1022/1101] enabled PCI: 00:1b.2 [1022/1102] enabled PCI: 00:1b.3 [1022/1103] ops PCI: 00:1b.3 [1022/1103] enabled amdk8_scan_chains max: 0 starting... Hyper transport scan link: 1 max: 1 PCI: 01:01.0 [1022/7450] enabled next_unitid: 0003 PCI: 01:03.0 [1022/7460] enabled next_unitid: 0007 HyperT reset needed
* YhLu YhLu@tyan.com [040324 04:57]:
It seems the soft reset didn't rest the MB and ...
Ollie,
Can you check that in S2885? And I think if you changed the hard_reset and soft_reset to bus 1, it may not rest the ht.
I've changed the reset code today so that the same code is used on all K8+AMD8111 systems
reset.c went to southbridge/amd/amd8111/amd8111_reset.c
In the config file, you can now specify the device doing the hard reset, instead of copy+write the reset code for every new mainboard:
default HARD_RESET_BUS=1 default HARD_RESET_DEVICE=5 default HARD_RESET_FUNCTION=0
It would be a lot nicer to find the device dynamically. Maybe that can get fixed together with dynamically creating pirq and the other tables some day..
The Tyan boards currently assume the 8111 reset logic is available at following positions on the PCI bus:
s2850 1:2.0 s2880 1:4.0 s2881 1:4.0 s2882 1:4.0 s2885 3:4.0 s4880 1:4.0
Yinghai, is this correct?
Stefan
On Wed, 2004-03-24 at 08:35, Stefan Reinauer wrote:
- YhLu YhLu@tyan.com [040324 04:57]:
It seems the soft reset didn't rest the MB and ...
Ollie,
Can you check that in S2885? And I think if you changed the hard_reset and soft_reset to bus 1, it may not rest the ht.
I've changed the reset code today so that the same code is used on all K8+AMD8111 systems
reset.c went to southbridge/amd/amd8111/amd8111_reset.c
In the config file, you can now specify the device doing the hard reset, instead of copy+write the reset code for every new mainboard:
default HARD_RESET_BUS=1 default HARD_RESET_DEVICE=5 default HARD_RESET_FUNCTION=0
These macros are K8 specific, should we add AMDK8 in front of it ?
It would be a lot nicer to find the device dynamically. Maybe that can get fixed together with dynamically creating pirq and the other tables some day..
The Tyan boards currently assume the 8111 reset logic is available at following positions on the PCI bus:
s2850 1:2.0 s2880 1:4.0 s2881 1:4.0 s2882 1:4.0 s2885 3:4.0 s4880 1:4.0
How do you actually determine this ? And how is this been programmed in LinuxBIOS ?
Ollie
* Li-Ta Lo ollie@lanl.gov [040324 17:18]:
In the config file, you can now specify the device doing the hard reset, instead of copy+write the reset code for every new mainboard:
default HARD_RESET_BUS=1 default HARD_RESET_DEVICE=5 default HARD_RESET_FUNCTION=0
These macros are K8 specific, should we add AMDK8 in front of it ?
Sounds reasonable. If we can be sure there will not be other platforms with wandering devices on the bus.
The Tyan boards currently assume the 8111 reset logic is available at following positions on the PCI bus:
s2850 1:2.0 s2880 1:4.0 s2881 1:4.0 s2882 1:4.0 s2885 3:4.0 s4880 1:4.0How do you actually determine this ? And how is this been programmed in LinuxBIOS ?
This was a hardcoded value in each occurence of reset.c:hard_reset(). The device location was put into the PCI_DEV( bus, dev, fn ) macro which is defined in the same file. The actual value was determined by looking at the debug output of each of the ports. The actual bus/device/function number can change depending on the order of the bus mapping, iirc. Changes to that part of the code made it necessary to change all of those files. If there is a small and elegant way of finding the ISA bridge: Advanced Micro Devices [AMD] AMD-8111 LPC device on the fly, we could get rid of the config macros all together. This would definitely be the best solution, since it lowers efforts to port LinuxBIOS to a new motherboard.
Stefan
On Wed, 2004-03-24 at 09:26, Stefan Reinauer wrote:
This was a hardcoded value in each occurence of reset.c:hard_reset(). The device location was put into the PCI_DEV( bus, dev, fn ) macro which is defined in the same file. The actual value was determined by looking at the debug output of each of the ports. The actual bus/device/function number can change depending on the order of the bus mapping, iirc. Changes to that part of the code made it necessary to change all of those files. If there is a small and elegant way of finding the ISA bridge: Advanced Micro Devices [AMD] AMD-8111 LPC device on the fly, we could get rid of the config macros all together. This would definitely be the best solution, since it lowers efforts to port LinuxBIOS to a new motherboard.
There was a function called coherent_ht_mainboard. Is it no longer used ?
Ollie
* Li-Ta Lo ollie@lanl.gov [040324 17:54]:
There was a function called coherent_ht_mainboard. Is it no longer used?
Yes. It was never used by any port but the tyan boards, and the code did some ht link setup. The functionality this code added (like optimizing hypertransport link speed) is done by the generic k8 code since quite a while. The functions are still there, tyan/*/hypertransport.c, but they are no longer called.
Stefan
On Wed, 24 Mar 2004, Li-Ta Lo wrote:
These macros are K8 specific, should we add AMDK8 in front of it ?
rather than spend too much time perfecting the macros, let's put the effort into finding the southbridge dynamically.
There's already some of that done in some of the ports.
ron
ron minnich rminnich@lanl.gov writes:
On Wed, 24 Mar 2004, Li-Ta Lo wrote:
These macros are K8 specific, should we add AMDK8 in front of it ?
rather than spend too much time perfecting the macros, let's put the effort into finding the southbridge dynamically.
There's already some of that done in some of the ports.
There are 2 places we use the hard_reset code.
1) Right at the top of hardwaremain.c before enumerate_static_devices in case we get into LinuxBIOS for some odd reason. Say the OS's wants to do a reboot. 2) In device/hypertransport.c where we to do something to get the HT settings on an I/O chain to go into effect.
The easiest thing to do is a global flag that says we need to reset the system in hypertransport.c and then to put all of the reset code after dev_enumerate.
There are still some details there to be worked out, but...
Eric
On Tue, 2004-03-23 at 20:57, YhLu wrote:
It seems the soft reset didn't rest the MB and ...
Ollie,
Can you check that in S2885? And I think if you changed the hard_reset and soft_reset to bus 1, it may not rest the ht.
What ?? I have to change it to bus 1 to make the reset work on S2885.
Ollie
Regards
Yinghai Lu
-----邮件原件----- 发件人: YhLu 发送时间: 2004年3月23日 19:22 收件人: ebiederman@lnxi.com; Stefan Reinauer; ron minnich 抄送: linuxbios@clustermatic.org 主题: S4882 support
Eric,
The ht reset in auto.c seems not thoroughly.
And it will stuck at hard_reset in amdk8_scan_chains. ( at this time can not access 8111 yet).
Regards
YH
LinuxBIOS-1.1.62.0_Normal Tue Mar 23 17:33:50 PST 2004 starting... setting up resource map....done. 04 nodes initialized. ht reset -Ram1.00 XÀm1.01 Ram1.02 Ram1.03 Ram2.00 Ram2.01 Ram2.02 Ram2.03 Ram3 Initializing memory: done Initializing memory: done Initializing memory: done Initializing memory: done Clearing LinuxBIOS memory: done Ram4 Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.62.0_Normal Tue Mar 23 17:46:40 PST 2004 booting... Finding PCI configuration type. PCI: Using configuration type 1 Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Enumerating: AMD K8 Enumerating: AMD K8 Enumerating: AMD K8 Enumerating: AMD 8111 Enumerating: Winbond w83627hf Enumerating buses...PCI: pci_scan_bus for bus 0 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] ops PCI: 00:19.3 [1022/1103] enabled PCI: 00:1a.0 [1022/1100] enabled PCI: 00:1a.1 [1022/1101] enabled PCI: 00:1a.2 [1022/1102] enabled PCI: 00:1a.3 [1022/1103] ops PCI: 00:1a.3 [1022/1103] enabled PCI: 00:1b.0 [1022/1100] enabled PCI: 00:1b.1 [1022/1101] enabled PCI: 00:1b.2 [1022/1102] enabled PCI: 00:1b.3 [1022/1103] ops PCI: 00:1b.3 [1022/1103] enabled amdk8_scan_chains max: 0 starting... Hyper transport scan link: 1 max: 1 PCI: 01:01.0 [1022/7450] enabled next_unitid: 0003 PCI: 01:03.0 [1022/7460] enabled next_unitid: 0007 HyperT reset needed
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