I've been trying to make the configuration spaces match between v2 and v3. The biggest difference left is the disabled/hidden devices which are not hidden in v3.
Any chance that's causing the problem?
I've also been trying to figure out where the legacy IO space (e.g. 0x3d4) gets routed to the card. Does this happen automatically because the VGA bit is set in the bridge?
Thanks, Myles
On Mon, Oct 20, 2008 at 12:38 PM, Myles Watson mylesgw@gmail.com wrote:
I've been trying to make the configuration spaces match between v2 and v3. The biggest difference left is the disabled/hidden devices which are not hidden in v3.
Any chance that's causing the problem?
I've also been trying to figure out where the legacy IO space (e.g. 0x3d4) gets routed to the card. Does this happen automatically because the VGA bit is set in the bridge?
legacy IO is the vga address range and the PC IO.
One of the config space registers should have ISA set.
ron
Myles Watson wrote:
I've been trying to make the configuration spaces match between v2 and v3. The biggest difference left is the disabled/hidden devices which are not hidden in v3.
Any chance that's causing the problem?
I've also been trying to figure out where the legacy IO space (e.g. 0x3d4) gets routed to the card. Does this happen automatically because the VGA bit is set in the bridge?
Yes, The vga bit on the subtractive bridge routes the graphics io.
How did you work around the vm86 problem? Did the graphics command register get re-enabled?
Marc
On Mon, Oct 20, 2008 at 1:48 PM, Marc Jones Marc.Jones@amd.com wrote:
Myles Watson wrote:
I've been trying to make the configuration spaces match between v2 and v3. The biggest difference left is the disabled/hidden devices which are not hidden in v3.
Any chance that's causing the problem?
I've also been trying to figure out where the legacy IO space (e.g. 0x3d4) gets routed to the card. Does this happen automatically because the VGA bit is set in the bridge?
Yes, The vga bit on the subtractive bridge routes the graphics io.
How did you work around the vm86 problem? Did the graphics command register get re-enabled?
I made the interrupts self contained, with no output. The VGA ROM initialization returns, but there is no output to the screen. At least the screen turns black on an int10 now, though.
The only differences between the PCI configuration registers now is that v3 has a little larger space for VGA and SERR is set.
Thanks, Myles
On Mon, Oct 20, 2008 at 1:56 PM, Myles Watson mylesgw@gmail.com wrote:
On Mon, Oct 20, 2008 at 1:48 PM, Marc Jones Marc.Jones@amd.com wrote:
Myles Watson wrote:
I've been trying to make the configuration spaces match between v2 and v3. The biggest difference left is the disabled/hidden devices which are not hidden in v3.
Any chance that's causing the problem?
I've also been trying to figure out where the legacy IO space (e.g. 0x3d4) gets routed to the card. Does this happen automatically because the VGA bit is set in the bridge?
Yes, The vga bit on the subtractive bridge routes the graphics io.
How did you work around the vm86 problem? Did the graphics command register get re-enabled?
I made the interrupts self contained, with no output. The VGA ROM initialization returns, but there is no output to the screen. At least the screen turns black on an int10 now, though.
I sent the patch to the list in a message with the subject "temporary fix"
Now x86emu and vm86 have the same behavior. The both end with a black display but working serial.
Thanks, Myles
Myles Watson wrote:
On Mon, Oct 20, 2008 at 1:48 PM, Marc Jones <Marc.Jones@amd.com mailto:Marc.Jones@amd.com> wrote:
Myles Watson wrote: I've been trying to make the configuration spaces match between v2 and v3. The biggest difference left is the disabled/hidden devices which are not hidden in v3. Any chance that's causing the problem? I've also been trying to figure out where the legacy IO space (e.g. 0x3d4) gets routed to the card. Does this happen automatically because the VGA bit is set in the bridge? Yes, The vga bit on the subtractive bridge routes the graphics io. How did you work around the vm86 problem? Did the graphics command register get re-enabled?I made the interrupts self contained, with no output. The VGA ROM initialization returns, but there is no output to the screen. At least the screen turns black on an int10 now, though.
The only differences between the PCI configuration registers now is that v3 has a little larger space for VGA and SERR is set.
Ok, That should be fine. Black usually means all FF in the vga memory. Check A000-BFFFF are getting to the controller. VGA enable in the bridge control register (3e) and VGA pallet snoop in the command register (04) should be set in the bridge.
Marc
Marc Jones wrote:
Myles Watson wrote:
On Mon, Oct 20, 2008 at 1:48 PM, Marc Jones <Marc.Jones@amd.com mailto:Marc.Jones@amd.com> wrote:
Myles Watson wrote: I've been trying to make the configuration spaces match between v2 and v3. The biggest difference left is the disabled/hidden devices which are not hidden in v3. Any chance that's causing the problem? I've also been trying to figure out where the legacy IO space (e.g. 0x3d4) gets routed to the card. Does this happen automatically because the VGA bit is set in the bridge? Yes, The vga bit on the subtractive bridge routes the graphics io. How did you work around the vm86 problem? Did the graphics command register get re-enabled?I made the interrupts self contained, with no output. The VGA ROM initialization returns, but there is no output to the screen. At least the screen turns black on an int10 now, though.
The only differences between the PCI configuration registers now is that v3 has a little larger space for VGA and SERR is set.
Ok, That should be fine. Black usually means all FF in the vga memory. Check A000-BFFFF are getting to the controller. VGA enable in the bridge control register (3e) and VGA pallet snoop in the command register (04) should be set in the bridge.
Sorry, I had that backwards FF is blinking white, 00 is black.
Marc
On Mon, Oct 20, 2008 at 2:26 PM, Marc Jones Marc.Jones@amd.com wrote:
Myles Watson wrote:
On Mon, Oct 20, 2008 at 1:48 PM, Marc Jones <Marc.Jones@amd.com mailto: Marc.Jones@amd.com> wrote:
Myles Watson wrote:
I've been trying to make the configuration spaces match between v2 and v3. The biggest difference left is the disabled/hidden devices which are not hidden in v3. Any chance that's causing the problem? I've also been trying to figure out where the legacy IO space (e.g. 0x3d4) gets routed to the card. Does this happen automatically because the VGA bit is set in the bridge?Yes, The vga bit on the subtractive bridge routes the graphics io.
How did you work around the vm86 problem? Did the graphics command register get re-enabled?
I made the interrupts self contained, with no output. The VGA ROM initialization returns, but there is no output to the screen. At least the screen turns black on an int10 now, though.
The only differences between the PCI configuration registers now is that v3 has a little larger space for VGA and SERR is set.
Ok, That should be fine. Black usually means all FF in the vga memory. Check A000-BFFFF are getting to the controller. VGA enable in the bridge control register (3e) and VGA pallet snoop in the command register (04) should be set in the bridge.
As far as I can tell it's set correctly. I've included the config space below. What I wanted to see was the VGA BIOS message on the display when it initializes.
Thanks, Myles
0 6 0 AMD-8111 PCI 74601022 02300147 06040007 00014000 00000000 00000000 40010100 02001010 FE00FD00 FFE0FFF0 00000000 00000000 00000000 000000C0 00000000 042B00FF 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 06040000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 0086F008 00000022 000000D0 00010022 00000002 00000000 00000000 00000000 00000008 00000008 0000000F 00000000 80000008 00000000 00000000 00000000
1 4 0 Display Controller 20671022 02A00143 03000003 00004010 FD000000 FE055000 00001001 00000000 00000000 00000000 00000000 00000000 FE040001 00000000 00000000 C0C00100 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 0 24 0 K8 [Athlon64/Opteron] HyperTransport Technology Configuration 11001022 00100000 06000000 00800000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000080 00000000 00000000 00010101 00010101 00010101 00010101 00010101 00010101 00010101 00010101 00000000 000000E4 0F00C800 00000070 00000000 00000000 00000000 00000000 2101A008 11110020 80750622 00000002 02510456 00030000 00000007 00000000 2101C008 771100D0 80750022 00000002 02510456 00000000 00000002 00000000 21010008 771100D0 80750022 00000002 02510456 00000000 00000002 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 0 24 1 K8 [Athlon64/Opteron] Address Map 11011022 00000000 06000000 00800000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000003 000F0000 00000000 00000001 00000000 00000002 00000000 00000003 00000000 00000004 00000000 00000005 00000000 00000006 00000000 00000007 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000A03 00000B00 00FD0003 00FE1F00 00000000 00000000 00001013 00002000 00000000 00000000 00000000 00000000 00000000 00000000 03000003 00000000 00000000 00000000 00000000 00000000 00000000 00000000
Myles Watson wrote:
0 6 0 AMD-8111 PCI 74601022 02300147 06040007 00014000 00000000 00000000 40010100 02001010 FE00FD00 FFE0FFF0 00000000 00000000 00000000 000000C0 00000000 042B00FF
^ ISA isn't set. That might be a problem.
On Mon, Oct 20, 2008 at 4:10 PM, Marc Jones Marc.Jones@amd.com wrote:
Myles Watson wrote:
0 6 0 AMD-8111 PCI 74601022 02300147 06040007 00014000 00000000 00000000 40010100 02001010 FE00FD00 FFE0FFF0 00000000 00000000 00000000 000000C0 00000000 042B00FF
^ISA isn't set. That might be a problem.
I can't tell that v2 ever sets it. In the 8111 datasheet it looks like that bit makes it so that bits 8 & 9 of the address get ignored so that only 256B of every 1024 are accessible. I don't think that's what we want.
Looking for that I found an interesting couple of defines.
include/device/pci_def.h:#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ include/device/pci_def.h:#define PCI_CB_BRIDGE_CTL_ISA 0x04
I can see that they're used in two different places (one for the hardware, one for the device struct), but it still seems confusing.
Thanks, Myles
Myles Watson wrote:
On Mon, Oct 20, 2008 at 4:10 PM, Marc Jones <Marc.Jones@amd.com mailto:Marc.Jones@amd.com> wrote:
Myles Watson wrote: 0 6 0 AMD-8111 PCI 74601022 02300147 06040007 00014000 00000000 00000000 40010100 02001010 FE00FD00 FFE0FFF0 00000000 00000000 00000000 000000C0 00000000 042B00FF ^ ISA isn't set. That might be a problem.I can't tell that v2 ever sets it. In the 8111 datasheet it looks like that bit makes it so that bits 8 & 9 of the address get ignored so that only 256B of every 1024 are accessible. I don't think that's what we want.
Looking for that I found an interesting couple of defines.
include/device/pci_def.h:#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ include/device/pci_def.h:#define PCI_CB_BRIDGE_CTL_ISA 0x04
I can see that they're used in two different places (one for the hardware, one for the device struct), but it still seems confusing.
You are correct. I misunderstood this setting. I don't think that it should be set. I think that the problem is probably in the mmio map that Ron posted yesterday. I'll keep looking at stage2 device init and then I'll check out what is going on with mmio.
Marc
On Tue, Oct 21, 2008 at 10:20 AM, Marc Jones Marc.Jones@amd.com wrote:
Myles Watson wrote:
On Mon, Oct 20, 2008 at 4:10 PM, Marc Jones <Marc.Jones@amd.com mailto: Marc.Jones@amd.com> wrote:
Myles Watson wrote:
0 6 0 AMD-8111 PCI 74601022 02300147 06040007 00014000 00000000 00000000 40010100 02001010 FE00FD00 FFE0FFF0 00000000 00000000 00000000 000000C0 00000000 042B00FF ^ISA isn't set. That might be a problem.
I can't tell that v2 ever sets it. In the 8111 datasheet it looks like that bit makes it so that bits 8 & 9 of the address get ignored so that only 256B of every 1024 are accessible. I don't think that's what we want.
Looking for that I found an interesting couple of defines.
include/device/pci_def.h:#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ include/device/pci_def.h:#define PCI_CB_BRIDGE_CTL_ISA 0x04
I can see that they're used in two different places (one for the hardware, one for the device struct), but it still seems confusing.
I think that the problem is probably in the mmio map that Ron posted yesterday.
This is my latest. The one Ron posted was from func 0 just after RAM init. This one is from func 1. After RAM init: DRAM(40)0000000000-000fffffff, ->(0), R, W, No interleave, 0 DRAM(48)0000000000-0000ffffff, ->(1), , , No interleave, 0 DRAM(50)0000000000-0000ffffff, ->(2), , , No interleave, 0 DRAM(58)0000000000-0000ffffff, ->(3), , , No interleave, 0 DRAM(60)0000000000-0000ffffff, ->(4), , , No interleave, 0 DRAM(68)0000000000-0000ffffff, ->(5), , , No interleave, 0 DRAM(70)0000000000-0000ffffff, ->(6), , , No interleave, 0 DRAM(78)0000000000-0000ffffff, ->(7), , , No interleave, 0 MMIO(80)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non posted 0 MMIO(88)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non posted 0 MMIO(90)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non posted 0 MMIO(98)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non posted 0 MMIO(a0)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non posted 0 MMIO(a8)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non posted 0 MMIO(b0)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non posted 0 MMIO(b8)00fc000000-00ffffffff, ->(0,0), R, W, CPU disable 0, Lock 0, Non posted 0 PCIIO(c0)00000003-01fff000 PCIIO(c0)00000000-01fff000, ->(0,0), R, W,VGA 0 ISA 0 PCIIO(c8)00000000-00000000 PCIIO(c8)00000000-00000000, ->(0,0), , ,VGA 0 ISA 0 PCIIO(d0)00000000-00000000 PCIIO(d0)00000000-00000000, ->(0,0), , ,VGA 0 ISA 0 PCIIO(d8)00000000-00000000 PCIIO(d8)00000000-00000000, ->(0,0), , ,VGA 0 ISA 0 CONFIG(e0)0000003f-00000000 ->(0,0),R W CE 0 CONFIG(e4)00000000-00000000 ->(0,0), CE 0 CONFIG(e8)00000000-00000000 ->(0,0), CE 0 CONFIG(ec)00000000-00000000 ->(0,0), CE 0
After assign resources ( I took out the ones that were all 0) DRAM(40)0000000000-000fffffff, ->(0), R, W, No interleave, 0 MMIO(a8)00000a0000-00000bffff, ->(0,0), R, W, CPU disable 0, Lock 0, Non posted 0 MMIO(b0)00fd000000-00fe1fffff, ->(0,0), R, W, CPU disable 0, Lock 0, Non posted 0 PCIIO(c0)00001000-00002000, ->(0,0), R, W,VGA 1 ISA 0 CONFIG(e0)00000003-00000000 ->(0,0),R W CE 0
Thanks, Myles
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Marc Jones -
Myles Watson -
ron minnich