Thomasheidler via coreboot coreboot@coreboot.org writes:
If one excludes any microcode and the VGA BIOS, is it possible to build a functioning, blobless coreboot for any Sandy Bridge or Ivy Bridge device supported? I'm referring here only to the BIOS region on the flash, not the ME region, IFD and GbE. If the FSP blob is needed, would that be the only blob required?
Coreboot has native x86 code to fully initialize sandy bridge without blobs. Even the VGA bios can be replaced with existing native graphic init (C code for LVDS or libgfxinit for every display output).
There is an FSP path for sandy bridge but it is not used much due to native code being easier to work with.
Thanks
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