IB520 Embedded MoBo

[Davide Visconti]

Hi to all,
I'm new in this mailing list. I have install, on my embedded system, a 
minimal version of Debian and/or Ubuntu, but... I must have a very fast 
boot, so I have see that my cpu and chipset are supported by LinuxBIOS.
I have a IB520 motherboard (http://www.ibase.com.tw/ib520.htm) with a 
CPU Geode LX 700 (433MHz) and the AMD CS5536 (south bridge).
The I/O chip is a Winbond W83627HF.
The BIOS is a PhoenixBios E686 on a chip SST 49LF004B 
(http://www.sst.com/products.xhtml/serial_flash/49/SST49LF004B).
If possible, I would want to put the linux kernel inside of the BIOS 
chipset.
I have attached the output of "lspci" and "lspci -vv" command.
Please, can you give any suggestion?
After the installation can I "reinstall" my old bios? How?
Thank you in advance.
bye Davide

ps: sorry for my bad English... it's rusted.

00:01.0 Host bridge: Advanced Micro Devices [AMD] Unknown device 2080 (rev 31)
00:01.1 VGA compatible controller: Advanced Micro Devices [AMD] Geode LX Video
00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX AES Security Block
00:0e.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10)
00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (rev 03)
00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE (rev 01)
00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC (rev 02)
00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02)

00:01.0 Host bridge: Advanced Micro Devices [AMD] Unknown device 2080 (rev 31)
    Subsystem: Advanced Micro Devices [AMD] Unknown device 2080
    Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
    Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
    Latency: 248, Cache Line Size: 32 bytes
    Region 0: I/O ports at ac1c [size=4]

00:01.1 VGA compatible controller: Advanced Micro Devices [AMD] Geode LX Video (prog-if 00 [VGA])
    Subsystem: Advanced Micro Devices [AMD] Geode LX Video
    Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
    Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
    Latency: 0, Cache Line Size: 32 bytes
    Interrupt: pin A routed to IRQ 11
    Region 0: Memory at ee000000 (32-bit, non-prefetchable) [size=16M]
    Region 1: Memory at ef000000 (32-bit, non-prefetchable) [size=16K]
    Region 2: Memory at ef004000 (32-bit, non-prefetchable) [size=16K]
    Region 3: Memory at ef008000 (32-bit, non-prefetchable) [size=16K]
    Region 4: Memory at ef00c000 (32-bit, non-prefetchable) [size=16K]

00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX AES Security Block
    Subsystem: Advanced Micro Devices [AMD] Geode LX AES Security Block
    Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
    Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
    Latency: 0, Cache Line Size: 32 bytes
    Interrupt: pin A routed to IRQ 11
    Region 0: Memory at ef010000 (32-bit, non-prefetchable) [size=16K]

00:0e.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10)
    Subsystem: Realtek Semiconductor Co., Ltd. RT8139
    Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
    Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
    Latency: 32 (8000ns min, 16000ns max)
    Interrupt: pin A routed to IRQ 11
    Region 0: I/O ports at e000 [size=256]
    Region 1: Memory at ef014000 (32-bit, non-prefetchable) [size=256]
    Capabilities: [50] Power Management version 2
    	Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0-,D1+,D2+,D3hot+,D3cold+)
    	Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (rev 03)
    Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA
    Control: I/O+ Mem- BusMaster- SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
    Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
    Region 0: I/O ports at 6000 [size=8]
    Region 1: I/O ports at 6100 [size=256]
    Region 2: I/O ports at 6200 [size=64]
    Region 3: I/O ports at 1000 [size=32]
    Region 4: I/O ports at 9d00 [size=128]
    Region 5: I/O ports at 9c00 [size=64]

00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE (rev 01) (prog-if 80 [Master])
    Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE
    Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
    Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
    Latency: 248, Cache Line Size: 32 bytes
    Region 0: [virtual] Memory at 000001f0 (32-bit, non-prefetchable) [disabled] [size=8]
    Region 1: [virtual] Memory at 000003f0 (type 3, non-prefetchable) [disabled] [size=1]
    Region 2: [virtual] Memory at 00000170 (32-bit, non-prefetchable) [disabled] [size=8]
    Region 3: [virtual] Memory at 00000370 (type 3, non-prefetchable) [disabled] [size=1]
    Region 4: I/O ports at f000 [size=16]

00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC (rev 02) (prog-if 10 [OHCI])
    Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC
    Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
    Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
    Latency: 0, Cache Line Size: 32 bytes
    Interrupt: pin D routed to IRQ 10
    Region 0: Memory at ef015000 (32-bit, non-prefetchable) [size=4K]
    Capabilities: [40] Power Management version 2
    	Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
    	Status: D0 PME-Enable- DSel=0 DScale=0 PME-

00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02) (prog-if 20 [EHCI])
    Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC
    Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
    Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
    Latency: 0, Cache Line Size: 32 bytes
    Interrupt: pin D routed to IRQ 10
    Region 0: Memory at ef016000 (32-bit, non-prefetchable) [size=4K]
    Capabilities: [40] Power Management version 2
    	Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
    	Status: D0 PME-Enable- DSel=0 DScale=0 PME-

[Peter Stuge]

Hi Davide,

Davide Visconti wrote:
> I'm new in this mailing list.

Welcome to the list!
> I have install, on my embedded system, a minimal version of Debian
> and/or Ubuntu, but... I must have a very fast boot, so I have see
> that my cpu and chipset are supported by LinuxBIOS.
> I have a IB520 motherboard (http://www.ibase.com.tw/ib520.htm) with
> a CPU Geode LX 700 (433MHz) and the AMD CS5536 (south bridge).
> The I/O chip is a Winbond W83627HF.
> The BIOS is a PhoenixBios E686 on a chip SST 49LF004B 
> (http://www.sst.com/products.xhtml/serial_flash/49/SST49LF004B).
> If possible, I would want to put the linux kernel inside of the
> BIOS chipset.
> I have attached the output of "lspci" and "lspci -vv" command.
> Please, can you give any suggestion?

This platform (Geode LX + CS5536) is well supported by coreboot, and
several similar mainboards are already working well, but some code
and data files will still be needed to make this specific mainboard
work.

SST49LF004B is a FWH type flash chip, and because it is in a socket
it is easy to replace with a larger flash chips. There are compatible
flash chips up to 16 Mbit (2Mbyte) in size, which is enough room for
a Linux kernel.
> After the installation can I "reinstall" my old bios? How?

The program flashrom (http://www.coreboot.org/Flashrom) can be used
to reprogram the contents of flash chips from Linux. But we strongly
recommend you to buy several extra flash chips, so that you can swap
between your factory BIOS and coreboot while developing. This is a
nice idea: http://www.coreboot.org/Image:Pushpin_roms_2.jpg

If you have some more money for the project it is nice to work with a
ROM emulator, but the cheapest ones we know cost 150-200 EUR or so.

If you want to work on adding support for this mainboard I suggest
starting with the code for the ALIX boards, they may be similar and
are well supported.

It will be helpful to have an engineering contact at iBASE, but if
they are uncooperative it can still be possible to support the board
in coreboot.

//Peter

[Davide Visconti]

> > I have install, on my embedded system, 
> > [...]
>
> This platform (Geode LX + CS5536) is well supported by coreboot, and
> several similar mainboards are already working well, but some code
> and data files will still be needed to make this specific mainboard
> work.
>
> SST49LF004B is a FWH type flash chip, and because it is in a socket
> it is easy to replace with a larger flash chips. There are compatible
> flash chips up to 16 Mbit (2Mbyte) in size, which is enough room for
> a Linux kernel.

Ok, Yes I thik that I can mount, for example, the SST49LF016C. (16Mbit)
> > After the installation can I "reinstall" my old bios? How?
>
> The program flashrom (http://www.coreboot.org/Flashrom) can be used
> to reprogram the contents of flash chips from Linux. But we strongly
> recommend you to buy several extra flash chips, so that you can swap
> between your factory BIOS and coreboot while developing. This is a
> nice idea: http://www.coreboot.org/Image:Pushpin_roms_2.jpg

That's right!
I will buy a extra flash chips, and, if possibile, a external hw for 
download/reset the firmware.
> If you have some more money for the project it is nice to work with a
> ROM emulator, but the cheapest ones we know cost 150-200 EUR or so.

Sorry but... What is a Rom emulator? Can you post a sample link?
> If you want to work on adding support for this mainboard I suggest
> starting with the code for the ALIX boards, they may be similar and
> are well supported.

My difficulty is that i start from zero.
For example, I have see on a ALIX tutorial page 
(http://www.coreboot.org/PC_Engines_ALIX1.C_Build_Tutorial) but I don't 
find any sample or howto for build the firmware...
How I can make for build a firmware with a linux kernel and after 
dowload it on a flash chips?

I can following this howto... ? 
(http://www.coreboot.org/AMD_Geode_Porting_Guide)

Thank you for your patience and your collaboration.
Davide

[Marc Jones]

Davide Visconti wrote:
> I can following this howto... ? 
> (http://www.coreboot.org/AMD_Geode_Porting_Guide)

Yes, That link is the best for getting started on adding a new mainboard.

If any parts are confusing please let us know so we can make that page 
better.

Thanks,
Marc

[Davide Visconti]

Hi,
I have try to build rom file but I have incountered several difficulties.
There insn't a simple howto step by step?
I follow the AMD_Geode_Porting_Guide but after download the buildrom
and coreboot.. for example where I must do the command make menuconfig 
and make?
I would want put into the bios the linux kernel for obtain a fast boot. 
If possibile? How?
Thak you in andvance.

Marc Jones ha scritto:
> Davide Visconti wrote:
> > I can following this howto... ? 
> > (http://www.coreboot.org/AMD_Geode_Porting_Guide)
>
> Yes, That link is the best for getting started on adding a new mainboard.
>
> If any parts are confusing please let us know so we can make that page 
> better.
>
> Thanks,
> Marc

[Myles Watson]

> Hi,
> I have try to build rom file but I have incountered several difficulties.
> There insn't a simple howto step by step?
> I follow the AMD_Geode_Porting_Guide but after download the buildrom
> and coreboot.. for example where I must do the command make menuconfig
> and make?

from buildrom/buildrom-devel/

if you want to configure coreboot v3
make coreboot-v3-config

if you want to choose the payload (in your case the linux kernel)
make menuconfig

Thanks,
Myles

[ron minnich]

we have people on this list who don't necessarily code but want to
help. If anybody wants to put together a web page with screen shots of
the buildrom process, starting from svn co of buildrom through make
menuconfig and a flashrom invocation, that would be a real help.

ron

[Davide Visconti]

That's right Ron, it would be a lot appreciated.
A simple howto that show step by step the operations for compile from 
svn and ...etc
I think that would be a beautiful idea.
Thanks however for the help that I have received.

ron minnich ha scritto:
> we have people on this list who don't necessarily code but want to
> help. If anybody wants to put together a web page with screen shots of
> the buildrom process, starting from svn co of buildrom through make
> menuconfig and a flashrom invocation, that would be a real help.
>
> ron

[Davide Visconti]

> > Hi,
> > I have try to build rom file but I have incountered several difficulties.
> > There insn't a simple howto step by step?
> > I follow the AMD_Geode_Porting_Guide but after download the buildrom
> > and coreboot.. for example where I must do the command make menuconfig
> > and make?
>
> from buildrom/buildrom-devel/
>
> if you want to configure coreboot v3
> make coreboot-v3-config
>
> if you want to choose the payload (in your case the linux kernel)
> make menuconfig
>
> Thanks,
> Myles

I have econtered an error during the compilation.
I have make these step:
- svn co svn://coreboot.org/buildrom
- svn co svn://coreboot.org/repos/trunk/coreboot-v2
- cd buildrom/buildrom-devel/
- make menuconfig
- make

When I run "make" I get the attached error.
How I make to understand where is the problem?

...and after the succesfull rom compilation?

Thank you in advance, Davide

root@ubuntu:~/buildrom/buildrom-devel# make
Fetching the mkelfimage rev 3473 code...
Unpacking mkelfimage...
Patching mkelfimage...
Building mkelfImage...
--18:37:57--  http://www.cs.cmu.edu/~ajw/public/dist//unifdef-1.0.tar.gz
           => `/root/buildrom/buildrom-devel/sources/unifdef-1.0.tar.gz'
Risoluzione di www.cs.cmu.edu in corso... 128.2.203.164
Connessione a www.cs.cmu.edu|128.2.203.164:80... connesso.
HTTP richiesta inviata, aspetto la risposta... 200 OK
Lunghezza: 15,850 (15K) [application/x-gzip]

100%[=============================================================================================================================>] 15,850        41.60K/s

18:37:59 (41.49 KB/s) - "/root/buildrom/buildrom-devel/sources/unifdef-1.0.tar.gz" salvato [15850/15850]

Patching unifdef...
Applying patch unifdef-build-fix.patch
Now at patch unifdef-build-fix.patch
Building unifdef (host)...
Fetching the AMD VSA binary...
wget  -P /root/buildrom/buildrom-devel/sources http://www.amd.com/files/connectivitysolutions/geode/geode_lx/amd_vsa_lx_1.0... -O /root/buildrom/buildrom-devel/sources/amd_vsa_lx_1.01.bin.gz
--18:38:02--  http://www.amd.com/files/connectivitysolutions/geode/geode_lx/amd_vsa_lx_1.0...
           => `/root/buildrom/buildrom-devel/sources/amd_vsa_lx_1.01.bin.gz'
Risoluzione di www.amd.com in corso... 80.67.86.31, 80.67.86.25
Connessione a www.amd.com|80.67.86.31:80... connesso.
HTTP richiesta inviata, aspetto la risposta... 200 OK
Lunghezza: non specificato [application/x-gzip]

[    <=>                                                                                                                       ] 57,504        56.40K/s

18:38:04 (56.36 KB/s) - "/root/buildrom/buildrom-devel/sources/amd_vsa_lx_1.01.bin.gz" salvato [57504]

--18:38:04--  http://kernel.org/pub/linux/kernel/v2.6//linux-2.6.20.2.tar.bz2
           => `/root/buildrom/buildrom-devel/sources/linux-2.6.20.2.tar.bz2'
Risoluzione di kernel.org in corso... 204.152.191.5, 204.152.191.37
Connessione a kernel.org|204.152.191.5:80... connesso.
HTTP richiesta inviata, aspetto la risposta... 200 OK
Lunghezza: 43,378,711 (41M) [application/x-bzip2]

100%[=============================================================================================================================>] 43,378,711   116.04K/s    ETA 00:00

18:42:54 (146.37 KB/s) - "/root/buildrom/buildrom-devel/sources/linux-2.6.20.2.tar.bz2" salvato [43378711/43378711]

Unpacking kernel (2.6.20.2)...
Patching kernel...
Building kernel...
Installing kernel headers...
Building the ELF payload...
Fetching the coreboot rev 3335 code...
Unpacking coreboot (coreboot-svn-3335.tar.gz)...
Patching coreboot...
Building target...
Building coreboot...
make: *** [/root/buildrom/buildrom-devel/work/coreboot/svn/targets//pcengines/alix1c/alix1c/coreboot.rom] Error 2
root@ubuntu:~/buildrom/buildrom-devel#

[Myles Watson]

> -----Original Message-----
> From: [e-mail] [mailto:[e-mail]]
> On Behalf Of Davide Visconti
> Sent: Thursday, October 16, 2008 11:27 AM
> To: Coreboot
> Subject: Re: [coreboot] IB520 Embedded MoBo
> > > Hi,
> > > I have try to build rom file but I have incountered several
>
> difficulties.
> > > There insn't a simple howto step by step?
> > > I follow the AMD_Geode_Porting_Guide but after download the buildrom
> > > and coreboot.. for example where I must do the command make menuconfig
> > > and make?
> >
> > from buildrom/buildrom-devel/
> >
> > if you want to configure coreboot v3
> > make coreboot-v3-config
> >
> > if you want to choose the payload (in your case the linux kernel)
> > make menuconfig
> >
> > Thanks,
> > Myles
>
> I have econtered an error during the compilation.
> I have make these step:
> svn co svn://coreboot.org/buildrom
> svn co svn://coreboot.org/repos/trunk/coreboot-v2
> cd buildrom/buildrom-devel/
> make menuconfig
> make
>
> When I run "make" I get the attached error.
> How I make to understand where is the problem?
>
> ...and after the succesfull rom compilation?
>
> Thank you in advance, Davide

The build log is buildrom/buildrom-devel/work/coreboot-v2/logs/build.log

That's where the real error is.

Thanks,
Myles

[Myles Watson]

On Thu, Oct 16, 2008 at 11:33 AM, Myles Watson  wrote:
> > -----Original Message-----
> > From: [e-mail] [mailto:
>
> [e-mail]]
> > On Behalf Of Davide Visconti
> > Sent: Thursday, October 16, 2008 11:27 AM
> > To: Coreboot
> > Subject: Re: [coreboot] IB520 Embedded MoBo
> > > > Hi,
> > > > I have try to build rom file but I have incountered several
> >
> > difficulties.
> > > > There insn't a simple howto step by step?
> > > > I follow the AMD_Geode_Porting_Guide but after download the buildrom
> > > > and coreboot.. for example where I must do the command make menuconfig
> > > > and make?
> > >
> > > from buildrom/buildrom-devel/
> > >
> > > if you want to configure coreboot v3
> > > make coreboot-v3-config
> > >
> > > if you want to choose the payload (in your case the linux kernel)
> > > make menuconfig
> > >
> > > Thanks,
> > > Myles
> >
> > I have econtered an error during the compilation.
> > I have make these step:
> > svn co svn://coreboot.org/buildrom
> > svn co svn://coreboot.org/repos/trunk/coreboot-v2
> > cd buildrom/buildrom-devel/
> > make menuconfig
> > make
> >
> > When I run "make" I get the attached error.
> > How I make to understand where is the problem?
> >
> > ...and after the succesfull rom compilation?
> >
> > Thank you in advance, Davide
>
> The build log is buildrom/buildrom-devel/work/coreboot-v2/logs/build.log

I meant coreboot/logs/build.log

I'd bet that the problem is the size of the payload.  How big of a chip do
you have?

Thanks,
Myles

[Davide Visconti]

> > > [...]
> >
> > I have econtered an error during the compilation.
> > I have make these step:
> > svn co svn://coreboot.org/buildrom
> > svn co svn://coreboot.org/repos/trunk/coreboot-v2
> > cd buildrom/buildrom-devel/
> > make menuconfig
> > make
> >
> > When I run "make" I get the attached error.
> > How I make to understand where is the problem?
> >
> > ...and after the succesfull rom compilation?
> >
> > Thank you in advance, Davide
>
> The build log is buildrom/buildrom-devel/work/coreboot-v2/logs/build.log
>
> That's where the real error is.
>
> Thanks,
> Myles

I have see the log file 
"buildrom/buildrom-devel/work/coreboot/logs/build.log" and the size is 
too big.

[...file cut...]
nm -n coreboot | sort > coreboot.map
objcopy --gap-fill 0xff -O binary coreboot coreboot.strip
gcc -o buildrom 
/root/buildrom/buildrom-devel/work/coreboot/svn/util/buildrom/buildrom.c
cp ../payload.elf payload
./buildrom coreboot.strip coreboot.rom payload 0x10000 0x77000
ERROR: payload (1572884) + coreboot (65536) - Size is 1150996 bytes 
larger than ROM size (487424).
make[2]: *** [coreboot.rom] Error 1
make[1]: *** [fallback/coreboot.rom] Error 1

How to set the ROM size?
On the IB520 MoBo I have a 512Kb but in the future I can buy a 2Mb.

[Marc Jones]

Davide Visconti wrote:
> > > > [...]
> > >
> > > I have econtered an error during the compilation.
> > > I have make these step:
> > > svn co svn://coreboot.org/buildrom
> > > svn co svn://coreboot.org/repos/trunk/coreboot-v2
> > > cd buildrom/buildrom-devel/
> > > make menuconfig
> > > make
> > >
> > > When I run "make" I get the attached error.
> > > How I make to understand where is the problem?
> > >
> > > ...and after the succesfull rom compilation?
> > >
> > > Thank you in advance, Davide
> >
> > The build log is buildrom/buildrom-devel/work/coreboot-v2/logs/build.log
> >
> > That's where the real error is.
> >
> > Thanks,
> > Myles
>
> I have see the log file 
> "buildrom/buildrom-devel/work/coreboot/logs/build.log" and the size is 
> too big.
>
> [...file cut...]
> nm -n coreboot | sort > coreboot.map
> objcopy --gap-fill 0xff -O binary coreboot coreboot.strip
> gcc -o buildrom 
> /root/buildrom/buildrom-devel/work/coreboot/svn/util/buildrom/buildrom.c
> cp ../payload.elf payload
> ./buildrom coreboot.strip coreboot.rom payload 0x10000 0x77000
> ERROR: payload (1572884) + coreboot (65536) - Size is 1150996 bytes 
> larger than ROM size (487424).
> make[2]: *** [coreboot.rom] Error 1
> make[1]: *** [fallback/coreboot.rom] Error 1
>
> How to set the ROM size?
> On the IB520 MoBo I have a 512Kb but in the future I can buy a 2Mb.

The ROM size is set in coreboot/targets/company/mainboard/Config.lb

[Davide Visconti]

Hi,
I illustrate to you my step and my doubts:

- I have download only the "buildrom" (no coreboot-v2 !?) with "svn co 
svn://coreboot.org/buildrom"
- Go into buildrom/buildrom-devel/ directory.
- Through "make menuconfig" I have set the "pcengine" and "alix1c" mobo
- After "make menuconfig" I have run "make"... and I get the error.
- That's right, I have change the ROM_SIZE from 512 to 2048 in the file:
./buildrom/buildrom-devel/work/coreboot/svn/targets/pcengines/alix1c/Config.lb
- I have run again the "make" command. Ok It's compiled correctly.

...and now?
Can I download the .rom file into the BIOS chip?
But...the Init process? Who launch it?

and the coreboot-v2?
svn co svn://coreboot.org/repos/trunk/coreboot-v2
I use it for ...?

Thank you in advance.
Davide

[Peter Stuge]

Hi Davide,

Davide Visconti wrote:
> Hi,
> I illustrate to you my step and my doubts:
> I have download only the "buildrom" (no coreboot-v2 !?) with "svn co
>
> svn://coreboot.org/buildrom"
> Go into buildrom/buildrom-devel/ directory.
> Through "make menuconfig" I have set the "pcengine" and "alix1c" mobo
> After "make menuconfig" I have run "make"... and I get the error.
> That's right, I have change the ROM_SIZE from 512 to 2048 in the file:
>
> ./buildrom/buildrom-devel/work/coreboot/svn/targets/pcengines/alix1c/Config.lb
> I have run again the "make" command. Ok It's compiled correctly.
>
> ...and now?
> Can I download the .rom file into the BIOS chip?

Yes, that's right.
> But...the Init process? Who launch it?

If you selected a "Linux kernel payload" then the Linux kernel is
inside the .rom file and will mount root and start init according to
the Kernel command line option in buildrom. You can find these
options in the buildrom menuconfig:

Payload Configuration -> Desired payload -> Linux kernel
and
Payload Configuration -> Desired payload -> Kernel Configuration -> Kernel command line
> and the coreboot-v2?
> svn co svn://coreboot.org/repos/trunk/coreboot-v2
> I use it for ...?

It is not needed when you are using buildrom. buildrom downloads it's
own copy of coreboot during the build process.

//Peter

[Davide Visconti]

> [...]
> > But...the Init process? Who launch it?
>
> If you selected a "Linux kernel payload" then the Linux kernel is
> inside the .rom file and will mount root and start init according to
> the Kernel command line option in buildrom. You can find these
> options in the buildrom menuconfig:
>
> Payload Configuration -> Desired payload -> Linux kernel
> and
> Payload Configuration -> Desired payload -> Kernel Configuration -> Kernel command line

Ok, perfetct!
I have search on the internet but I don't find an example.
If, in a normal grub configuration file I have:

title Ubuntu
root (hd0,0)
kernel /boot/vmlinuz-2.6.20 root=/dev/hda1 ro quiet splash
initrd /boot/initrd.img-2.6.20

I replace this in "Kernel command line" coreboot option with...?
Can you post an example?
...and in my sample grub conf is specified the root (root=/dev/hda1). 
Where is specified in the coreboot? I must pass it always in the "kernel 
command line" option? How?

After the correct point of init process I will have to do a 
modifications on a source of the PcEngine alix1c file config because I 
have another mobo (IB520). It's correct?
...or recovery and try with a alix1c board for verify the correct rom build.

Thank you very much for the help.
If I complete correctly the build, download, etc.. I will write a simple 
pdf howto for the person (like me) that know a lot little the coreboot 
project.

[Davide Visconti]

> > [...]
> > > But...the Init process? Who launch it?
> >
> > If you selected a "Linux kernel payload" then the Linux kernel is
> > inside the .rom file and will mount root and start init according to
> > the Kernel command line option in buildrom. You can find these
> > options in the buildrom menuconfig:
> >
> > Payload Configuration -> Desired payload -> Linux kernel
> > and
> > Payload Configuration -> Desired payload -> Kernel Configuration -> 
> > Kernel command line
>
> Ok, perfetct!
> I have search on the internet but I don't find an example.
> If, in a normal grub configuration file I have:
>
> title Ubuntu
> root (hd0,0)
> kernel /boot/vmlinuz-2.6.20 root=/dev/hda1 ro quiet splash
> initrd /boot/initrd.img-2.6.20
>
> I replace this in "Kernel command line" coreboot option with...?
> Can you post an example?
> ...and in my sample grub conf is specified the root (root=/dev/hda1). 
> Where is specified in the coreboot? I must pass it always in the "kernel 
> command line" option? How?
>
> After the correct point of init process I will have to do a 
> modifications on a source of the PcEngine alix1c file config because I 
> have another mobo (IB520). It's correct?
> ...or recovery and try with a alix1c board for verify the correct rom 
> build.
>
> Thank you very much for the help.
> If I complete correctly the build, download, etc.. I will write a simple 
> pdf howto for the person (like me) that know a lot little the coreboot 
> project.

there isn't anybody that can post me an example?
Thank you in advance.
Davide