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On 05/17/2018 05:21 PM, Banik, Subrata wrote:
Hi Subrata,
Can you please check few more things and please help to clarify some details.
- Is this kind of regression ? because we are not seeing this
issue.
Can't tell that it is first time I try to enable Skylake in coreboot.
- I believe its FSP1.1 selection in Kconfig, please confirm ?
FSP2.0, I'm following Librem Purism options since they seem to boot the same SoC. They use KabyLake FSP obtained by get_blobss.sh [1], if you think this is incorrect then I would like to know why, because it may mean that Pursim code is also incorrect from Intel point of view.
- Please check if BIOS_RESET_CPL is already set prior to setting
0x121 MSR Refer to code enable_bios_reset_cpl
Will do that and get back with result.
As per my debug MSR 0x121 will only through exception if BIOS reset cpl done bits are already set before this call, which shouldn't be the case, otherwise all SKL design might see this issue.
Would be great to know in which document I can read about this MSR.
[1] https://github.com/osresearch/heads/blob/master/blobs/librem_skl/get_blo bs.sh
Best Regards, - -- Piotr Król Embedded Systems Consultant https://3mdeb.com | @3mdeb_com
FSP2.0, I'm following Librem Purism options since they seem to boot the same SoC. They use KabyLake FSP obtained by get_blobss.sh [1], if you think this is incorrect then I would like to know why, because it may mean that Pursim code is also incorrect from Intel point of view.
SKL won't be compatible with KBL FSP. Please don’t try to use KBL FSP and mix match with SKL Coreboot. No one tested that combination.
Thanks, Subrata
-----Original Message----- From: Piotr Król [mailto:piotr.krol@3mdeb.com] Sent: Thursday, May 17, 2018 9:38 PM To: Banik, Subrata subrata.banik@intel.com Cc: coreboot@coreboot.org Subject: Re: Exception on Skylake after enabling ACPI timer emulation
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On 05/17/2018 05:21 PM, Banik, Subrata wrote:
Hi Subrata,
Can you please check few more things and please help to clarify some details.
- Is this kind of regression ? because we are not seeing this issue.
Can't tell that it is first time I try to enable Skylake in coreboot.
- I believe its FSP1.1 selection in Kconfig, please confirm ?
FSP2.0, I'm following Librem Purism options since they seem to boot the same SoC. They use KabyLake FSP obtained by get_blobss.sh [1], if you think this is incorrect then I would like to know why, because it may mean that Pursim code is also incorrect from Intel point of view.
- Please check if BIOS_RESET_CPL is already set prior to setting
0x121 MSR Refer to code enable_bios_reset_cpl
Will do that and get back with result.
As per my debug MSR 0x121 will only through exception if BIOS reset cpl done bits are already set before this call, which shouldn't be the case, otherwise all SKL design might see this issue.
Would be great to know in which document I can read about this MSR.
[1] https://github.com/osresearch/heads/blob/master/blobs/librem_skl/get_blo bs.sh
Best Regards, - -- Piotr Król Embedded Systems Consultant https://3mdeb.com | @3mdeb_com
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On 05/17/2018 06:08 PM, Piotr Król wrote:
Hi Subrata,
- Please check if BIOS_RESET_CPL is already set prior to
setting 0x121 MSR Refer to code enable_bios_reset_cpl
Will do that and get back with result.
BIOS_RESET_CPL was not set before that MSR.
setting it up doesn't help:
Best Regards, - -- Piotr Król Embedded Systems Consultant https://3mdeb.com | @3mdeb_com
-
Banik, Subrata -
Piotr Król