What is the transfer rate and latency of the interface between the CPU and the BIOS socket in motherboards like Via Epia or Tyan Opteron boards?
What I am thinking to do is to put very fast SRAM there (it should work, shouldn't it?), battery backed up of course, and run the LinuxBIOS and kernel XiP eXecute in Place (without copying to RAM). Would that work? Imagine I could put 8 MB of fast SRAM there.
Now, would that make sense, is the interface as fast as the FSB if I have a 200 MHz FSB for example?
If I put some SRAM with random access time below 5 ns in there would it communicate with the CPU faster than DRAM in hte DIMM sockets is? Or at least as fast? With the intention of running it XiP.
Miernik wrote:
What is the transfer rate and latency of the interface between the CPU and the BIOS socket in motherboards like Via Epia or Tyan Opteron boards?
What I am thinking to do is to put very fast SRAM there (it should work, shouldn't it?), battery backed up of course, and run the LinuxBIOS and kernel XiP eXecute in Place (without copying to RAM). Would that work? Imagine I could put 8 MB of fast SRAM there.
won't help. The timing is set by chipset. faster part won't run faster.
I wish it would.
ron
On Tue, Feb 07, 2006 at 03:42:21PM -0700, Ronald G Minnich wrote:
won't help. The timing is set by chipset. faster part won't run faster.
And what is the timing for example chipsets? For VT8601, VT8623 for example? How much slower it is from the timing of RAM? Do some chipsets have it higher then others or is there some kind of common speed which everyone uses? Can't the chipset be "tweaked" to overclock that bus?
Miernik wrote:
And what is the timing for example chipsets?
It really varies. There is no one constant.
For VT8601, VT8623 for example?
These are north, flash is on south, so they are not the issue.
Do some chipsets have it higher then others or is there some kind
of common speed which everyone uses?
There is no common speed. If you have a slow socket, using a faster part won't hurt -- it just runs slow.
ron
Ronald G Minnich rminnich@lanl.gov wrote:
It really varies. There is no one constant.
For VT8601, VT8623 for example?
These are north, flash is on south, so they are not the issue.
The link between North and South, for example the Ultra V-Link in CN400 is 1066 MB/s anyway, so that's the higher limit. DDR400 runs 3200 MB/s so it'll be 3 times slower anyway, no matter what the Southbridge does, if the Northbridge is CN400.
So for example what it is on VT8237 (the speed of connection to flash chip), does anyone have the datasheet?
How is this parameter commonly called in datasheets, so I can google for it? What are the known southbridges with highest speed?
Miernik wrote:
So for example what it is on VT8237 (the speed of connection to flash chip), does anyone have the datasheet?
How is this parameter commonly called in datasheets, so I can google for it? What are the known southbridges with highest speed?
The VT8237 supports LPC flash. The LPC clock is the same speed as the PCI clock, 33MHz.
For more info take a look at the LPC spec: http://www.intel.com/design/chipsets/industry/lpc.htm
-Bari
Bari Ari bari@onelabs.com wrote:
The VT8237 supports LPC flash. The LPC clock is the same speed as the PCI clock, 33MHz.
For more info take a look at the LPC spec: http://www.intel.com/design/chipsets/industry/lpc.htm
33 MHz, 4 bit wide, that gives 16 MB/s theoretical maximum. Not really impressive compared to 1066 MB/s N-S link. 64 times slower. And 192 times slower than DDR400 RAM. Am I right? XiP would be terribly slow :(
Miernik wrote:
Bari Ari bari@onelabs.com wrote:
The VT8237 supports LPC flash. The LPC clock is the same speed as the PCI clock, 33MHz.
For more info take a look at the LPC spec: http://www.intel.com/design/chipsets/industry/lpc.htm
33 MHz, 4 bit wide, that gives 16 MB/s theoretical maximum. Not really impressive compared to 1066 MB/s N-S link. 64 times slower. And 192 times slower than DDR400 RAM. Am I right? XiP would be terribly slow :(
Yes, slow.
I think you misunderstood me. I didn't intend to put SRAM in the DRAM sockets, but in the BIOS chip NOR flash socket. Isn't NOR flash read the same way as SRAM (write is different of course, but I don't care about writes here)?
Would that work?
Even if you had SRAM with matching packages and pinouts to replace the Flash, the read access times would be the same.
The chipset sets the speed of LPC, ISA or FWH interface.
-Bari
Miernik wrote:
What I am thinking to do is to put very fast SRAM there (it should work, shouldn't it?),
No, it won't work. SRAM and DRAM operate very differently and have entirely different interfaces. PC chipset memory controllers do not support SRAM.
battery backed up of course, and run the LinuxBIOS and
kernel XiP eXecute in Place (without copying to RAM). Would that work?
No. See answer above.
Imagine I could put 8 MB of fast SRAM there.
Now, would that make sense, is the interface as fast as the FSB if I have a 200 MHz FSB for example?
If I put some SRAM with random access time below 5 ns in there would it communicate with the CPU faster than DRAM in hte DIMM sockets is? Or at least as fast? With the intention of running it XiP.
The memory controllers drive the speed of the memory bus cycles.
Maybe the confusion here is due to an assumption that all memory controllers and memory devices use SPD (or speed detection algorithims) to detect the memory device speeds. SPD is only used with memory modules, not with Flash or SRAM.
Memory devices have timing specifications that guarantee that the memory device will have stable valid data ready to be read from it or that the memory device can write data sent to it AFTER a certain period has elapsed, after the access cycle has been initiated by the memory controller.
-Bari
Bari Ari bari@onelabs.com wrote:
What I am thinking to do is to put very fast SRAM there (it should work, shouldn't it?),
No, it won't work. SRAM and DRAM operate very differently and have entirely different interfaces. PC chipset memory controllers do not support SRAM.
I think you misunderstood me. I didn't intend to put SRAM in the DRAM sockets, but in the BIOS chip NOR flash socket. Isn't NOR flash read the same way as SRAM (write is different of course, but I don't care about writes here)?
Would that work?
-
Bari Ari -
Miernik -
Ronald G Minnich