On 14.04.2009 17:41, svn@coreboot.org wrote:
Author: cozzie Date: 2009-04-14 17:41:33 +0200 (Tue, 14 Apr 2009) New Revision: 1164
Modified: coreboot-v3/arch/x86/pirq_routing.c coreboot-v3/arch/x86/via/stage0.S coreboot-v3/mainboard/jetway/Kconfig Log: Enable caching for Via C7 CPUs, and also improve readability. Tested on hardware and seems to be working.
Signed-off-by: Corey Osgood corey.osgood@gmail.com Acked-by: Myles Watson mylesgw@gmail.com
Sorry I didn't see the patch earlier.
If (CONFIG_COREBOOT_ROMSIZE_KB + CONFIG_CARSIZE) exceeds L2 cache size, CAR will explode. I bet your test conditions didn't trigger that condition. You can calculate allowed ROM cache size, though. CPUID can tell you L2 size and from that you subtract CARSIZE, then round down to the next power of two.
It seems some unrelated PIRQ change snuck in this changeset.
Regards, Carl-Daniel
Modified: coreboot-v3/arch/x86/pirq_routing.c
--- coreboot-v3/arch/x86/pirq_routing.c 2009-04-14 13:58:45 UTC (rev 1163) +++ coreboot-v3/arch/x86/pirq_routing.c 2009-04-14 15:41:33 UTC (rev 1164) @@ -26,7 +26,7 @@ #include <console.h> #include <device/device.h> #include <tables.h> -#include <pirq_routing.h> +#include <arch/x86/pirq_routing.h>
static void check_pirq_routing_table(struct irq_routing_table *rt) {
Modified: coreboot-v3/arch/x86/via/stage0.S
--- coreboot-v3/arch/x86/via/stage0.S 2009-04-14 13:58:45 UTC (rev 1163) +++ coreboot-v3/arch/x86/via/stage0.S 2009-04-14 15:41:33 UTC (rev 1164) @@ -35,6 +35,11 @@ #define CACHE_RAM_CODE_SEG 0x18 #define CACHE_RAM_DATA_SEG 0x20
+/* Note: disable this only if you want the system to boot REEEEALLY slow for debugging */ +#ifndef CACHE_CBROM +#define CACHE_CBROM +#endif
- .align 4 .globl protected_stage0
protected_stage0: @@ -101,39 +106,37 @@ jmp clear_fixed_var_mtrr clear_fixed_var_mtrr_out: /* MTRRPhysBase */
- movl $0x200, %ecx
movl $(MTRRphysBase_MSR(0)), %ecx xorl %edx, %edx movl $(CacheBase|MTRR_TYPE_WRBACK),%eax wrmsr
/* MTRRPhysMask */
- movl $0x201, %ecx
- movl $(MTRRphysMask_MSR(0)), %ecx /* This assumes we never access addresses above 2^36 in CAR. */ movl $0x0000000f,%edx
- movl $(~(CacheSize-1)|0x800),%eax
- movl $(~(CacheSize-1)|(1<<11)), %eax wrmsr
-#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
/* enable write base caching so we can do execute in place* on the flash rom.*/+#ifdef CACHE_CBROM
- /* enable write base caching. */ /* MTRRPhysBase */
- movl $0x202, %ecx
- movl $(MTRRphysBase_MSR(1)), %ecx xorl %edx, %edx
- movl $(XIP_ROM_BASE|MTRR_TYPE_WRBACK),%eax
movl $((0x100000000 - (CONFIG_COREBOOT_ROMSIZE_KB * 1024))|MTRR_TYPE_WRBACK),%eax wrmsr
/* MTRRPhysMask */
- movl $0x203, %ecx
- movl $(MTRRphysMask_MSR(1)), %ecx movl $0x0000000f,%edx
- movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
- movl $(~((CONFIG_COREBOOT_ROMSIZE_KB * 1024) - 1) | (1<<11)), %eax wrmsr
-#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */ +#endif /* CACHE_CBROM */
movl $MTRRdefType_MSR, %ecx xorl %edx, %edx /* Enable Variable and Fixed MTRRs */
- movl $0x00000800, %eax
movl $(1<<11), %eax wrmsr
/* enable cache */
@@ -153,12 +156,12 @@ xorl %eax, %eax rep stosl
-#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
- /* Read the XIP area */
- movl XIP_ROM_BASE, %esi
- movl $(XIP_ROM_SIZE>>2), %ecx
+#ifdef CACHE_CBROM
- /* Read the ROM area */
- movl (0x100000000 - (CONFIG_COREBOOT_ROMSIZE_KB * 1024)), %esi
- movl $((CONFIG_COREBOOT_ROMSIZE_KB * 1024) >> 2), %ecx rep lodsl
-#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */ +#endif /* CACHE_CBROM */
/* The key point of this CAR code is C7 cache does not turn into * "no fill" mode, which is not compatible with general CAR code.
Modified: coreboot-v3/mainboard/jetway/Kconfig
--- coreboot-v3/mainboard/jetway/Kconfig 2009-04-14 13:58:45 UTC (rev 1163) +++ coreboot-v3/mainboard/jetway/Kconfig 2009-04-14 15:41:33 UTC (rev 1164) @@ -28,7 +28,7 @@ select NORTHBRIDGE_VIA_CN700 select SOUTHBRIDGE_VIA_VT8237 select SUPERIO_FINTEK_F71805F
- select PIRQ_TABLE
+## select PIRQ_TABLE help Jetway J7F2-Series board. endchoice
On Tue, Apr 14, 2009 at 6:16 PM, Carl-Daniel Hailfinger < c-d.hailfinger.devel.2006@gmx.net> wrote:
On 14.04.2009 17:41, svn@coreboot.org wrote:
Author: cozzie Date: 2009-04-14 17:41:33 +0200 (Tue, 14 Apr 2009) New Revision: 1164
Modified: coreboot-v3/arch/x86/pirq_routing.c coreboot-v3/arch/x86/via/stage0.S coreboot-v3/mainboard/jetway/Kconfig Log: Enable caching for Via C7 CPUs, and also improve readability. Tested on
hardware
and seems to be working.
Signed-off-by: Corey Osgood corey.osgood@gmail.com Acked-by: Myles Watson mylesgw@gmail.com
Sorry I didn't see the patch earlier.
If (CONFIG_COREBOOT_ROMSIZE_KB + CONFIG_CARSIZE) exceeds L2 cache size, CAR will explode. I bet your test conditions didn't trigger that condition. You can calculate allowed ROM cache size, though. CPUID can tell you L2 size and from that you subtract CARSIZE, then round down to the next power of two.
Alright, I'll fix it tonight. The bootblock and stage0/1 code should always be at the start of the ROM, right? Is there a chance of explosion if stage0+1 is larger then the cached size?
It seems some unrelated PIRQ change snuck in this changeset.
Sorry about that, I forgot my svn password and I guess in the process I forgot to single out that file when I figured it out. The Kconfig change is needed to build the Jetway target, so I think it should stay, and the pirq_routing.c is simply clarification, the file does actually reside in include/arch/x86/. If anyone wants the latter revert the latter, feel free.
Thanks, Corey
On 15.04.2009 00:26, Corey Osgood wrote:
On Tue, Apr 14, 2009 at 6:16 PM, Carl-Daniel Hailfinger < c-d.hailfinger.devel.2006@gmx.net> wrote:
On 14.04.2009 17:41, svn@coreboot.org wrote:
Author: cozzie Date: 2009-04-14 17:41:33 +0200 (Tue, 14 Apr 2009) New Revision: 1164
Modified: coreboot-v3/arch/x86/pirq_routing.c coreboot-v3/arch/x86/via/stage0.S coreboot-v3/mainboard/jetway/Kconfig Log: Enable caching for Via C7 CPUs, and also improve readability. Tested on
hardware
and seems to be working.
Signed-off-by: Corey Osgood corey.osgood@gmail.com Acked-by: Myles Watson mylesgw@gmail.com
Sorry I didn't see the patch earlier.
If (CONFIG_COREBOOT_ROMSIZE_KB + CONFIG_CARSIZE) exceeds L2 cache size, CAR will explode. I bet your test conditions didn't trigger that condition. You can calculate allowed ROM cache size, though. CPUID can tell you L2 size and from that you subtract CARSIZE, then round down to the next power of two.
Alright, I'll fix it tonight. The bootblock and stage0/1 code should always be at the start of the ROM, right?
The bootblock (stage0+1) will always be at the end of the ROM. Initram is usually at the start of the ROM because the LAR utility always uses the lowest possible address for adding a LAR member, but that can be changed.
For the LAR placement strategy change, look at util/lar/stream.c:lar_add_entry(), specifically the call to lar_empty_offset(). You'll want to create a variant lar_last_empty_offset_for_size() or somesuch.
Is there a chance of explosion if stage0+1 is larger then the cached size?
No, just slowness for some code paths. What you really want for fast bootup is having initram directly before the bootblock at the end (highest address) of the ROM and both of them cached as one contiguous block. That gives you lightning fast startup until MTRRs are reset (but then RAM is available and you can cache the whole ROM).
It seems some unrelated PIRQ change snuck in this changeset.
Sorry about that, I forgot my svn password and I guess in the process I forgot to single out that file when I figured it out. The Kconfig change is needed to build the Jetway target, so I think it should stay, and the pirq_routing.c is simply clarification, the file does actually reside in include/arch/x86/. If anyone wants the latter revert the latter, feel free.
OK with me, I just wanted to clarify.
Regards, Carl-Daniel
-
Carl-Daniel Hailfinger -
Corey Osgood