26 Oct
2009
26 Oct
'09
11:55 a.m.
Hi,
this is an unfinished board I had lying around. CAR and serial output works, but it dies after ram init.
Right now I don't think there is a considerable chance that I can finish it, but here's the patch in case anyone has the time and hardware to look into this.
Stefan
--
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: info@coresystems.de • http://www.coresystems.de/
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Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
preliminary Intel D945GCLF Atom+i945 support.
ram init fails, as the i945 driver currently only supports the mobile version
of the chipset..
Signed-off-by: Stefan Reinauer stepan@coresystems.de
Index: src/superio/smsc/lpc47m15x/lpc47m15x_early_serial.c
===================================================================
--- src/superio/smsc/lpc47m15x/lpc47m15x_early_serial.c (revision 0)
+++ src/superio/smsc/lpc47m15x/lpc47m15x_early_serial.c (revision 0)
@@ -0,0 +1,42 @@
+/*
+ * lpc47m15x_early_serial.c: Pre-RAM driver for SMSC LPC47M15X Super I/O chip
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "lpc47m15x.h"
+
+static inline void pnp_enter_conf_state(device_t dev)
+{
+ unsigned port = dev>>8;
+ outb(0x55, port);
+}
+
+static void pnp_exit_conf_state(device_t dev) {
+ unsigned port = dev>>8;
+ outb(0xaa, port);
+}
+
+static void lpc47b272_enable_serial(device_t dev, unsigned iobase)
+{
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_conf_state(dev);
+}
Index: src/superio/smsc/lpc47m15x/Config.lb
===================================================================
--- src/superio/smsc/lpc47m15x/Config.lb (revision 0)
+++ src/superio/smsc/lpc47m15x/Config.lb (revision 0)
@@ -0,0 +1,2 @@
+config chip.h
+object superio.o
Index: src/superio/smsc/lpc47m15x/superio.c
===================================================================
--- src/superio/smsc/lpc47m15x/superio.c (revision 0)
+++ src/superio/smsc/lpc47m15x/superio.c (revision 0)
@@ -0,0 +1,136 @@
+/*
+ * superio.c: RAM driver for SMSC LPC47M15X Super I/O chip
+ *
+ * (C) 2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console/console.h>
+#include <device/smbus.h>
+#include <string.h>
+#include <bitops.h>
+#include <uart8250.h>
+#include <pc80/keyboard.h>
+#include <stdlib.h>
+#include "chip.h"
+#include "lpc47m15x.h"
+
+// Forward declarations
+static void enable_dev(device_t dev);
+void lpc47m15x_pnp_set_resources(device_t dev);
+void lpc47m15x_pnp_set_resources(device_t dev);
+void lpc47m15x_pnp_enable_resources(device_t dev);
+void lpc47m15x_pnp_enable(device_t dev);
+static void lpc47m15x_init(device_t dev);
+
+static void pnp_enter_conf_state(device_t dev);
+static void pnp_exit_conf_state(device_t dev);
+static void dump_pnp_device(device_t dev);
+
+
+struct chip_operations superio_smsc_lpc47m15x_ops = {
+ CHIP_NAME("SMSC LPC47M15x/192/997 Super I/O")
+ .enable_dev = enable_dev
+};
+
+static struct device_operations ops = {
+ .read_resources = pnp_read_resources,
+ .set_resources = lpc47m15x_pnp_set_resources,
+ .enable_resources = lpc47m15x_pnp_enable_resources,
+ .enable = lpc47m15x_pnp_enable,
+ .init = lpc47m15x_init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ { &ops, LPC47M15X_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+ { &ops, LPC47M15X_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+ { &ops, LPC47M15X_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ { &ops, LPC47M15X_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ { &ops, LPC47M15X_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
+};
+
+static void enable_dev(device_t dev)
+{
+ pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+void lpc47m15x_pnp_set_resources(device_t dev)
+{
+ pnp_enter_conf_state(dev);
+ pnp_set_resources(dev);
+ pnp_exit_conf_state(dev);
+}
+
+void lpc47m15x_pnp_enable_resources(device_t dev)
+{
+ pnp_enter_conf_state(dev);
+ pnp_enable_resources(dev);
+ pnp_exit_conf_state(dev);
+}
+
+void lpc47m15x_pnp_enable(device_t dev)
+{
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+
+ if(dev->enabled) {
+ pnp_set_enable(dev, 1);
+ }
+ else {
+ pnp_set_enable(dev, 0);
+ }
+ pnp_exit_conf_state(dev);
+}
+
+static void lpc47m15x_init(device_t dev)
+{
+ struct superio_smsc_lpc47m15x_config *conf = dev->chip_info;
+ struct resource *res0, *res1;
+
+ if (!dev->enabled)
+ return;
+
+ switch(dev->path.pnp.device) {
+ case LPC47M15X_SP1:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+ init_uart8250(res0->base, &conf->com1);
+ break;
+
+ case LPC47M15X_SP2:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+ init_uart8250(res0->base, &conf->com2);
+ break;
+
+ case LPC47M15X_KBC:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+ res1 = find_resource(dev, PNP_IDX_IO1);
+ pc_keyboard_init(&conf->keyboard);
+ break;
+ }
+}
+
+static void pnp_enter_conf_state(device_t dev)
+{
+ outb(0x55, dev->path.pnp.port);
+}
+
+static void pnp_exit_conf_state(device_t dev)
+{
+ outb(0xaa, dev->path.pnp.port);
+}
+
Index: src/superio/smsc/lpc47m15x/chip.h
===================================================================
--- src/superio/smsc/lpc47m15x/chip.h (revision 0)
+++ src/superio/smsc/lpc47m15x/chip.h (revision 0)
@@ -0,0 +1,10 @@
+struct chip_operations;
+extern struct chip_operations superio_smsc_lpc47m15x_ops;
+
+#include <pc80/keyboard.h>
+#include <uart8250.h>
+
+struct superio_smsc_lpc47m15x_config {
+ struct uart8250 com1, com2;
+ struct pc_keyboard keyboard;
+};
Index: src/superio/smsc/lpc47m15x/lpc47m15x.h
===================================================================
--- src/superio/smsc/lpc47m15x/lpc47m15x.h (revision 0)
+++ src/superio/smsc/lpc47m15x/lpc47m15x.h (revision 0)
@@ -0,0 +1,10 @@
+#define LPC47M15X_FDC 0 /* Floppy */
+#define LPC47M15X_PP 3 /* Parallel Port */
+#define LPC47M15X_SP1 4 /* Com1 */
+#define LPC47M15X_SP2 5 /* Com2 */
+#define LPC47M15X_KBC 7 /* Keyboard & Mouse */
+#define LPC47M15X_GAME 9 /* GAME */
+#define LPC47M15X_PME 10 /* PME reg*/
+#define LPC47M15X_MPU 11 /* MPE -- who knows -- reg*/
+
+#define LPC47M15X2_MAX_CONFIG_REGISTER 0x5F
Index: src/cpu/intel/socket_441/Config.lb
===================================================================
--- src/cpu/intel/socket_441/Config.lb (revision 0)
+++ src/cpu/intel/socket_441/Config.lb (revision 0)
@@ -0,0 +1,3 @@
+config chip.h
+object socket_441.o
+dir /cpu/intel/model_106cx
Index: src/cpu/intel/socket_441/socket_441.c
===================================================================
--- src/cpu/intel/socket_441/socket_441.c (revision 0)
+++ src/cpu/intel/socket_441/socket_441.c (revision 0)
@@ -0,0 +1,7 @@
+#include <device/device.h>
+#include "chip.h"
+
+
+struct chip_operations cpu_intel_socket_441_ops = {
+ CHIP_NAME("Socket 441 CPU")
+};
Index: src/cpu/intel/socket_441/chip.h
===================================================================
--- src/cpu/intel/socket_441/chip.h (revision 0)
+++ src/cpu/intel/socket_441/chip.h (revision 0)
@@ -0,0 +1,4 @@
+extern struct chip_operations cpu_intel_socket_441_ops;
+
+struct cpu_intel_socket_441_config {
+};
Index: src/cpu/intel/model_106cx/Config.lb
===================================================================
--- src/cpu/intel/model_106cx/Config.lb (revision 0)
+++ src/cpu/intel/model_106cx/Config.lb (revision 0)
@@ -0,0 +1,14 @@
+uses CONFIG_HAVE_MOVNTI
+default CONFIG_HAVE_MOVNTI=1
+
+dir /cpu/x86/tsc
+dir /cpu/x86/mtrr
+dir /cpu/x86/fpu
+dir /cpu/x86/sse
+dir /cpu/x86/lapic
+dir /cpu/x86/cache
+dir /cpu/x86/smm
+dir /cpu/intel/microcode
+dir /cpu/intel/hyperthreading
+dir /cpu/intel/speedstep
+driver model_6cx_init.o
Index: src/cpu/intel/model_106cx/model_6cx_init.c
===================================================================
--- src/cpu/intel/model_106cx/model_6cx_init.c (revision 0)
+++ src/cpu/intel/model_106cx/model_6cx_init.c (revision 0)
@@ -0,0 +1,226 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/intel/microcode.h>
+#include <cpu/intel/hyperthreading.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/mtrr.h>
+#include <usbdebug_direct.h>
+
+static const uint32_t microcode_updates[] = {
+ /* Dummy terminator */
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+};
+
+static inline void strcpy(char *dst, char *src)
+{
+ while (*src) *dst++ = *src++;
+}
+
+static void fill_processor_name(char *processor_name)
+{
+ struct cpuid_result regs;
+ char temp_processor_name[49];
+ char *processor_name_start;
+ unsigned int *name_as_ints = (unsigned int *)temp_processor_name;
+ int i;
+
+ for (i=0; i<3; i++) {
+ regs = cpuid(0x80000002 + i);
+ name_as_ints[i*4 + 0] = regs.eax;
+ name_as_ints[i*4 + 1] = regs.ebx;
+ name_as_ints[i*4 + 2] = regs.ecx;
+ name_as_ints[i*4 + 3] = regs.edx;
+ }
+
+ temp_processor_name[48] = 0;
+
+ /* Skip leading spaces */
+ processor_name_start = temp_processor_name;
+ while (*processor_name_start == ' ')
+ processor_name_start++;
+
+ memset(processor_name, 0, 49);
+ strcpy(processor_name, processor_name_start);
+}
+
+#define IA32_FEATURE_CONTROL 0x003a
+
+#define CPUID_VMX (1 << 5)
+#define CPUID_SMX (1 << 6)
+static void enable_vmx(void)
+{
+ struct cpuid_result regs;
+ msr_t msr;
+
+ msr = rdmsr(IA32_FEATURE_CONTROL);
+
+ if (msr.lo & (1 << 0)) {
+ /* VMX locked. If we set it again we get an illegal
+ * instruction
+ */
+ return;
+ }
+
+ regs = cpuid(1);
+ if (regs.ecx & CPUID_VMX) {
+ msr.lo |= (1 << 2);
+ if (regs.ecx & CPUID_SMX)
+ msr.lo |= (1 << 1);
+ }
+
+ wrmsr(IA32_FEATURE_CONTROL, msr);
+
+ msr.lo |= (1 << 0); /* Set lock bit */
+
+ wrmsr(IA32_FEATURE_CONTROL, msr);
+}
+
+#define PMG_CST_CONFIG_CONTROL 0xe2
+#define PMG_IO_BASE_ADDR 0xe3
+#define PMG_IO_CAPTURE_ADDR 0xe4
+#define PMB0 0x510 /* analogous to P_BLK in cpu.asl */
+#define PMB1 0x0 /* IO port that triggers SMI once cores are in the same state.
+ See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4] */
+#define HIGHEST_CLEVEL 3
+static void configure_c_states(void)
+{
+ msr_t msr;
+
+ msr = rdmsr(PMG_CST_CONFIG_CONTROL);
+ msr.lo |= (1 << 15); // Lock configuration
+ msr.lo |= (1 << 10); // redirect IO-based CState transition requests to MWAIT
+ msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk
+ msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3
+ // TODO Do we want Deep C4 and Dynamic L2 shrinking?
+ wrmsr(PMG_CST_CONFIG_CONTROL, msr);
+
+ // set P_BLK address
+ msr = rdmsr(PMG_IO_BASE_ADDR);
+ msr.lo = (PMB0 + 4) | (PMB1 << 16);
+ wrmsr(PMG_IO_BASE_ADDR, msr);
+
+ // set C_LVL controls
+ msr = rdmsr(PMG_IO_CAPTURE_ADDR);
+ msr.lo = (PMB0 + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted
+ wrmsr(PMG_IO_CAPTURE_ADDR, msr);
+}
+
+#define IA32_MISC_ENABLE 0x1a0
+static void configure_misc(void)
+{
+ msr_t msr;
+
+ msr = rdmsr(IA32_MISC_ENABLE);
+ msr.lo |= (1 << 3); /* TM1 enable */
+ msr.lo |= (1 << 13); /* TM2 enable */
+ msr.lo |= (1 << 17); /* Bidirectional PROCHOT# */
+
+ msr.lo |= (1 << 10); /* FERR# multiplexing */
+
+ // TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1
+ msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
+
+ // TODO Do we want Deep C4 and Dynamic L2 shrinking?
+ wrmsr(IA32_MISC_ENABLE, msr);
+
+ msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */
+ wrmsr(IA32_MISC_ENABLE, msr);
+}
+
+#if CONFIG_USBDEBUG_DIRECT
+static unsigned ehci_debug_addr;
+#endif
+
+static void model_6ex_init(device_t cpu)
+{
+ char processor_name[49];
+
+ /* Turn on caching if we haven't already */
+ x86_enable_cache();
+
+ /* Update the microcode */
+ intel_update_microcode(microcode_updates);
+
+ /* Print processor name */
+ fill_processor_name(processor_name);
+ printk_info("CPU: %s.\n", processor_name);
+
+#if CONFIG_USBDEBUG_DIRECT
+ // Is this caution really needed?
+ if(!ehci_debug_addr)
+ ehci_debug_addr = get_ehci_debug();
+ set_ehci_debug(0);
+#endif
+
+ /* Setup MTRRs */
+ x86_setup_mtrrs(36);
+ x86_mtrr_check();
+
+#if CONFIG_USBDEBUG_DIRECT
+ set_ehci_debug(ehci_debug_addr);
+#endif
+
+ /* Enable the local cpu apics */
+ setup_lapic();
+
+ /* Enable virtualization */
+ enable_vmx();
+
+ /* Configure C States */
+ configure_c_states();
+
+ /* Configure Enhanced SpeedStep and Thermal Sensors */
+ configure_misc();
+
+ /* TODO: PIC thermal sensor control */
+
+ /* Start up my cpu siblings */
+ intel_sibling_init(cpu);
+}
+
+static struct device_operations cpu_dev_ops = {
+ .init = model_6ex_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+ { X86_VENDOR_INTEL, 0x06e0 }, /* Intel Core Solo/Core Duo */
+ { X86_VENDOR_INTEL, 0x06e8 }, /* Intel Core Solo/Core Duo */
+ { X86_VENDOR_INTEL, 0x06ec }, /* Intel Core Solo/Core Duo */
+ { 0, 0 },
+};
+
+static const struct cpu_driver driver __cpu_driver = {
+ .ops = &cpu_dev_ops,
+ .id_table = cpu_table,
+};
+
Index: src/cpu/intel/model_106cx/cache_as_ram_disable.c
===================================================================
--- src/cpu/intel/model_106cx/cache_as_ram_disable.c (revision 0)
+++ src/cpu/intel/model_106cx/cache_as_ram_disable.c (revision 0)
@@ -0,0 +1,116 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include "cpu/x86/car/copy_and_run.c"
+
+void real_main(unsigned long bist);
+
+void stage1_main(unsigned long bist)
+{
+ unsigned int cpu_reset = 0;
+
+#if CONFIG_USE_FALLBACK_IMAGE == 1
+ /* Is this a deliberate reset by the bios */
+ if (bios_reset_detected() && last_boot_normal()) {
+ goto normal_image;
+ } else {
+ /* This is the primary cpu how should I boot? */
+ check_cmos_failed();
+ if (do_normal_boot()) {
+ goto normal_image;
+ }
+ else {
+ goto fallback_image;
+ }
+ }
+ normal_image:
+ __asm__ volatile ("jmp __normal_image"
+ : /* outputs */
+ : "a" (bist) /* inputs */
+ );
+ fallback_image:
+#endif
+
+ real_main(bist);
+
+ /* No servicable parts below this line .. */
+
+ {
+ /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
+ unsigned v_esp;
+ __asm__ volatile (
+ "movl %%esp, %0\n\t"
+ : "=a" (v_esp)
+ );
+ printk_spew("v_esp=%08x\r\n", v_esp);
+ }
+
+cpu_reset_x:
+
+ printk_spew("cpu_reset = %08x\r\n",cpu_reset);
+
+ if(cpu_reset == 0) {
+ print_spew("Clearing initial memory region: ");
+ }
+ print_spew("No cache as ram now - ");
+
+ /* store cpu_reset to ebx */
+ __asm__ volatile (
+ "movl %0, %%ebx\n\t"
+ ::"a" (cpu_reset)
+ );
+
+ if(cpu_reset==0) {
+#define CLEAR_FIRST_1M_RAM 1
+#include "cache_as_ram_post.c"
+ } else {
+#undef CLEAR_FIRST_1M_RAM
+#include "cache_as_ram_post.c"
+ }
+
+ __asm__ volatile (
+ /* set new esp */ /* before _RAMBASE */
+ "subl %0, %%ebp\n\t"
+ "subl %0, %%esp\n\t"
+ ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- CONFIG_RAMBASE )
+ );
+
+ {
+ unsigned new_cpu_reset;
+
+ /* get back cpu_reset from ebx */
+ __asm__ volatile (
+ "movl %%ebx, %0\n\t"
+ :"=a" (new_cpu_reset)
+ );
+
+#ifdef CONFIG_DEACTIVATE_CAR
+ print_debug("Deactivating CAR");
+#include CONFIG_DEACTIVATE_CAR_FILE
+ print_debug(" - Done.\r\n");
+#endif
+ /* Copy and execute coreboot_ram */
+ copy_and_run(new_cpu_reset);
+ /* We will not return */
+ }
+
+ print_debug("sorry. parachute did not open.\r\n");
+}
Index: src/cpu/intel/model_106cx/cache_as_ram_post.c
===================================================================
--- src/cpu/intel/model_106cx/cache_as_ram_post.c (revision 0)
+++ src/cpu/intel/model_106cx/cache_as_ram_post.c (revision 0)
@@ -0,0 +1,125 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+ __asm__ volatile (
+
+ "movb $0x30, %al\noutb %al, $0x80\n"
+
+ /* Disable Cache */
+ "movl %cr0, %eax\n"
+ "orl $(1 << 30), %eax\n"
+ "movl %eax, %cr0\n"
+
+ "movb $0x31, %al\noutb %al, $0x80\n"
+
+ /* Disable MTRR */
+ "movl $MTRRdefType_MSR, %ecx\n"
+ "rdmsr\n"
+ "andl $(~(1 << 11)), %eax\n"
+ "wrmsr\n"
+
+ "movb $0x32, %al\noutb %al, $0x80\n"
+
+ "invd\n"
+#if 0
+ "xorl %eax, %eax\n"
+ "xorl %edx, %edx\n"
+ "movl $MTRRphysBase_MSR(0), %ecx\n"
+ "wrmsr\n"
+ "movl $MTRRphysMask_MSR(0), %ecx\n"
+ "wrmsr\n"
+ "movl $MTRRphysBase_MSR(1), %ecx\n"
+ "wrmsr\n"
+ "movl $MTRRphysMask_MSR(1), %ecx\n"
+ "wrmsr\n"
+#endif
+
+ "movb $0x33, %al\noutb %al, $0x80\n"
+#ifdef CLEAR_FIRST_1M_RAM
+ "movb $0x34, %al\noutb %al, $0x80\n"
+ /* Enable Write Combining and Speculative Reads for the first 1MB */
+ "movl $MTRRphysBase_MSR(0), %ecx\n"
+ "movl $(0x00000000 | MTRR_TYPE_WRCOMB), %eax\n"
+ "xorl %edx, %edx\n"
+ "wrmsr\n"
+ "movl $MTRRphysMask_MSR(0), %ecx\n"
+ "movl $(~(1024*1024 -1) | (1 << 11)), %eax\n"
+ "movl $0x0000000f, %edx\n" // 36bit address space
+ "wrmsr\n"
+ "movb $0x35, %al\noutb %al, $0x80\n"
+#endif
+
+ /* Enable Cache */
+ "movl %cr0, %eax\n"
+ "andl $~( (1 << 30) | (1 << 29) ), %eax\n"
+ "movl %eax, %cr0\n"
+
+ "movb $0x36, %al\noutb %al, $0x80\n"
+#ifdef CLEAR_FIRST_1M_RAM
+
+ /* Clear first 1MB of RAM */
+ "movl $0x00000000, %edi\n"
+ "cld\n"
+ "xorl %eax, %eax\n"
+ "movl $((1024*1024) / 4), %ecx\n"
+ "rep stosl\n"
+
+ "movb $0x37, %al\noutb %al, $0x80\n"
+#endif
+
+ /* Disable Cache */
+ "movl %cr0, %eax\n"
+ "orl $(1 << 30), %eax\n"
+ "movl %eax, %cr0\n"
+
+ "movb $0x38, %al\noutb %al, $0x80\n"
+
+ /* Enable Write Back and Speculative Reads for the first 1MB */
+ "movl $MTRRphysBase_MSR(0), %ecx\n"
+ "movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax\n"
+ "xorl %edx, %edx\n"
+ "wrmsr\n"
+ "movl $MTRRphysMask_MSR(0), %ecx\n"
+ "movl $(~(1024*1024 -1) | (1 << 11)), %eax\n"
+ "movl $0x0000000f, %edx\n" // 36bit address space
+ "wrmsr\n"
+
+ "movb $0x39, %al\noutb %al, $0x80\n"
+
+ /* And Enable Cache again after setting MTRRs */
+ "movl %cr0, %eax\n"
+ "andl $~( (1 << 30) | (1 << 29) ), %eax\n"
+ "movl %eax, %cr0\n"
+
+ "movb $0x3a, %al\noutb %al, $0x80\n"
+
+ /* Enable MTRR */
+ "movl $MTRRdefType_MSR, %ecx\n"
+ "rdmsr\n"
+ "orl $(1 << 11), %eax\n"
+ "wrmsr\n"
+
+ "movb $0x3b, %al\noutb %al, $0x80\n"
+
+ /* Invalidate the cache again */
+ "invd\n"
+ "movb $0x3c, %al\noutb %al, $0x80\n"
+ );
Index: src/cpu/intel/model_106cx/cache_as_ram.inc
===================================================================
--- src/cpu/intel/model_106cx/cache_as_ram.inc (revision 0)
+++ src/cpu/intel/model_106cx/cache_as_ram.inc (revision 0)
@@ -0,0 +1,165 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000,2007 Ronald G. Minnich rminnich@gmail.com
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
+#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
+#define post_code(x) intel_chip_post_macro(x)
+
+#include <cpu/x86/mtrr.h>
+#include <cpu/amd/mtrr.h>
+
+ /* Save the BIST result */
+ movl %eax, %ebp
+
+cache_as_ram:
+#if CONFIG_USE_FALLBACK_IMAGE == 1
+
+ post_code(0x20)
+
+ /* Send INIT IPI to all excluding ourself */
+ movl $0x000C4500, %eax
+ movl $0xFEE00300, %esi
+ movl %eax, (%esi)
+
+ post_code(0x21)
+
+ /* Zero out all Fixed Range and Variable Range MTRRs */
+ movl $mtrr_table, %esi
+ movl $( (mtrr_table_end - mtrr_table) / 2), %edi
+ xorl %eax, %eax
+ xorl %edx, %edx
+clear_mtrrs:
+ movw (%esi), %bx
+ movzx %bx, %ecx
+ wrmsr
+ add $2, %esi
+ dec %edi
+ jnz clear_mtrrs
+ post_code(0x22)
+
+ /* Configure the default memory type to uncacheable */
+ movl $MTRRdefType_MSR, %ecx
+ rdmsr
+ andl $(~0x00000cff), %eax
+ wrmsr
+
+ post_code(0x23)
+ /* Set cache as ram base address */
+ movl $(MTRRphysBase_MSR(0)), %ecx
+ movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
+ xorl %edx, %edx
+ wrmsr
+
+ post_code(0x24)
+ /* Set cache as ram mask */
+ movl $(MTRRphysMask_MSR(0)), %ecx
+ movl $(~((CACHE_AS_RAM_SIZE-1)) | (1 << 11)), %eax
+ movl $0x00000000, %edx
+ wrmsr
+
+ post_code(0x25)
+ /* Enable MTRR */
+ movl $MTRRdefType_MSR, %ecx
+ rdmsr
+ orl $(1 << 11), %eax
+ wrmsr
+
+ post_code(0x26)
+ /* Enable L2 Cache */
+ movl $0x11e, %ecx
+ rdmsr
+ orl $(1 << 8), %eax
+ wrmsr
+
+ post_code(0x27)
+ /* CR0.CD = 0, CR0.NW = 0 */
+ movl %cr0, %eax
+ andl $( ~( (1 << 30) | (1 << 29) ) ), %eax
+ invd
+ movl %eax, %cr0
+
+ post_code(0x28)
+ /* Clear the cache memory reagion */
+ movl $CACHE_AS_RAM_BASE, %esi
+ movl %esi, %edi
+ movl $(CACHE_AS_RAM_SIZE / 4), %ecx
+ //movl $0x23322332, %eax
+ xorl %eax, %eax
+ rep stosl
+#endif
+
+ post_code(0x29)
+ /* Enable Cache As RAM mode by disabling cache */
+ movl %cr0, %eax
+ orl $(1 << 30), %eax
+ movl %eax, %cr0
+
+#if 0
+#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
+ /* Enable cache for our code in Flash because we do CONFIG_XIP here */
+ movl $MTRRphysBase_MSR(1), %ecx
+ xorl %edx, %edx
+ movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+ wrmsr
+
+ movl $MTRRphysMask_MSR(1), %ecx
+ movl $0x0000000f, %edx
+ movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
+ wrmsr
+#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
+#endif
+
+ post_code(0x2a)
+ /* enable cache */
+ movl %cr0, %eax
+ andl $( ~( (1 << 30) | (1 << 29) ) ), %eax
+ movl %eax, %cr0
+
+ /* Set up stack pointer */
+ movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax
+ movl %eax, %esp
+
+ /* Restore the BIST result */
+ movl %ebp, %eax
+ movl %esp, %ebp
+ pushl %eax
+
+ post_code(0x23)
+
+ call stage1_main
+
+ post_code(0x2f)
+error:
+ hlt
+ jmp error
+
+mtrr_table:
+ /* Fixed MTRRs */
+ .word 0x250, 0x258, 0x259
+ .word 0x268, 0x269, 0x26A
+ .word 0x26B, 0x26C, 0x26D
+ .word 0x26E, 0x26F
+ /* Variable MTRRs */
+ .word 0x200, 0x201, 0x202, 0x203
+ .word 0x204, 0x205, 0x206, 0x207
+ .word 0x208, 0x209, 0x20A, 0x20B
+ .word 0x20C, 0x20D, 0x20E, 0x20F
+mtrr_table_end:
+
Index: src/mainboard/intel/Kconfig
===================================================================
--- src/mainboard/intel/Kconfig (revision 4861)
+++ src/mainboard/intel/Kconfig (working copy)
@@ -2,6 +2,7 @@
prompt "Mainboard model"
depends on VENDOR_INTEL
+source "src/mainboard/intel/d945gclf/Kconfig"
source "src/mainboard/intel/eagleheights/Kconfig"
source "src/mainboard/intel/jarrell/Kconfig"
source "src/mainboard/intel/mtarvon/Kconfig"
Index: src/mainboard/intel/d945gclf/Kconfig
===================================================================
--- src/mainboard/intel/d945gclf/Kconfig (revision 0)
+++ src/mainboard/intel/d945gclf/Kconfig (revision 0)
@@ -0,0 +1,62 @@
+config BOARD_INTEL_D945GCLF
+ bool "D945GCLF"
+ select ARCH_X86
+ select CPU_INTEL_CORE
+ select CPU_INTEL_SOCKET_MFCPGA478
+ select NORTHBRIDGE_INTEL_I945
+ select SOUTHBRIDGE_INTEL_I82801GX
+ select SUPERIO_WINBOND_W83627THG
+ select HAVE_PIRQ_TABLE
+ select HAVE_MP_TABLE
+ select MMCONF_SUPPORT
+ select USE_PRINTK_IN_CAR
+ select AP_IN_SIPI_WAIT
+ select UDELAY_LAPIC
+ select HAVE_ACPI_TABLES
+ select HAVE_SMI_HANDLER
+ select BOARD_ROMSIZE_KB_1024
+
+config MAINBOARD_DIR
+ string
+ default intel/d945gclf
+ depends on BOARD_INTEL_D945GCLF
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xffdf8000
+ depends on BOARD_INTEL_D945GCLF
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x8000
+ depends on BOARD_INTEL_D945GCLF
+
+config LB_CKS_RANGE_END
+ int
+ default 122
+ depends on BOARD_INTEL_D945GCLF
+
+config LB_CKS_LOC
+ int
+ default 123
+ depends on BOARD_INTEL_D945GCLF
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "D945GCLF"
+ depends on BOARD_INTEL_D945GCLF
+
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xf0000000
+ depends on BOARD_INTEL_D945GCLF
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+ depends on BOARD_INTEL_D945GCLF
+
+config MAX_PHYSICAL_CPUS
+ int
+ default 2
+ depends on BOARD_INTEL_D945GCLF
Index: src/mainboard/intel/d945gclf/Makefile.inc
===================================================================
--- src/mainboard/intel/d945gclf/Makefile.inc (revision 0)
+++ src/mainboard/intel/d945gclf/Makefile.inc (revision 0)
@@ -0,0 +1,70 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+##
+## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
+##
+
+driver-y += mainboard.o
+driver-y += rtl8168.o
+
+#obj-y += ../../../southbridge/intel/i82801gx/i82801gx_reset.c
+obj-$(CONFIG_GENERATE_MP_TABLE) += mptable.o
+obj-$(CONFIG_GENERATE_PIRQ_TABLE) += irq_tables.o
+obj-$(CONFIG_GENERATE_ACPI_TABLES) += dsdt.o
+obj-$(CONFIG_GENERATE_ACPI_TABLES) += acpi_tables.o
+obj-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.o
+
+smmobj-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.o
+
+# This is part of the conversion to init-obj and away from included code.
+
+initobj-y += crt0.o
+# FIXME in $(top)/Makefile
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += ../../../../src/cpu/intel/model_6ex/cache_as_ram.inc
+crt0-y += auto.inc
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+
+ifdef POST_EVALUATION
+
+$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+ iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+ mv dsdt.hex $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
+ $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h
+ $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@
+ perl -e 's/.rodata/.rom.data/g' -pi $@
+ perl -e 's/.text/.section .rom.text/g' -pi $@
+
+endif
+
Index: src/mainboard/intel/d945gclf/mainboard_smi.c
===================================================================
--- src/mainboard/intel/d945gclf/mainboard_smi.c (revision 0)
+++ src/mainboard/intel/d945gclf/mainboard_smi.c (revision 0)
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include "../../../southbridge/intel/i82801gx/i82801gx_nvs.h"
+
+/* The southbridge SMI handler checks whether gnvs has a
+ * valid pointer before calling the trap handler
+ */
+extern global_nvs_t *gnvs;
+
+int mainboard_io_trap_handler(int smif)
+{
+ switch (smif) {
+ case 0x99:
+ printk_debug("Sample\n");
+ gnvs->smif = 0;
+ break;
+ default:
+ return 0;
+ }
+
+ /* On success, the IO Trap Handler returns 0
+ * On failure, the IO Trap Handler returns a value != 0
+ *
+ * For now, we force the return value to 0 and log all traps to
+ * see what's going on.
+ */
+ //gnvs->smif = 0;
+ return 1;
+}
+
+
Index: src/mainboard/intel/d945gclf/Options.lb
===================================================================
--- src/mainboard/intel/d945gclf/Options.lb (revision 0)
+++ src/mainboard/intel/d945gclf/Options.lb (revision 0)
@@ -0,0 +1,331 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+# Tables
+uses CONFIG_GENERATE_MP_TABLE
+uses CONFIG_GENERATE_PIRQ_TABLE
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_GENERATE_ACPI_TABLES
+uses CONFIG_HAVE_ACPI_RESUME
+uses CONFIG_HAVE_MAINBOARD_RESOURCES
+# SMP
+uses CONFIG_SMP
+uses CONFIG_LOGICAL_CPUS
+uses CONFIG_AP_IN_SIPI_WAIT
+uses CONFIG_MAX_CPUS
+uses CONFIG_MAX_PHYSICAL_CPUS
+uses CONFIG_IOAPIC
+# Image Size
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
+# Payload
+uses CONFIG_ROM_PAYLOAD
+uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses CONFIG_PRECOMPRESSED_PAYLOAD
+# Build Internals
+uses CONFIG_RAMBASE
+uses CONFIG_ROMBASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
+uses CONFIG_USE_INIT
+uses CONFIG_USE_PRINTK_IN_CAR
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_SMI_HANDLER
+uses CONFIG_PCIE_CONFIGSPACE_HOLE
+uses CONFIG_MMCONF_SUPPORT
+uses CONFIG_MMCONF_BASE_ADDRESS
+uses CONFIG_GFXUMA
+
+#
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+# Timers
+uses CONFIG_UDELAY_LAPIC
+# Console
+uses CONFIG_CONSOLE_SERIAL8250
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_VGA_ROM_RUN
+uses CONFIG_PCI_ROM_RUN
+uses CONFIG_DEBUG
+# Toolchain
+uses CC
+uses HOSTCC
+uses CONFIG_CROSS_COMPILE
+uses CONFIG_OBJCOPY
+# Tweaks
+uses CONFIG_GDB_STUB
+uses CONFIG_MAX_REBOOT_CNT
+uses CONFIG_USE_WATCHDOG_ON_BOOT
+uses COREBOOT_EXTRA_VERSION
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+
+###
+### Build options
+###
+
+##
+##
+default CONFIG_MAX_REBOOT_CNT=3
+
+##
+## Use the watchdog to break out of a lockup condition
+##
+default CONFIG_USE_WATCHDOG_ON_BOOT=0
+
+##
+## ROM_SIZE is the size of boot ROM that this board will use.
+##
+default CONFIG_ROM_SIZE=CONFIG_FALLBACK_SIZE*2
+
+
+##
+## Build code for the fallback boot
+##
+default CONFIG_HAVE_FALLBACK_BOOT=1
+
+##
+## Delay timer options
+##
+default CONFIG_UDELAY_LAPIC=1
+
+##
+## Build code to reset the motherboard from coreboot
+##
+default CONFIG_HAVE_HARD_RESET=1
+
+##
+## Build SMI handler
+##
+default CONFIG_HAVE_SMI_HANDLER=1
+
+##
+## Leave a hole for mmapped PCIe config space
+##
+
+default CONFIG_PCIE_CONFIGSPACE_HOLE=1
+default CONFIG_MMCONF_SUPPORT=1
+default CONFIG_MMCONF_BASE_ADDRESS=0xf0000000
+
+##
+## UMA
+##
+default CONFIG_GFXUMA=1
+
+##
+## Build code to export a programmable irq routing table
+##
+default CONFIG_GENERATE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=18
+
+##
+## Build code to export an x86 MP table
+## Useful for specifying IRQ routing values
+##
+default CONFIG_GENERATE_MP_TABLE=1
+
+##
+## Build code to provide ACPI support
+##
+default CONFIG_GENERATE_ACPI_TABLES=1
+default CONFIG_HAVE_MAINBOARD_RESOURCES=1
+default CONFIG_HAVE_ACPI_RESUME=1
+
+##
+## Build code to export a CMOS option table
+##
+default CONFIG_HAVE_OPTION_TABLE=1
+
+##
+## Move the default CONFIG_coreboot cmos range off of AMD RTC registers
+##
+default CONFIG_LB_CKS_RANGE_START=49
+default CONFIG_LB_CKS_RANGE_END=122
+default CONFIG_LB_CKS_LOC=123
+
+#VGA Console
+default CONFIG_CONSOLE_VGA=1
+# There are some network option roms that don't work with
+# coreboot's x86emu. Thus, we only execute the VGA option rom
+# for now:
+default CONFIG_VGA_ROM_RUN=1
+default CONFIG_PCI_ROM_RUN=0
+default CONFIG_DEBUG=0
+
+##
+## Build code for SMP support
+## Only worry about 2 micro processors
+##
+default CONFIG_SMP=1
+default CONFIG_MAX_CPUS=4
+default CONFIG_MAX_PHYSICAL_CPUS=2
+default CONFIG_LOGICAL_CPUS=1
+default CONFIG_AP_IN_SIPI_WAIT=1
+
+##
+## enable CACHE_AS_RAM specifics
+##
+default CONFIG_USE_DCACHE_RAM=1
+default CONFIG_DCACHE_RAM_SIZE=0x8000
+default CONFIG_DCACHE_RAM_BASE=0xffed8000
+default CONFIG_USE_PRINTK_IN_CAR=1
+
+##
+## Execute In Place settings
+##
+
+default CONFIG_XIP_ROM_SIZE = 128 * 1024
+default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE )
+
+##
+## Build code to setup a generic IOAPIC
+##
+default CONFIG_IOAPIC=1
+
+##
+## Clean up the motherboard id strings
+##
+default CONFIG_MAINBOARD_PART_NUMBER="D945GCLF"
+default CONFIG_MAINBOARD_VENDOR= "INTEL"
+
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x464c
+
+###
+### coreboot layout values
+###
+
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 0xb800
+
+##
+## Use a small 8K stack
+##
+default CONFIG_STACK_SIZE=0x2000
+
+##
+## Use a small 32K heap
+##
+default CONFIG_HEAP_SIZE=0x8000
+
+
+###
+### Compute the location and size of where this firmware image
+### (coreboot plus bootloader) will live in the boot rom chip.
+###
+default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE
+
+##
+## coreboot C code runs at this location in RAM
+##
+default CONFIG_RAMBASE=0x00100000
+
+##
+## Load the payload from the ROM
+##
+default CONFIG_ROM_PAYLOAD=1
+
+###
+### Defaults of options that you may want to override in the target config file
+###
+
+##
+## The default compiler
+##
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
+
+##
+## Disable the gdb stub by default
+##
+default CONFIG_GDB_STUB=0
+
+##
+## The Serial Console
+##
+
+# To Enable the Serial Console
+default CONFIG_CONSOLE_SERIAL8250=1
+
+## Select the serial console baud rate
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
+
+# Select the serial console base port
+default CONFIG_TTYS0_BASE=0x3f8
+
+# Select the serial protocol
+# This defaults to 8 data bits, 1 stop bit, and no parity
+default CONFIG_TTYS0_LCS=0x3
+
+##
+### Select the coreboot loglevel
+##
+## EMERG 1 system is unusable
+## ALERT 2 action must be taken immediately
+## CRIT 3 critical conditions
+## ERR 4 error conditions
+## WARNING 5 warning conditions
+## NOTICE 6 normal but significant condition
+## INFO 7 informational
+## DEBUG 8 debug-level messages
+## SPEW 9 Way too many details
+
+## Request this level of debugging output
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5
+## At a maximum only compile in this level of debugging
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
+
+##
+## Select power on after power fail setting
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+
+### End Options.lb
+end
Index: src/mainboard/intel/d945gclf/acpi_tables.c
===================================================================
--- src/mainboard/intel/d945gclf/acpi_tables.c (revision 0)
+++ src/mainboard/intel/d945gclf/acpi_tables.c (revision 0)
@@ -0,0 +1,360 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include "dmi.h"
+
+#define OLD_ACPI 0
+
+extern unsigned char AmlCode[];
+#if CONFIG_HAVE_ACPI_SLIC
+unsigned long acpi_create_slic(unsigned long current);
+#endif
+void generate_cpu_entries(void); // from cpu/intel/speedstep
+unsigned long acpi_fill_mcfg(unsigned long current); // from northbridge/intel/i945
+
+#if OLD_ACPI
+typedef struct acpi_oemb {
+ acpi_header_t header;
+ u8 ss;
+ u16 iost;
+ u32 topm;
+ u32 roms;
+ u32 mg1b;
+ u32 mg1l;
+ u32 mg2b;
+ u32 mg2l;
+ u8 rsvd;
+ u8 dmax;
+ u32 hpta;
+ u32 cpb0;
+ u32 cpb1;
+ u32 cpb2;
+ u32 cpb3;
+ u8 assb;
+ u8 aotb;
+ u32 aaxb;
+ u8 smif;
+ u8 dtse;
+ u8 dts1;
+ u8 dts2;
+ u8 mpen;
+} __attribute__((packed)) acpi_oemb_t;
+#endif
+
+typedef struct acpi_gnvs {
+ // 0x00
+ u16 osys;
+ u8 smif;
+ u8 reserved[13];
+ // 0x10
+ u8 mpen;
+} __attribute__((packed)) acpi_gnvs_t;
+
+#if OLD_ACPI
+void acpi_create_oemb(acpi_oemb_t *oemb)
+{
+ acpi_header_t *header = &(oemb->header);
+ unsigned long tolud;
+
+ memset (oemb, 0, sizeof(*oemb));
+
+ /* fill out header fields */
+ memcpy(header->signature, "OEMB", 4);
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, "COREBOOT", 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+
+ header->length = sizeof(acpi_oemb_t);
+ header->revision = 1;
+
+ oemb->ss = 0x09; // ss1 + ss 4
+ oemb->iost = 0x0403; // ??
+
+ tolud = pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c);
+ oemb->topm = tolud;
+
+ oemb->roms = 0xfff00000; // 1M hardcoded
+
+ oemb->mg1b = 0x000d0000;
+ oemb->mg1l = 0x00010000;
+
+ oemb->mg2b = tolud;
+ oemb->mg2l = 0-tolud;
+
+ oemb->dmax = 0x87;
+ oemb->hpta = 0x000e36c0;
+
+ header->checksum =
+ acpi_checksum((void *) oemb, sizeof(acpi_oemb_t));
+
+};
+#endif
+
+void acpi_create_gnvs(acpi_gnvs_t *gnvs)
+{
+ memset((void *)gnvs, 0, sizeof(*gnvs));
+ gnvs->mpen = 1;
+}
+
+void acpi_create_intel_hpet(acpi_hpet_t * hpet)
+{
+#define HPET_ADDR 0xfed00000ULL
+ acpi_header_t *header = &(hpet->header);
+ acpi_addr_t *addr = &(hpet->addr);
+
+ memset((void *) hpet, 0, sizeof(acpi_hpet_t));
+
+ /* fill out header fields */
+ memcpy(header->signature, "HPET", 4);
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, "COREBOOT", 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+
+ header->length = sizeof(acpi_hpet_t);
+ header->revision = 1;
+
+ /* fill out HPET address */
+ addr->space_id = 0; /* Memory */
+ addr->bit_width = 64;
+ addr->bit_offset = 0;
+ addr->addrl = HPET_ADDR & 0xffffffff;
+ addr->addrh = HPET_ADDR >> 32;
+
+ hpet->id = 0x8086a201; /* Intel */
+ hpet->number = 0x00;
+ hpet->min_tick = 0x0080;
+
+ header->checksum =
+ acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
+}
+
+#define IO_APIC_ADDR 0xfec00000UL
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* Local APICs */
+ current = acpi_create_madt_lapics(current);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ 2, IO_APIC_ADDR, 0);
+
+ /* INT_SRC_OVR */
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
+
+ return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
+{
+ generate_cpu_entries();
+ return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+ // Not implemented
+ return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+ /* No NUMA, no SRAT */
+ return current;
+}
+
+void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
+
+#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10)
+unsigned long write_acpi_tables(unsigned long start)
+{
+ unsigned long current;
+ int i;
+ acpi_rsdp_t *rsdp;
+ acpi_rsdt_t *rsdt;
+ acpi_hpet_t *hpet;
+ acpi_madt_t *madt;
+ acpi_mcfg_t *mcfg;
+ acpi_fadt_t *fadt;
+ acpi_facs_t *facs;
+#if CONFIG_HAVE_ACPI_SLIC
+ acpi_header_t *slic;
+#endif
+#if OLD_ACPI
+ acpi_oemb_t *oemb;
+#endif
+ acpi_gnvs_t *gnvs;
+ acpi_header_t *ssdt;
+ acpi_header_t *dsdt;
+
+ current = start;
+
+ /* Align ACPI tables to 16byte */
+ ALIGN_CURRENT;
+
+ printk_info("ACPI: Writing ACPI tables at %lx.\n", start);
+
+ /* We need at least an RSDP and an RSDT Table */
+ rsdp = (acpi_rsdp_t *) current;
+ current += sizeof(acpi_rsdp_t);
+ ALIGN_CURRENT;
+ rsdt = (acpi_rsdt_t *) current;
+ current += sizeof(acpi_rsdt_t);
+ ALIGN_CURRENT;
+
+ /* clear all table memory */
+ memset((void *) start, 0, current - start);
+
+ acpi_write_rsdp(rsdp, rsdt, NULL);
+ acpi_write_rsdt(rsdt);
+
+ /*
+ * We explicitly add these tables later on:
+ */
+ printk_debug("ACPI: * HPET\n");
+
+ hpet = (acpi_hpet_t *) current;
+ current += sizeof(acpi_hpet_t);
+ ALIGN_CURRENT;
+ acpi_create_intel_hpet(hpet);
+ acpi_add_table(rsdp, hpet);
+
+ /* If we want to use HPET Timers Linux wants an MADT */
+ printk_debug("ACPI: * MADT\n");
+
+ madt = (acpi_madt_t *) current;
+ acpi_create_madt(madt);
+ current += madt->header.length;
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, madt);
+
+ printk_debug("ACPI: * MCFG\n");
+ mcfg = (acpi_mcfg_t *) current;
+ acpi_create_mcfg(mcfg);
+ current += mcfg->header.length;
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, mcfg);
+
+#if OLD_ACPI
+ printk_debug("ACPI: * OEMB\n");
+ oemb=(acpi_oemb_t *)current;
+ current += sizeof(acpi_oemb_t);
+ ALIGN_CURRENT;
+ acpi_create_oemb(oemb);
+ acpi_add_table(rsdp, oemb);
+#endif
+
+ printk_debug("ACPI: * FACS\n");
+ facs = (acpi_facs_t *) current;
+ current += sizeof(acpi_facs_t);
+ ALIGN_CURRENT;
+ acpi_create_facs(facs);
+
+ dsdt = (acpi_header_t *) current;
+ current += ((acpi_header_t *) AmlCode)->length;
+ memcpy((void *) dsdt, (void *) AmlCode,
+ ((acpi_header_t *) AmlCode)->length);
+
+#if OLD_ACPI
+ for (i=0; i < dsdt->length; i++) {
+ if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBEEF) {
+ printk_debug("ACPI: Patching up DSDT at offset 0x%04x -> 0x%08x\n", i, 0x24 + (u32)oemb);
+ *(u32*)(((u32)dsdt) + i) = 0x24 + (u32)oemb;
+ break;
+ }
+ }
+#endif
+
+ ALIGN_CURRENT;
+
+ /* Pack GNVS into the ACPI table area */
+ for (i=0; i < dsdt->length; i++) {
+ if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
+ printk_debug("ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08x\n", i, current);
+ *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
+ break;
+ }
+ }
+
+ /* And fill it */
+ acpi_create_gnvs(current);
+
+ current += 0x100;
+ ALIGN_CURRENT;
+
+ /* And tell SMI about it */
+ smm_setup_structures((void *)current, NULL, NULL);
+
+ /* We patched up the DSDT, so we need to recalculate the checksum */
+ dsdt->checksum = 0;
+ dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
+
+ printk_debug("ACPI: * DSDT @ %p Length %x\n", dsdt,
+ dsdt->length);
+
+#if CONFIG_HAVE_ACPI_SLIC
+ printk_debug("ACPI: * SLIC\n");
+ slic = (acpi_header_t *)current;
+ current += acpi_create_slic(current);
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, slic);
+#endif
+
+ printk_debug("ACPI: * FADT\n");
+ fadt = (acpi_fadt_t *) current;
+ current += sizeof(acpi_fadt_t);
+ ALIGN_CURRENT;
+
+ acpi_create_fadt(fadt, facs, dsdt);
+ acpi_add_table(rsdp, fadt);
+
+ printk_debug("ACPI: * SSDT\n");
+ ssdt = (acpi_header_t *)current;
+ acpi_create_ssdt_generator(ssdt, "DYNADATA");
+ current += ssdt->length;
+ acpi_add_table(rsdp, ssdt);
+
+ printk_debug("current = %lx\n", current);
+
+ printk_debug("ACPI: * DMI (Linux workaround)\n");
+ memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE);
+#if CONFIG_WRITE_HIGH_TABLES == 1
+ memcpy((void *)current, dmi_table, DMI_TABLE_SIZE);
+ current += DMI_TABLE_SIZE;
+ ALIGN_CURRENT;
+#endif
+
+ printk_info("ACPI: done.\n");
+ return current;
+}
Index: src/mainboard/intel/d945gclf/auto.c
===================================================================
--- src/mainboard/intel/d945gclf/auto.c (revision 0)
+++ src/mainboard/intel/d945gclf/auto.c (revision 0)
@@ -0,0 +1,349 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// __ROMCC__ means: use "unsigned" for device, not a struct.
+#define __ROMCC__
+
+#include <stdint.h>
+#include <string.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+
+#include "superio/smsc/lpc47m15x/lpc47m15x.h"
+
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include <cpu/x86/bist.h>
+
+#if CONFIG_USBDEBUG_DIRECT
+#define DBGP_DEFAULT 1
+#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
+#include "pc80/usbdebug_direct_serial.c"
+#endif
+
+#include "lib/ramtest.c"
+#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
+#include "reset.c"
+#include "superio/smsc/lpc47m15x/lpc47m15x_early_serial.c"
+
+#include "northbridge/intel/i945/udelay.c"
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
+
+#include "southbridge/intel/i82801gx/i82801gx.h"
+static void setup_ich7_gpios(void)
+{
+ /* TODO: This is highly board specific and should be moved */
+ printk_debug(" GPIOS...");
+ /* General Registers */
+ outl(0x3f3df7c1, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
+ outl(0xc6fcbfc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
+ outl(0xecfefdff, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
+ /* Output Control Registers */
+ outl(0x00040000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */
+ /* Input Control Registers */
+ outl(0x0000a000, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
+ outl(0x000000ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
+ outl(0x000000bf, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
+ outl(0x000300fd, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */
+}
+
+#include "northbridge/intel/i945/early_init.c"
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+ return smbus_read_byte(device, address);
+}
+
+#define CHANNEL_XOR_RANDOMIZATION 1
+#include "northbridge/intel/i945/raminit.h"
+#include "northbridge/intel/i945/raminit.c"
+#include "northbridge/intel/i945/reset_test.c"
+#include "northbridge/intel/i945/errata.c"
+#include "debug.c"
+
+static void ich7_enable_lpc(void)
+{
+ // Enable Serial IRQ
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+ // Set COM1/COM2 decode range
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
+ // Enable COM1
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x140d);
+ // Enable SuperIO Power Management Events
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0681);
+}
+
+
+/* This box has two superios, so enabling serial becomes slightly excessive.
+ * We disable a lot of stuff to make sure that there are no conflicts between
+ * the two. Also set up the GPIOs from the beginning. This is the "no schematic
+ * but safe anyways" method.
+ */
+static void early_superio_config_lpc47m15x(void)
+{
+ device_t dev;
+
+ dev=PNP_DEV(0x2e, LPC47M15X_SP1);
+ pnp_enter_conf_state(dev);
+
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
+ pnp_set_irq(dev, PNP_IDX_IRQ0, 4);
+ pnp_set_enable(dev, 1);
+
+ /* Enable SuperIO PM */
+ dev=PNP_DEV(0x2e, LPC47M15X_PME);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, 0x680);
+ pnp_set_enable(dev, 1);
+
+ pnp_exit_conf_state(dev);
+}
+
+static void rcba_config(void)
+{
+ /* Set up virtual channel 0 */
+ //RCBA32(0x0014) = 0x80000001;
+ //RCBA32(0x001c) = 0x03128010;
+
+ /* Device 1f interrupt pin register */
+ RCBA32(0x3100) = 0x00042210;
+ /* Device 1d interrupt pin register */
+ RCBA32(0x310c) = 0x00214321;
+
+ /* dev irq route register */
+ RCBA16(0x3140) = 0x0132;
+ RCBA16(0x3142) = 0x0146;
+ RCBA16(0x3144) = 0x0237;
+ RCBA16(0x3146) = 0x3201;
+ RCBA16(0x3148) = 0x0146;
+
+ /* Enable IOAPIC */
+ RCBA8(0x31ff) = 0x03;
+
+ /* Enable upper 128bytes of CMOS */
+ RCBA32(0x3400) = (1 << 2);
+
+ /* Disable unused devices */
+ //RCBA32(0x3418) = FD_PCIE6|FD_PCIE5|FD_PCIE4|FD_ACMOD|FD_ACAUD|FD_PATA;
+ // RCBA32(0x3418) |= (1 << 0); // Required.
+ // FIXME look me up!
+ RCBA32(0x3418) = 0x003204e1;
+
+ /* Enable PCIe Root Port Clock Gate */
+ // RCBA32(0x341c) = 0x00000001;
+}
+
+static void early_ich7_init(void)
+{
+ uint8_t reg8;
+ uint32_t reg32;
+
+ // program secondary mlt XXX byte?
+ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
+
+ // reset rtc power status
+ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
+ reg8 &= ~(1 << 2);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
+
+ // usb transient disconnect
+ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
+ reg8 |= (3 << 0);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
+
+ reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
+ reg32 |= (1 << 29) | (1 << 17);
+ pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
+
+ reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
+ reg32 |= (1 << 31) | (1 << 27);
+ pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
+
+ RCBA32(0x0088) = 0x0011d000;
+ RCBA16(0x01fc) = 0x060f;
+ RCBA32(0x01f4) = 0x86000040;
+ RCBA32(0x0214) = 0x10030549;
+ RCBA32(0x0218) = 0x00020504;
+ RCBA8(0x0220) = 0xc5;
+ reg32 = RCBA32(0x3410);
+ reg32 |= (1 << 6);
+ RCBA32(0x3410) = reg32;
+ reg32 = RCBA32(0x3430);
+ reg32 &= ~(3 << 0);
+ reg32 |= (1 << 0);
+ RCBA32(0x3430) = reg32;
+ RCBA32(0x3418) |= (1 << 0);
+ RCBA16(0x0200) = 0x2008;
+ RCBA8(0x2027) = 0x0d;
+ RCBA16(0x3e08) |= (1 << 7);
+ RCBA16(0x3e48) |= (1 << 7);
+ RCBA32(0x3e0e) |= (1 << 7);
+ RCBA32(0x3e4e) |= (1 << 7);
+
+ // next step only on ich7m b0 and later:
+ reg32 = RCBA32(0x2034);
+ reg32 &= ~(0x0f << 16);
+ reg32 |= (5 << 16);
+ RCBA32(0x2034) = reg32;
+}
+
+#if CONFIG_USE_FALLBACK_IMAGE == 1
+#include "southbridge/intel/i82801gx/cmos_failover.c"
+#endif
+
+#include <cbmem.h>
+
+// Now, this needs to be included because it relies on the symbol
+// __ROMCC_ being set during CAR stage (in order to compile the
+// BSS free versions of the functions). Either rewrite the code
+// to be always BSS free, or invent a flag that's better suited than
+// __ROMCC__ to determine whether we're in ram init stage (stage 1)
+//
+#include "lib/cbmem.c"
+
+void real_main(unsigned long bist)
+{
+ u32 reg32;
+ int boot_mode = 0;
+
+ if (bist == 0) {
+ enable_lapic();
+ }
+
+ ich7_enable_lpc();
+ early_superio_config_lpc47m15x();
+
+ /* Set up the console */
+ uart_init();
+
+#if CONFIG_USBDEBUG_DIRECT
+ i82801gx_enable_usbdebug_direct(DBGP_DEFAULT);
+ early_usbdebug_direct_init();
+#endif
+
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ if (MCHBAR16(SSKPD) == 0xCAFE) {
+ printk_debug("soft reset detected.\n");
+ boot_mode = 1;
+ }
+
+ /* Perform some early chipset initialization required
+ * before RAM initialization can work
+ */
+ i945_early_initialization();
+
+ /* Read PM1_CNT */
+ reg32 = inl(DEFAULT_PMBASE + 0x04);
+ printk_debug("PM1_CNT: %08x\n", reg32);
+ if (((reg32 >> 10) & 7) == 5) {
+#if CONFIG_HAVE_ACPI_RESUME
+ printk_debug("Resume from S3 detected.\n");
+ boot_mode = 2;
+ /* Clear SLP_TYPE. This will break stage2 but
+ * we care for that when we get there.
+ */
+ outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
+#else
+ printk_debug("Resume from S3 detected, but disabled.\n");
+#endif
+ }
+
+ /* Enable SPD ROMs and DDR-II DRAM */
+ enable_smbus();
+
+#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+ dump_spd_registers();
+#endif
+
+ sdram_initialize(boot_mode);
+
+ /* Perform some initialization that must run before stage2 */
+ early_ich7_init();
+
+ /* This should probably go away. Until now it is required
+ * and mainboard specific
+ */
+ rcba_config();
+
+ /* Chipset Errata! */
+ fixup_i945_errata();
+
+ /* Initialize the internal PCIe links before we go into stage2 */
+ i945_late_initialization();
+
+#if !CONFIG_HAVE_ACPI_RESUME
+#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+#if defined(DEBUG_RAM_SETUP)
+ sdram_dump_mchbar_registers();
+#endif
+
+ {
+ /* This will not work if TSEG is in place! */
+ u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
+
+ printk_debug("TOM: 0x%08x\n", tom);
+ ram_check(0x00000000, 0x000a0000);
+ //ram_check(0x00100000, tom);
+ }
+#endif
+#endif
+
+ MCHBAR16(SSKPD) = 0xCAFE;
+
+#if CONFIG_HAVE_ACPI_RESUME
+ /* Start address of high memory tables */
+ unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE;
+
+ /* If there is no high memory area, we didn't boot before, so
+ * this is not a resume. In that case we just create the cbmem toc.
+ */
+ if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) {
+ void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
+
+ /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
+ * through stage 2. We could keep stuff like stack and heap in high tables
+ * memory completely, but that's a wonderful clean up task for another
+ * day.
+ */
+ if (resume_backup_memory)
+ memcpy(resume_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
+
+ /* Magic for S3 resume */
+ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+ }
+#endif
+}
+
+#include "cpu/intel/model_106cx/cache_as_ram_disable.c"
Index: src/mainboard/intel/d945gclf/dmi.h
===================================================================
--- src/mainboard/intel/d945gclf/dmi.h (revision 0)
+++ src/mainboard/intel/d945gclf/dmi.h (revision 0)
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#define DMI_TABLE_SIZE 0x55
+
+static u8 dmi_table[DMI_TABLE_SIZE] = {
+ 0x5f, 0x53, 0x4d, 0x5f, 0x2d, 0x1f, 0x02, 0x03, 0x51, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x5f, 0x44, 0x4d, 0x49, 0x5f, 0xeb, 0xa8, 0x03, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00,
+ 0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00,
+ 0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20,
+ 0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32,
+ 0x30, 0x30, 0x38, 0x00, 0x00
+};
Index: src/mainboard/intel/d945gclf/fadt.c
===================================================================
--- src/mainboard/intel/d945gclf/fadt.c (revision 0)
+++ src/mainboard/intel/d945gclf/fadt.c (revision 0)
@@ -0,0 +1,167 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <device/pci.h>
+#include <arch/acpi.h>
+
+/* FIXME: This needs to go into a separate .h file
+ * to be included by the ich7 smi handler, ich7 smi init
+ * code and the mainboard fadt.
+ */
+#define APM_CNT 0xb2
+#define CST_CONTROL 0x85
+#define PST_CONTROL 0x80
+#define ACPI_DISABLE 0x1e
+#define ACPI_ENABLE 0xe1
+#define GNVS_UPDATE 0xea
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+ u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe;
+
+ memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
+ header->length = sizeof(acpi_fadt_t);
+ header->revision = 3;
+ memcpy(header->oem_id, "CORE ", 6);
+ memcpy(header->oem_table_id, "COREBOOT", 8);
+ memcpy(header->asl_compiler_id, "CORE", 4);
+ header->asl_compiler_revision = 1;
+
+ fadt->firmware_ctrl = (unsigned long) facs;
+ fadt->dsdt = (unsigned long) dsdt;
+ fadt->model = 1;
+ fadt->preferred_pm_profile = PM_MOBILE;
+
+ fadt->sci_int = 0x9;
+ fadt->smi_cmd = APM_CNT;
+ fadt->acpi_enable = ACPI_ENABLE;
+ fadt->acpi_disable = ACPI_DISABLE;
+ fadt->s4bios_req = 0x0;
+ fadt->pstate_cnt = PST_CONTROL;
+
+ fadt->pm1a_evt_blk = pmbase;
+ fadt->pm1b_evt_blk = 0x0;
+ fadt->pm1a_cnt_blk = pmbase + 0x4;
+ fadt->pm1b_cnt_blk = 0x0;
+ fadt->pm2_cnt_blk = pmbase + 0x20;
+ fadt->pm_tmr_blk = pmbase + 0x8;
+ fadt->gpe0_blk = pmbase + 0x28;
+ fadt->gpe1_blk = 0;
+
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ // XXX: pm2_cnt_len is probably wrong. find out right value (hint: it's != 0)
+ fadt->pm2_cnt_len = 2;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = 8;
+ fadt->gpe1_blk_len = 0;
+ fadt->gpe1_base = 0;
+ fadt->cst_cnt = CST_CONTROL;
+ fadt->p_lvl2_lat = 1;
+ fadt->p_lvl3_lat = 85;
+ fadt->flush_size = 1024;
+ fadt->flush_stride = 16;
+ fadt->duty_offset = 1;
+ fadt->duty_width = 0;
+ fadt->day_alrm = 0xd;
+ fadt->mon_alrm = 0x00;
+ fadt->century = 0x00;
+ fadt->iapc_boot_arch = 0x03;
+
+ fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+ ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
+ ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
+
+ fadt->reset_reg.space_id = 0;
+ fadt->reset_reg.bit_width = 0;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.resv = 0;
+ fadt->reset_reg.addrl = 0x0;
+ fadt->reset_reg.addrh = 0x0;
+
+ fadt->reset_value = 0;
+ fadt->x_firmware_ctl_l = (unsigned long)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (unsigned long)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ fadt->x_pm1a_evt_blk.space_id = 1;
+ fadt->x_pm1a_evt_blk.bit_width = 32;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.resv = 0;
+ fadt->x_pm1a_evt_blk.addrl = pmbase;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_evt_blk.space_id = 1;
+ fadt->x_pm1b_evt_blk.bit_width = 0;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.resv = 0;
+ fadt->x_pm1b_evt_blk.addrl = 0x0;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1a_cnt_blk.space_id = 1;
+ fadt->x_pm1a_cnt_blk.bit_width = 16;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.resv = 0;
+ fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_cnt_blk.space_id = 1;
+ fadt->x_pm1b_cnt_blk.bit_width = 0;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.resv = 0;
+ fadt->x_pm1b_cnt_blk.addrl = 0x0;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm2_cnt_blk.space_id = 1;
+ fadt->x_pm2_cnt_blk.bit_width = 8;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.resv = 0;
+ fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = 32;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.resv = 0;
+ fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+ fadt->x_gpe0_blk.space_id = 1;
+ fadt->x_gpe0_blk.bit_width = 64;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.resv = 0;
+ fadt->x_gpe0_blk.addrl = pmbase + 0x28;
+ fadt->x_gpe0_blk.addrh = 0x0;
+
+ fadt->x_gpe1_blk.space_id = 1;
+ fadt->x_gpe1_blk.bit_width = 0;
+ fadt->x_gpe1_blk.bit_offset = 0;
+ fadt->x_gpe1_blk.resv = 0;
+ fadt->x_gpe1_blk.addrl = 0x0;
+ fadt->x_gpe1_blk.addrh = 0x0;
+
+ header->checksum =
+ acpi_checksum((void *) fadt, header->length);
+}
Index: src/mainboard/intel/d945gclf/Config.lb
===================================================================
--- src/mainboard/intel/d945gclf/Config.lb (revision 0)
+++ src/mainboard/intel/d945gclf/Config.lb (revision 0)
@@ -0,0 +1,237 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+##
+## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
+##
+
+##
+## Only use the option table in a normal image
+##
+default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+
+##
+## Image size calculation
+##
+
+include /config/nofailovercalculation.lb
+
+##
+## Set all of the defaults for an x86 architecture
+##
+
+arch i386 end
+
+##
+## Build the objects we have code for in this directory.
+##
+
+driver mainboard.o
+driver rtl8168.o
+if CONFIG_GENERATE_MP_TABLE object mptable.o end
+if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_SMI_HANDLER smmobject mainboard_smi.o end
+
+if CONFIG_GENERATE_ACPI_TABLES
+ object fadt.o
+ object acpi_tables.o
+ makerule dsdt.c
+ depends "$(CONFIG_MAINBOARD)/dsdt.asl"
+ action "$(CONFIG_CROSS_COMPILE)cpp -D__ACPI__ -P $(CPPFLAGS) -I$(CONFIG_MAINBOARD) $(CONFIG_MAINBOARD)/dsdt.asl -o $(CURDIR)/dsdt.asl"
+ action "iasl -p dsdt -tc $(CURDIR)/dsdt.asl"
+ action "mv $(CURDIR)/dsdt.hex dsdt.c"
+ end
+ object ./dsdt.o
+end
+
+object reset.o
+
+if CONFIG_USE_INIT
+
+makerule ./auto.o
+ depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
+ action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/auto.c -o $@"
+end
+
+else
+
+makerule ./auto.inc
+ depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
+ action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/auto.c -o $@"
+ action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+ action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+end
+
+end
+
+##
+## Build our 16 bit and 32 bit coreboot entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+if CONFIG_USE_INIT
+ ldscript /cpu/x86/32bit/entry32.lds
+ ldscript /cpu/x86/car/cache_as_ram.lds
+end
+
+##
+## Build our reset vector (This is where coreboot is entered)
+##
+if CONFIG_USE_FALLBACK_IMAGE
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
+else
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
+end
+
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
+##
+## Setup Cache-As-Ram
+##
+mainboardinit cpu/intel/model_106cx/cache_as_ram.inc
+
+###
+### This is the early phase of coreboot startup
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+if CONFIG_USE_FALLBACK_IMAGE
+ ldscript /arch/i386/lib/failover.lds
+end
+
+###
+### O.k. We aren't just an intermediary anymore!
+###
+
+if CONFIG_USE_INIT
+initobject auto.o
+else
+mainboardinit ./auto.inc
+end
+
+##
+## Include the secondary Configuration files
+##
+dir /pc80
+config chip.h
+
+chip northbridge/intel/i945
+
+ device apic_cluster 0 on
+ chip cpu/intel/socket_441
+ device apic 0 on end
+ end
+ end
+
+ device pci_domain 0 on
+ device pci 00.0 on end # host bridge
+ device pci 01.0 off end # i945 PCIe root port
+ chip drivers/pci/onboard
+ device pci 02.0 on end # vga controller
+ # register "rom_address" = "0xfffc0000" # 256 KB image
+ # register "rom_address" = "0xfff80000" # 512 KB image
+ # register "rom_address" = "0xfff00000" # 1 MB image
+ end
+ device pci 02.1 on end # display controller
+
+ chip southbridge/intel/i82801gx
+ register "pirqa_routing" = "0x05"
+ register "pirqb_routing" = "0x07"
+ register "pirqc_routing" = "0x05"
+ register "pirqd_routing" = "0x07"
+ register "pirqe_routing" = "0x80"
+ register "pirqf_routing" = "0x80"
+ register "pirqg_routing" = "0x80"
+ register "pirqh_routing" = "0x06"
+
+ # GPI routing
+ # 0 No effect (default)
+ # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+ # 2 SCI (if corresponding GPIO_EN bit is also set)
+ register "gpi13_routing" = "1"
+ register "gpe0_en" = "0x20000601"
+
+ register "ide_legacy_combined" = "0x1"
+ register "ide_enable_primary" = "0x1"
+ register "ide_enable_secondary" = "0x0"
+ register "sata_ahci" = "0x0"
+
+ device pci 1b.0 on end # High Definition Audio
+ device pci 1c.0 on end # PCIe
+ device pci 1c.1 on end # PCIe
+ device pci 1c.2 on end # PCIe
+ #device pci 1c.3 off end # PCIe port 4
+ #device pci 1c.4 off end # PCIe port 5
+ #device pci 1c.5 off end # PCIe port 6
+ device pci 1d.0 on end # USB UHCI
+ device pci 1d.1 on end # USB UHCI
+ device pci 1d.2 on end # USB UHCI
+ device pci 1d.3 on end # USB UHCI
+ device pci 1d.7 on end # USB2 EHCI
+ device pci 1e.0 on end # PCI bridge
+ #device pci 1e.2 off end # AC'97 Audio
+ #device pci 1e.3 off end # AC'97 Modem
+ device pci 1f.0 on # LPC bridge
+ chip superio/smsc/lpc47m15x
+ device pnp 2e.0 off # Floppy
+ end
+ device pnp 2e.3 off # Parport
+ end
+ device pnp 2e.4 on
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.5 on
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq
+ end
+ device pnp 2e.7 on # Keyboard+Mouse
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ irq 0xf0 = 0x82 # HW accel A20.
+ end
+ device pnp 2e.8 on # GAME
+ # all default
+ end
+ device pnp 2e.a on # PME
+ end
+ device pnp 2e.b on # MPU
+ end
+ end
+ end
+ #device pci 1f.1 off end # IDE
+ device pci 1f.2 on end # SATA
+ device pci 1f.3 on end # SMBus
+ #device pci 1f.4 off end # Realtek ID Codec
+ end
+ end
+end
Index: src/mainboard/intel/d945gclf/devicetree.cb
===================================================================
--- src/mainboard/intel/d945gclf/devicetree.cb (revision 0)
+++ src/mainboard/intel/d945gclf/devicetree.cb (revision 0)
@@ -0,0 +1,115 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+chip northbridge/intel/i945
+
+ device apic_cluster 0 on
+ chip cpu/intel/socket_441
+ device apic 0 on end
+ end
+ end
+
+ device pci_domain 0 on
+ device pci 00.0 on end # host bridge
+ device pci 01.0 off end # i945 PCIe root port
+ chip drivers/pci/onboard
+ device pci 02.0 on end # vga controller
+ # register "rom_address" = "0xfffc0000" # 256 KB image
+ # register "rom_address" = "0xfff80000" # 512 KB image
+ # register "rom_address" = "0xfff00000" # 1 MB image
+ end
+ device pci 02.1 on end # display controller
+
+ chip southbridge/intel/i82801gx
+ register "pirqa_routing" = "0x05"
+ register "pirqb_routing" = "0x07"
+ register "pirqc_routing" = "0x05"
+ register "pirqd_routing" = "0x07"
+ register "pirqe_routing" = "0x80"
+ register "pirqf_routing" = "0x80"
+ register "pirqg_routing" = "0x80"
+ register "pirqh_routing" = "0x06"
+
+ # GPI routing
+ # 0 No effect (default)
+ # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+ # 2 SCI (if corresponding GPIO_EN bit is also set)
+ register "gpi13_routing" = "1"
+ register "gpe0_en" = "0x20000601"
+
+ register "ide_legacy_combined" = "0x1"
+ register "ide_enable_primary" = "0x1"
+ register "ide_enable_secondary" = "0x0"
+ register "sata_ahci" = "0x0"
+
+ device pci 1b.0 on end # High Definition Audio
+ device pci 1c.0 on end # PCIe
+ device pci 1c.1 on end # PCIe
+ device pci 1c.2 on end # PCIe
+ #device pci 1c.3 off end # PCIe port 4
+ #device pci 1c.4 off end # PCIe port 5
+ #device pci 1c.5 off end # PCIe port 6
+ device pci 1d.0 on end # USB UHCI
+ device pci 1d.1 on end # USB UHCI
+ device pci 1d.2 on end # USB UHCI
+ device pci 1d.3 on end # USB UHCI
+ device pci 1d.7 on end # USB2 EHCI
+ device pci 1e.0 on end # PCI bridge
+ #device pci 1e.2 off end # AC'97 Audio
+ #device pci 1e.3 off end # AC'97 Modem
+ device pci 1f.0 on # LPC bridge
+ chip superio/smsc/lpc47m15x
+ device pnp 2e.0 off # Floppy
+ end
+ device pnp 2e.3 off # Parport
+ end
+ device pnp 2e.4 on
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.5 on
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq
+ end
+ device pnp 2e.7 on # Keyboard+Mouse
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ irq 0xf0 = 0x82 # HW accel A20.
+ end
+ device pnp 2e.8 on # GAME
+ # all default
+ end
+ device pnp 2e.a on # PME
+ end
+ device pnp 2e.b on # MPU
+ end
+ end
+ end
+ #device pci 1f.1 off end # IDE
+ device pci 1f.2 on end # SATA
+ device pci 1f.3 on end # SMBus
+ #device pci 1f.4 off end # Realtek ID Codec
+ end
+ end
+end
Index: src/mainboard/intel/d945gclf/reset.c
===================================================================
--- src/mainboard/intel/d945gclf/reset.c (revision 0)
+++ src/mainboard/intel/d945gclf/reset.c (revision 0)
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+
+void soft_reset(void)
+{
+ outb(0x04, 0xcf9);
+}
+
+void hard_reset(void)
+{
+ outb(0x02, 0xcf9);
+ outb(0x06, 0xcf9);
+}
Index: src/mainboard/intel/d945gclf/mptable.c
===================================================================
--- src/mainboard/intel/d945gclf/mptable.c (revision 0)
+++ src/mainboard/intel/d945gclf/mptable.c (revision 0)
@@ -0,0 +1,137 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <string.h>
+#include <stdint.h>
+
+void *smp_write_config_table(void *v)
+{
+ static const char sig[4] = "PCMP";
+ static const char oem[8] = "COREBOOT";
+ static const char productid[12] = "D945GCLF ";
+ struct mp_config_table *mc;
+ int i;
+ int max_pci_bus, isa_bus;
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+ memset(mc, 0, sizeof(*mc));
+
+ memcpy(mc->mpc_signature, sig, sizeof(sig));
+ mc->mpc_length = sizeof(*mc); /* initially just the header */
+ mc->mpc_spec = 0x04;
+ mc->mpc_checksum = 0; /* not yet computed */
+ memcpy(mc->mpc_oem, oem, sizeof(oem));
+ memcpy(mc->mpc_productid, productid, sizeof(productid));
+ mc->mpc_oemptr = 0;
+ mc->mpc_oemsize = 0;
+ mc->mpc_entry_count = 0; /* No entries yet... */
+ mc->mpc_lapic = LAPIC_ADDR;
+ mc->mpe_length = 0;
+ mc->mpe_checksum = 0;
+ mc->reserved = 0;
+
+ smp_write_processors(mc);
+
+ max_pci_bus = 5; // XXX read me from bridges.
+
+ /* ISA bus follows */
+ isa_bus = max_pci_bus + 1;
+
+ /* Bus: Bus ID Type */
+ for (i=0; i <= max_pci_bus; i++)
+ smp_write_bus(mc, i, "PCI ");
+
+ smp_write_bus(mc, isa_bus, "ISA ");
+
+ /* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
+
+ /* Legacy Interrupts */
+
+ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x0);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x1, 0x2, 0x1);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x2);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x3, 0x2, 0x3);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x4, 0x2, 0x4);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x8, 0x2, 0x8);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x9, 0x2, 0x9);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xa, 0x2, 0xa);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xb, 0x2, 0xb);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xc, 0x2, 0xc);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xd, 0x2, 0xd);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xe, 0x2, 0xe);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xf, 0x2, 0xf);
+
+ /* Builtin devices on Bus 0 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x17);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, 0x11);
+
+ /* Firewire 4:0.0 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, 0x10);
+
+ /* Old riser card */
+ // riser slot top 5:8.0
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, 0x14);
+ // riser slot middle 5:9.0
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2, 0x15);
+ // riser slot bottom 5:a.0
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, 0x16);
+
+ /* New Riser Card */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x30, 0x2, 0x14);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x34, 0x2, 0x15);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x38, 0x2, 0x16);
+
+ /* Onboard Ethernet */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
+
+ /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0);
+ smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1);
+
+ /* Compute the checksums */
+ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+ mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+
+ printk_debug("Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
+
+ return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr);
+ return (unsigned long)smp_write_config_table(v);
+}
Index: src/mainboard/intel/d945gclf/irq_tables.c
===================================================================
--- src/mainboard/intel/d945gclf/irq_tables.c (revision 0)
+++ src/mainboard/intel/d945gclf/irq_tables.c (revision 0)
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32+16*18, /* There can be total 18 devices on the bus */
+ 0x00, /* Where the interrupt router lies (bus) */
+ (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */
+ 0, /* IRQs devoted exclusively to PCI usage */
+ 0x8086, /* Vendor */
+ 0x27b0, /* Device */
+ 0, /* miniport */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0xf, /* u8 checksum. */
+ {
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00,(0x01<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
+ {0x00,(0x02<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
+ {0x00,(0x1e<<3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge
+ {0x00,(0x1f<<3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC
+ {0x00,(0x1d<<3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1
+ {0x00,(0x1b<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device
+ {0x00,(0x1c<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge
+ {0x04,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire
+ {0x04,(0x01<<3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge
+ {0x04,(0x02<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
+ {0x04,(0x03<<3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
+ {0x04,(0x04<<3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
+ {0x04,(0x05<<3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
+ {0x04,(0x06<<3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
+ {0x04,(0x09<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
+ {0x01,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168
+ {0x02,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
+ {0x03,(0x00<<3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
+ }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr);
+}
+
Index: src/mainboard/intel/d945gclf/debug.c
===================================================================
--- src/mainboard/intel/d945gclf/debug.c (revision 0)
+++ src/mainboard/intel/d945gclf/debug.c (revision 0)
@@ -0,0 +1,128 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#define SMBUS_MEM_DEVICE_START 0x50
+#define SMBUS_MEM_DEVICE_END 0x53
+#define SMBUS_MEM_DEVICE_INC 1
+
+static void print_pci_devices(void)
+{
+ device_t dev;
+ for(dev = PCI_DEV(0, 0, 0);
+ dev <= PCI_DEV(0, 0x1f, 0x7);
+ dev += PCI_DEV(0,0,1)) {
+ uint32_t id;
+ id = pci_read_config32(dev, PCI_VENDOR_ID);
+ if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
+ (((id >> 16) & 0xffff) == 0xffff) ||
+ (((id >> 16) & 0xffff) == 0x0000)) {
+ continue;
+ }
+ printk_debug("PCI: %02x:%02x.%02x", (dev >> 20) & 0xff,
+ (dev >> 15) & 0x1f, (dev >> 12) & 7);
+ printk_debug(" [%04x:%04x]\r\n", id &0xffff, id >> 16);
+ }
+}
+
+static void dump_pci_device(unsigned dev)
+{
+ int i;
+
+ printk_debug("PCI: %02x:%02x.%02x\r\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7);
+
+ for(i = 0; i <= 255; i++) {
+ unsigned char val;
+ if ((i & 0x0f) == 0) {
+ printk_debug("%02x:", i);
+ }
+ val = pci_read_config8(dev, i);
+ printk_debug(" %02x", val);
+ if ((i & 0x0f) == 0x0f) {
+ printk_debug("\r\n");
+ }
+ }
+}
+
+static void dump_pci_devices(void)
+{
+ device_t dev;
+ for(dev = PCI_DEV(0, 0, 0);
+ dev <= PCI_DEV(0, 0x1f, 0x7);
+ dev += PCI_DEV(0,0,1)) {
+ uint32_t id;
+ id = pci_read_config32(dev, PCI_VENDOR_ID);
+ if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
+ (((id >> 16) & 0xffff) == 0xffff) ||
+ (((id >> 16) & 0xffff) == 0x0000)) {
+ continue;
+ }
+ dump_pci_device(dev);
+ }
+}
+
+void dump_spd_registers(void)
+{
+ unsigned device;
+ device = SMBUS_MEM_DEVICE_START;
+ while(device <= SMBUS_MEM_DEVICE_END) {
+ int status = 0;
+ int i;
+ printk_debug("\r\ndimm %02x", device);
+
+ for(i = 0; (i < 256) ; i++) {
+ if ((i % 16) == 0) {
+ printk_debug("\r\n%02x: ", i);
+ }
+ status = smbus_read_byte(device, i);
+ if (status < 0) {
+ printk_debug("bad device: %02x\r\n", -status);
+ break;
+ }
+ printk_debug("%02x ", status);
+ }
+ device += SMBUS_MEM_DEVICE_INC;
+ printk_debug("\r\n");
+ }
+}
+
+static void dump_mem(unsigned start, unsigned end)
+{
+ unsigned i;
+ print_debug("dump_mem:");
+ for(i=start;i<end;i++) {
+ if((i & 0xf)==0) {
+#if CONFIG_USE_INIT
+ printk_debug("\r\n%08x:", i);
+#else
+ print_debug("\r\n");
+ print_debug_hex32(i);
+ print_debug(":");
+#endif
+ }
+#if CONFIG_USE_INIT
+ printk_debug(" %02x", (unsigned char)*((unsigned char *)i));
+#else
+ print_debug(" ");
+ print_debug_hex8((unsigned char)*((unsigned char *)i));
+#endif
+ }
+ print_debug("\r\n");
+ }
Index: src/mainboard/intel/d945gclf/chip.h
===================================================================
--- src/mainboard/intel/d945gclf/chip.h (revision 0)
+++ src/mainboard/intel/d945gclf/chip.h (revision 0)
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+struct mainboard_config {
+ int nothing;
+};
Index: src/mainboard/intel/d945gclf/rtl8168.c
===================================================================
--- src/mainboard/intel/d945gclf/rtl8168.c (revision 0)
+++ src/mainboard/intel/d945gclf/rtl8168.c (revision 0)
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This code should work for all ICH* southbridges with a NIC. */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+static void nic_init(struct device *dev)
+{
+ printk_debug("Initializing RTL8168 Gigabit Ethernet\n");
+ // Nothing to do yet, but this has to be here to keep
+ // coreboot from trying to execute an option ROM.
+}
+
+static struct device_operations nic_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = nic_init,
+ .scan_bus = 0,
+};
+
+static const struct pci_driver rtl8169_nic __pci_driver = {
+ .ops = &nic_ops,
+ .vendor = 0x10ec,
+ .device = 0x8168,
+};
+
+
Index: src/mainboard/intel/d945gclf/dsdt.asl
===================================================================
--- src/mainboard/intel/d945gclf/dsdt.asl (revision 0)
+++ src/mainboard/intel/d945gclf/dsdt.asl (revision 0)
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0
+ "COREv2", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20090419 // OEM revision
+)
+{
+ // Some generic macros
+ #include "acpi/platform.asl"
+
+ // global NVS and variables
+ #include "../../../southbridge/intel/i82801gx/acpi/globalnvs.asl"
+
+ // General Purpose Events
+ //#include "acpi/gpe.asl"
+
+ // mainboard specific devices
+ #include "acpi/mainboard.asl"
+
+ // Thermal Zone
+ //#include "acpi/thermal.asl"
+
+ Scope (_SB) {
+ Device (PCI0)
+ {
+ #include "../../../northbridge/intel/i945/acpi/i945.asl"
+ #include "../../../southbridge/intel/i82801gx/acpi/ich7.asl"
+ }
+ }
+
+ /* Chipset specific sleep states */
+ #include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl"
+}
Index: src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl
===================================================================
--- src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl (revision 0)
+++ src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl (revision 0)
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for the
+ * i945
+ */
+
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+ If (PICM) {
+ Return (Package() {
+ // PCIe Graphics 0:1.0
+ Package() { 0x0001ffff, 0, 0, 16 },
+ Package() { 0x0001ffff, 1, 0, 17 },
+ Package() { 0x0001ffff, 2, 0, 18 },
+ Package() { 0x0001ffff, 3, 0, 19 },
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, 0, 16 },
+ // High Definition Audio 0:1b.0
+ Package() { 0x001bffff, 0, 0, 22 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, 0, 17 },
+ Package() { 0x001cffff, 1, 0, 16 },
+ Package() { 0x001cffff, 2, 0, 18 },
+ Package() { 0x001cffff, 3, 0, 19 },
+ // USB and EHCI 0:1d.x
+ Package() { 0x001dffff, 0, 0, 23 },
+ Package() { 0x001dffff, 1, 0, 19 },
+ Package() { 0x001dffff, 2, 0, 18 },
+ Package() { 0x001dffff, 3, 0, 16 },
+ // AC97 0:1e.2, 0:1e.3
+ Package() { 0x001effff, 0, 0, 22 },
+ Package() { 0x001effff, 1, 0, 20 },
+ // LPC device 0:1f.0
+ Package() { 0x001fffff, 0, 0, 18 },
+ Package() { 0x001fffff, 1, 0, 19 },
+ })
+ } Else {
+ Return (Package() {
+ // PCIe Graphics 0:1.0
+ Package() { 0x0001ffff, 0, _SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x0001ffff, 1, _SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x0001ffff, 2, _SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x0001ffff, 3, _SB.PCI0.LPCB.LNKD, 0 },
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, _SB.PCI0.LPCB.LNKA, 0 },
+ // High Definition Audio 0:1b.0
+ Package() { 0x001bffff, 0, _SB.PCI0.LPCB.LNKF, 0 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, _SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001cffff, 1, _SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x001cffff, 2, _SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x001cffff, 3, _SB.PCI0.LPCB.LNKD, 0 },
+ // USB and EHCI 0:1d.x
+ Package() { 0x001dffff, 0, _SB.PCI0.LPCB.LNKH, 0 },
+ Package() { 0x001dffff, 1, _SB.PCI0.LPCB.LNKD, 0 },
+ Package() { 0x001dffff, 2, _SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x001dffff, 3, _SB.PCI0.LPCB.LNKA, 0 },
+ // AC97 0:1e.2, 0:1e.3
+ Package() { 0x001effff, 0, _SB.PCI0.LPCB.LNKG, 0 },
+ Package() { 0x001effff, 1, _SB.PCI0.LPCB.LNKE, 0 },
+ // LPC device 0:1f.0
+ Package() { 0x001fffff, 0, _SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x001fffff, 1, _SB.PCI0.LPCB.LNKD, 0 },
+ })
+ }
+}
+
Index: src/mainboard/intel/d945gclf/acpi/ich7_pci_irqs.asl
===================================================================
--- src/mainboard/intel/d945gclf/acpi/ich7_pci_irqs.asl (revision 0)
+++ src/mainboard/intel/d945gclf/acpi/ich7_pci_irqs.asl (revision 0)
@@ -0,0 +1,85 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for the
+ * 0:1e.0 PCI bridge of the ICH7
+ */
+
+If (PICM) {
+ Return (Package() {
+ Package() { 0x0000ffff, 0, 0, 21},
+ Package() { 0x0000ffff, 1, 0, 22},
+ Package() { 0x0000ffff, 2, 0, 23},
+ Package() { 0x0000ffff, 3, 0, 20},
+
+ Package() { 0x0001ffff, 0, 0, 22},
+ Package() { 0x0001ffff, 1, 0, 21},
+ Package() { 0x0001ffff, 2, 0, 20},
+ Package() { 0x0001ffff, 3, 0, 23},
+
+ Package() { 0x0002ffff, 0, 0, 18},
+ Package() { 0x0002ffff, 1, 0, 19},
+ Package() { 0x0002ffff, 2, 0, 17},
+ Package() { 0x0002ffff, 3, 0, 16},
+
+ Package() { 0x0003ffff, 0, 0, 19},
+ Package() { 0x0003ffff, 1, 0, 18},
+ Package() { 0x0003ffff, 2, 0, 21},
+ Package() { 0x0003ffff, 3, 0, 22},
+
+ Package() { 0x0005ffff, 0, 0, 17},
+ Package() { 0x0005ffff, 1, 0, 20},
+ Package() { 0x0005ffff, 2, 0, 22},
+ Package() { 0x0005ffff, 3, 0, 21},
+
+ Package() { 0x0008ffff, 0, 0, 20},
+ })
+} Else {
+ Return (Package() {
+ Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKF, 0},
+ Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKG, 0},
+ Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKH, 0},
+ Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKE, 0},
+
+ Package() { 0x0001ffff, 0, _SB.PCI0.LPCB.LNKG, 0},
+ Package() { 0x0001ffff, 1, _SB.PCI0.LPCB.LNKF, 0},
+ Package() { 0x0001ffff, 2, _SB.PCI0.LPCB.LNKE, 0},
+ Package() { 0x0001ffff, 3, _SB.PCI0.LPCB.LNKH, 0},
+
+ Package() { 0x0002ffff, 0, _SB.PCI0.LPCB.LNKC, 0},
+ Package() { 0x0002ffff, 1, _SB.PCI0.LPCB.LNKD, 0},
+ Package() { 0x0002ffff, 2, _SB.PCI0.LPCB.LNKB, 0},
+ Package() { 0x0002ffff, 3, _SB.PCI0.LPCB.LNKA, 0},
+
+ Package() { 0x0003ffff, 0, _SB.PCI0.LPCB.LNKD, 0},
+ Package() { 0x0003ffff, 1, _SB.PCI0.LPCB.LNKC, 0},
+ Package() { 0x0003ffff, 2, _SB.PCI0.LPCB.LNKF, 0},
+ Package() { 0x0003ffff, 3, _SB.PCI0.LPCB.LNKG, 0},
+
+ Package() { 0x0005ffff, 0, _SB.PCI0.LPCB.LNKB, 0},
+ Package() { 0x0005ffff, 1, _SB.PCI0.LPCB.LNKE, 0},
+ Package() { 0x0005ffff, 2, _SB.PCI0.LPCB.LNKG, 0},
+ Package() { 0x0005ffff, 3, _SB.PCI0.LPCB.LNKF, 0},
+
+ Package() { 0x0008ffff, 0, _SB.PCI0.LPCB.LNKE, 0},
+ })
+}
+
Index: src/mainboard/intel/d945gclf/acpi/platform.asl
===================================================================
--- src/mainboard/intel/d945gclf/acpi/platform.asl (revision 0)
+++ src/mainboard/intel/d945gclf/acpi/platform.asl (revision 0)
@@ -0,0 +1,93 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+ APMC, 8, // APM command
+ APMS, 8 // APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+ DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+ Store (Arg0, SMIF) // SMI Function
+ Store (0, TRP0) // Generate trap
+ Return (SMIF) // Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+ // Remember the OS' IRQ routing choice.
+ Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+ // Call a trap so SMI can prepare for Sleep as well.
+ // TRAP(0x55)
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ // CPU specific part
+
+ // Notify PCI Express slots in case a card
+ // was inserted while a sleep state was active.
+
+ // Are we going to S3?
+ If (LEqual(Arg0, 3)) {
+ // ..
+ }
+
+ // Are we going to S4?
+ If (LEqual(Arg0, 4)) {
+ // ..
+ }
+
+ // TODO: Windows XP SP2 P-State restore
+
+ Return(Package(){0,0})
+}
+
Index: src/mainboard/intel/d945gclf/acpi/superio.asl
===================================================================
--- src/mainboard/intel/d945gclf/acpi/superio.asl (revision 0)
+++ src/mainboard/intel/d945gclf/acpi/superio.asl (revision 0)
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+
+Device (SIO1)
+{
+ Name (_HID, EISAID("PNP0A05"))
+ Name (_UID, 1)
+
+ Device (UAR1)
+ {
+ Name(_HID, EISAID("PNP0501"))
+ Name(_UID, 1)
+
+ // Some methods need an implementation here:
+ // missing: _STA, _DIS, _CRS, _PRS,
+ // missing: _SRS, _PS0, _PS3
+ }
+
+ Device (UAR2)
+ {
+ Name(_HID, EISAID("PNP0501"))
+ Name(_UID, 2)
+
+ // Some methods need an implementation here:
+ // missing: _STA, _DIS, _CRS, _PRS,
+ // missing: _SRS, _PS0, _PS3
+ }
+}
+
Index: src/mainboard/intel/d945gclf/acpi/video.asl
===================================================================
--- src/mainboard/intel/d945gclf/acpi/video.asl (revision 0)
+++ src/mainboard/intel/d945gclf/acpi/video.asl (revision 0)
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// Brightness write
+Method (BRTW, 1, Serialized)
+{
+ // TODO
+}
+
+// Hot Key Display Switch
+Method (HKDS, 1, Serialized)
+{
+ // TODO
+}
+
+// Lid Switch Display Switch
+Method (LSDS, 1, Serialized)
+{
+ // TODO
+}
+
+// Brightness Notification
+Method(BRTN,1,Serialized)
+{
+ // TODO (no displays defined yet)
+}
+
Index: src/mainboard/intel/d945gclf/acpi/ec.asl
===================================================================
--- src/mainboard/intel/d945gclf/acpi/ec.asl (revision 0)
+++ src/mainboard/intel/d945gclf/acpi/ec.asl (revision 0)
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Device(EC0)
+{
+ Name (_HID, EISAID("PNP0C09"))
+ Name (_UID, 1)
+
+ Method (_CRS, 0)
+ {
+ Name (ECMD, ResourceTemplate()
+ {
+ IO (Decode16, 0x62, 0x62, 0, 1)
+ IO (Decode16, 0x66, 0x66, 0, 1)
+ })
+
+ Return (ECMD)
+ }
+
+ Method (_REG, 2)
+ {
+ // This method is needed by Windows XP/2000
+ // for EC initialization before a driver
+ // is loaded
+ }
+
+ Name (_GPE, 23) // GPI07 / GPE23 -> Runtime SCI
+
+ // TODO EC Query methods
+
+ // TODO Scope _SB devices for AC power, LID, Power button
+
+}
Index: src/mainboard/intel/d945gclf/acpi/mainboard.asl
===================================================================
--- src/mainboard/intel/d945gclf/acpi/mainboard.asl (revision 0)
+++ src/mainboard/intel/d945gclf/acpi/mainboard.asl (revision 0)
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Device (SLPB)
+{
+ Name(_HID, EisaId("PNP0C0E"))
+
+ // Wake
+ Name(_PRW, Package(){0x1d, 0x04})
+}
+
+Device (PWRB)
+{
+ Name(_HID, EisaId("PNP0C0C"))
+
+ // Wake
+ Name(_PRW, Package(){0x1d, 0x04})
+}
+
Index: src/mainboard/intel/d945gclf/acpi/thermal.asl
===================================================================
--- src/mainboard/intel/d945gclf/acpi/thermal.asl (revision 0)
+++ src/mainboard/intel/d945gclf/acpi/thermal.asl (revision 0)
@@ -0,0 +1,96 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// Thermal Zone
+
+Scope (_TZ)
+{
+ ThermalZone (THRM)
+ {
+
+ // FIXME these could/should be read from the
+ // GNVS area, so they can be controlled by
+ // coreboot
+ Name(TC1V, 0x04)
+ Name(TC2V, 0x03)
+ Name(TSPV, 0x64)
+
+ // At which temperature should the OS start
+ // active cooling?
+ Method (_AC0, 0, Serialized)
+ {
+ Return (0xf5c) // Value for Rocky
+ }
+
+ // Method (_AC1, 0, Serialized)
+ // {
+ // Return (0xf5c)
+ // }
+
+ // Critical shutdown temperature
+ Method (_CRT, 0, Serialized)
+ {
+ Return (Add (0x0aac, 0x50)) // FIXME
+ }
+
+ // CPU throttling start temperature
+ Method (_PSV, 0, Serialized)
+ {
+ Return (0xaaf) // FIXME
+ }
+
+ // Get DTS Temperature
+ Method (_TMP, 0, Serialized)
+ {
+ Return (0xaac) // FIXME
+ }
+
+ // Processors used for active cooling
+ Method (_PSL, 0, Serialized)
+ {
+ If (MPEN) {
+ Return (Package() {_PR.CPU1, _PR.CPU2})
+ }
+ Return (Package() {_PR.CPU1})
+ }
+
+ // TC1 value for passive cooling
+ Method (_TC1, 0, Serialized)
+ {
+ Return (TC1V)
+ }
+
+ // TC2 value for passive cooling
+ Method (_TC2, 0, Serialized)
+ {
+ Return (TC2V)
+ }
+
+ // Sampling period for passive cooling
+ Method (_TSP, 0, Serialized)
+ {
+ Return (TSPV)
+ }
+
+
+ }
+}
+
Index: src/mainboard/intel/d945gclf/power_reset_check.c
===================================================================
--- src/mainboard/intel/d945gclf/power_reset_check.c (revision 0)
+++ src/mainboard/intel/d945gclf/power_reset_check.c (revision 0)
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+
+static void power_down_reset_check(void)
+{
+ uint8_t cmos;
+
+ cmos=cmos_read(RTC_BOOT_BYTE)>>4 ;
+ printk_debug("Boot byte = %x\r\n", cmos);
+
+ if((cmos>2)&&(cmos&1)) full_reset();
+}
Index: src/mainboard/intel/d945gclf/mainboard.c
===================================================================
--- src/mainboard/intel/d945gclf/mainboard.c (revision 0)
+++ src/mainboard/intel/d945gclf/mainboard.c (revision 0)
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+
+#include <device/device.h>
+#include <console/console.h>
+#include <boot/tables.h>
+#include "chip.h"
+
+int add_northbridge_resources(struct lb_memory *mem);
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return add_northbridge_resources(mem);
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Intel D945GCLF Mainboard")
+};
+
Index: src/mainboard/intel/d945gclf/cmos.layout
===================================================================
--- src/mainboard/intel/d945gclf/cmos.layout (revision 0)
+++ src/mainboard/intel/d945gclf/cmos.layout (revision 0)
@@ -0,0 +1,144 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2007-2008 coresystems GmbH
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; version 2 of
+# the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+# -----------------------------------------------------------------
+# Status Register A
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+388 4 r 0 reboot_bits
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 e 5 baud_rate
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+# coreboot config options: cpu
+400 1 e 2 hyper_threading
+#401 7 r 0 unused
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+#411 5 r 0 unused
+
+# coreboot config options: bootloader
+416 512 s 0 boot_devices
+#928 80 r 0 unused
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+#1000 24 r 0 amd_reserved
+
+# ram initialization internal data
+1024 8 r 0 C0WL0REOST
+1032 8 r 0 C1WL0REOST
+1040 8 r 0 RCVENMT
+1048 4 r 0 C0DRT1
+1052 4 r 0 C1DRT1
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 983 984
+
+
Index: targets/intel/d945gclf/Config-abuild.lb
===================================================================
--- targets/intel/d945gclf/Config-abuild.lb (revision 0)
+++ targets/intel/d945gclf/Config-abuild.lb (revision 0)
@@ -0,0 +1,29 @@
+# This will make a target directory of ./VENDOR_MAINBOARD
+
+target VENDOR_MAINBOARD
+mainboard VENDOR/MAINBOARD
+
+option CC="CROSSCC"
+option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
+option HOSTCC="CROSS_HOSTCC"
+
+__COMPRESSION__
+__LOGLEVEL__
+
+option CONFIG_ROM_SIZE=512*1024
+
+romimage "normal"
+ option CONFIG_USE_FALLBACK_IMAGE=0
+ option COREBOOT_EXTRA_VERSION=".0-normal"
+ payload __PAYLOAD__
+end
+
+romimage "fallback"
+ option CONFIG_USE_FALLBACK_IMAGE=1
+ option COREBOOT_EXTRA_VERSION=".0-fallback"
+ payload __PAYLOAD__
+end
+
+buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
+pci_rom ../../../misc/d945gclf-pci8086,2772.rom vendor_id=0x8086 device_id=0x2772
+
28 Oct
28 Oct
10 a.m.
ron minnich wrote:
Acked-by: Ronald G. Minnich rminnich@gmail.com
thanks, r4879
--
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: info@coresystems.de • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
2 Nov
2 Nov
6:33 a.m.
If anyone does want to work on the D945GCLF board then you need to update the sdram_enable_memory_clocks in northbridge/intel/i945/raminit.c in a way that does not break the mobile version. The desktop version of the chipset has more clocks and so uses more bits in C0DCLKDIS and C1DCLKDIS to control them. Instead of bits 0&1 and 2&3, you need to use bits 0&1&2 and 3&4&5. A quick and dirty hack to get this going would seem to be to define OVERRIDE_CLOCK_DISABLE.
Sorry but I don't have time to do this myself but I thought the information might be useful to somebody. It should be enough to get RAM init working.
Andrew
5499
days inactive
5506
days old
3 comments
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participants (3)
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Andrew Goodbody -
ron minnich -
Stefan Reinauer